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Merge branch 'linus' into cpumask-for-linus
[linux-2.6/verdex.git] / arch / x86 / include / asm / processor.h
blob34c52370f2fe848a2e7c9dcb73fdc4a3048c087f
1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
21 #include <asm/msr.h>
22 #include <asm/desc_defs.h>
23 #include <asm/nops.h>
24 #include <asm/ds.h>
25
26 #include <linux/personality.h>
27 #include <linux/cpumask.h>
28 #include <linux/cache.h>
29 #include <linux/threads.h>
30 #include <linux/init.h>
31
32 /*
33 * Default implementation of macro that returns current
34 * instruction pointer ("program counter").
35 */
36 static inline void *current_text_addr(void)
37 {
38 void *pc;
39
40 asm volatile("mov $1f, %0; 1:":"=r" (pc));
41
42 return pc;
43 }
44
45 #ifdef CONFIG_X86_VSMP
46 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
47 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
48 #else
49 # define ARCH_MIN_TASKALIGN 16
50 # define ARCH_MIN_MMSTRUCT_ALIGN 0
51 #endif
52
53 /*
54 * CPU type and hardware bug flags. Kept separately for each CPU.
55 * Members of this structure are referenced in head.S, so think twice
56 * before touching them. [mj]
57 */
58
59 struct cpuinfo_x86 {
60 __u8 x86; /* CPU family */
61 __u8 x86_vendor; /* CPU vendor */
62 __u8 x86_model;
63 __u8 x86_mask;
64 #ifdef CONFIG_X86_32
65 char wp_works_ok; /* It doesn't on 386's */
66
67 /* Problems on some 486Dx4's and old 386's: */
68 char hlt_works_ok;
69 char hard_math;
70 char rfu;
71 char fdiv_bug;
72 char f00f_bug;
73 char coma_bug;
74 char pad0;
75 #else
76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
77 int x86_tlbsize;
78 #endif
79 __u8 x86_virt_bits;
80 __u8 x86_phys_bits;
81 /* CPUID returned core id bits: */
82 __u8 x86_coreid_bits;
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
85 /* Maximum supported CPUID level, -1=no CPUID: */
86 int cpuid_level;
87 __u32 x86_capability[NCAPINTS];
88 char x86_vendor_id[16];
89 char x86_model_id[64];
90 /* in KB - valid for CPUS which support this call: */
91 int x86_cache_size;
92 int x86_cache_alignment; /* In bytes */
93 int x86_power;
94 unsigned long loops_per_jiffy;
95 #ifdef CONFIG_SMP
96 /* cpus sharing the last level cache: */
97 cpumask_var_t llc_shared_map;
98 #endif
99 /* cpuid returned max cores value: */
100 u16 x86_max_cores;
101 u16 apicid;
102 u16 initial_apicid;
103 u16 x86_clflush_size;
104 #ifdef CONFIG_SMP
105 /* number of cores as seen by the OS: */
106 u16 booted_cores;
107 /* Physical processor id: */
108 u16 phys_proc_id;
109 /* Core id: */
110 u16 cpu_core_id;
111 /* Index into per_cpu list: */
112 u16 cpu_index;
113 #endif
114 unsigned int x86_hyper_vendor;
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
116
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_CENTAUR 5
122 #define X86_VENDOR_TRANSMETA 7
123 #define X86_VENDOR_NSC 8
124 #define X86_VENDOR_NUM 9
125
126 #define X86_VENDOR_UNKNOWN 0xff
127
128 #define X86_HYPER_VENDOR_NONE 0
129 #define X86_HYPER_VENDOR_VMWARE 1
130
131 /*
132 * capabilities of CPUs
133 */
134 extern struct cpuinfo_x86 boot_cpu_data;
135 extern struct cpuinfo_x86 new_cpu_data;
136
137 extern struct tss_struct doublefault_tss;
138 extern __u32 cleared_cpu_caps[NCAPINTS];
139
140 #ifdef CONFIG_SMP
141 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
142 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
143 #define current_cpu_data __get_cpu_var(cpu_info)
144 #else
145 #define cpu_data(cpu) boot_cpu_data
146 #define current_cpu_data boot_cpu_data
147 #endif
148
149 extern const struct seq_operations cpuinfo_op;
150
151 static inline int hlt_works(int cpu)
152 {
153 #ifdef CONFIG_X86_32
154 return cpu_data(cpu).hlt_works_ok;
155 #else
156 return 1;
157 #endif
158 }
159
160 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
161
162 extern void cpu_detect(struct cpuinfo_x86 *c);
163
164 extern struct pt_regs *idle_regs(struct pt_regs *);
165
166 extern void early_cpu_init(void);
167 extern void identify_boot_cpu(void);
168 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
169 extern void print_cpu_info(struct cpuinfo_x86 *);
170 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
171 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
172 extern unsigned short num_cache_leaves;
173
174 extern void detect_extended_topology(struct cpuinfo_x86 *c);
175 extern void detect_ht(struct cpuinfo_x86 *c);
176
177 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
178 unsigned int *ecx, unsigned int *edx)
179 {
180 /* ecx is often an input as well as an output. */
181 asm("cpuid"
182 : "=a" (*eax),
183 "=b" (*ebx),
184 "=c" (*ecx),
185 "=d" (*edx)
186 : "0" (*eax), "2" (*ecx));
187 }
188
189 static inline void load_cr3(pgd_t *pgdir)
190 {
191 write_cr3(__pa(pgdir));
192 }
193
194 #ifdef CONFIG_X86_32
195 /* This is the TSS defined by the hardware. */
196 struct x86_hw_tss {
197 unsigned short back_link, __blh;
198 unsigned long sp0;
199 unsigned short ss0, __ss0h;
200 unsigned long sp1;
201 /* ss1 caches MSR_IA32_SYSENTER_CS: */
202 unsigned short ss1, __ss1h;
203 unsigned long sp2;
204 unsigned short ss2, __ss2h;
205 unsigned long __cr3;
206 unsigned long ip;
207 unsigned long flags;
208 unsigned long ax;
209 unsigned long cx;
210 unsigned long dx;
211 unsigned long bx;
212 unsigned long sp;
213 unsigned long bp;
214 unsigned long si;
215 unsigned long di;
216 unsigned short es, __esh;
217 unsigned short cs, __csh;
218 unsigned short ss, __ssh;
219 unsigned short ds, __dsh;
220 unsigned short fs, __fsh;
221 unsigned short gs, __gsh;
222 unsigned short ldt, __ldth;
223 unsigned short trace;
224 unsigned short io_bitmap_base;
225
226 } __attribute__((packed));
227 #else
228 struct x86_hw_tss {
229 u32 reserved1;
230 u64 sp0;
231 u64 sp1;
232 u64 sp2;
233 u64 reserved2;
234 u64 ist[7];
235 u32 reserved3;
236 u32 reserved4;
237 u16 reserved5;
238 u16 io_bitmap_base;
239
240 } __attribute__((packed)) ____cacheline_aligned;
241 #endif
242
243 /*
244 * IO-bitmap sizes:
245 */
246 #define IO_BITMAP_BITS 65536
247 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
248 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
249 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
250 #define INVALID_IO_BITMAP_OFFSET 0x8000
251
252 struct tss_struct {
253 /*
254 * The hardware state:
255 */
256 struct x86_hw_tss x86_tss;
257
258 /*
259 * The extra 1 is there because the CPU will access an
260 * additional byte beyond the end of the IO permission
261 * bitmap. The extra byte must be all 1 bits, and must
262 * be within the limit.
263 */
264 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
265
266 /*
267 * .. and then another 0x100 bytes for the emergency kernel stack:
268 */
269 unsigned long stack[64];
270
271 } ____cacheline_aligned;
272
273 DECLARE_PER_CPU(struct tss_struct, init_tss);
274
275 /*
276 * Save the original ist values for checking stack pointers during debugging
277 */
278 struct orig_ist {
279 unsigned long ist[7];
280 };
281
282 #define MXCSR_DEFAULT 0x1f80
283
284 struct i387_fsave_struct {
285 u32 cwd; /* FPU Control Word */
286 u32 swd; /* FPU Status Word */
287 u32 twd; /* FPU Tag Word */
288 u32 fip; /* FPU IP Offset */
289 u32 fcs; /* FPU IP Selector */
290 u32 foo; /* FPU Operand Pointer Offset */
291 u32 fos; /* FPU Operand Pointer Selector */
292
293 /* 8*10 bytes for each FP-reg = 80 bytes: */
294 u32 st_space[20];
295
296 /* Software status information [not touched by FSAVE ]: */
297 u32 status;
298 };
299
300 struct i387_fxsave_struct {
301 u16 cwd; /* Control Word */
302 u16 swd; /* Status Word */
303 u16 twd; /* Tag Word */
304 u16 fop; /* Last Instruction Opcode */
305 union {
306 struct {
307 u64 rip; /* Instruction Pointer */
308 u64 rdp; /* Data Pointer */
309 };
310 struct {
311 u32 fip; /* FPU IP Offset */
312 u32 fcs; /* FPU IP Selector */
313 u32 foo; /* FPU Operand Offset */
314 u32 fos; /* FPU Operand Selector */
315 };
316 };
317 u32 mxcsr; /* MXCSR Register State */
318 u32 mxcsr_mask; /* MXCSR Mask */
319
320 /* 8*16 bytes for each FP-reg = 128 bytes: */
321 u32 st_space[32];
322
323 /* 16*16 bytes for each XMM-reg = 256 bytes: */
324 u32 xmm_space[64];
325
326 u32 padding[12];
327
328 union {
329 u32 padding1[12];
330 u32 sw_reserved[12];
331 };
332
333 } __attribute__((aligned(16)));
334
335 struct i387_soft_struct {
336 u32 cwd;
337 u32 swd;
338 u32 twd;
339 u32 fip;
340 u32 fcs;
341 u32 foo;
342 u32 fos;
343 /* 8*10 bytes for each FP-reg = 80 bytes: */
344 u32 st_space[20];
345 u8 ftop;
346 u8 changed;
347 u8 lookahead;
348 u8 no_update;
349 u8 rm;
350 u8 alimit;
351 struct math_emu_info *info;
352 u32 entry_eip;
353 };
354
355 struct xsave_hdr_struct {
356 u64 xstate_bv;
357 u64 reserved1[2];
358 u64 reserved2[5];
359 } __attribute__((packed));
360
361 struct xsave_struct {
362 struct i387_fxsave_struct i387;
363 struct xsave_hdr_struct xsave_hdr;
364 /* new processor state extensions will go here */
365 } __attribute__ ((packed, aligned (64)));
366
367 union thread_xstate {
368 struct i387_fsave_struct fsave;
369 struct i387_fxsave_struct fxsave;
370 struct i387_soft_struct soft;
371 struct xsave_struct xsave;
372 };
373
374 #ifdef CONFIG_X86_64
375 DECLARE_PER_CPU(struct orig_ist, orig_ist);
376
377 union irq_stack_union {
378 char irq_stack[IRQ_STACK_SIZE];
379 /*
380 * GCC hardcodes the stack canary as %gs:40. Since the
381 * irq_stack is the object at %gs:0, we reserve the bottom
382 * 48 bytes of the irq stack for the canary.
383 */
384 struct {
385 char gs_base[40];
386 unsigned long stack_canary;
387 };
388 };
389
390 DECLARE_PER_CPU(union irq_stack_union, irq_stack_union);
391 DECLARE_INIT_PER_CPU(irq_stack_union);
392
393 DECLARE_PER_CPU(char *, irq_stack_ptr);
394 DECLARE_PER_CPU(unsigned int, irq_count);
395 extern unsigned long kernel_eflags;
396 extern asmlinkage void ignore_sysret(void);
397 #else /* X86_64 */
398 #ifdef CONFIG_CC_STACKPROTECTOR
399 DECLARE_PER_CPU(unsigned long, stack_canary);
400 #endif
401 #endif /* X86_64 */
402
403 extern unsigned int xstate_size;
404 extern void free_thread_xstate(struct task_struct *);
405 extern struct kmem_cache *task_xstate_cachep;
406 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
407 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
408 extern unsigned short num_cache_leaves;
409
410 struct thread_struct {
411 /* Cached TLS descriptors: */
412 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
413 unsigned long sp0;
414 unsigned long sp;
415 #ifdef CONFIG_X86_32
416 unsigned long sysenter_cs;
417 #else
418 unsigned long usersp; /* Copy from PDA */
419 unsigned short es;
420 unsigned short ds;
421 unsigned short fsindex;
422 unsigned short gsindex;
423 #endif
424 unsigned long ip;
425 unsigned long fs;
426 unsigned long gs;
427 /* Hardware debugging registers: */
428 unsigned long debugreg0;
429 unsigned long debugreg1;
430 unsigned long debugreg2;
431 unsigned long debugreg3;
432 unsigned long debugreg6;
433 unsigned long debugreg7;
434 /* Fault info: */
435 unsigned long cr2;
436 unsigned long trap_no;
437 unsigned long error_code;
438 /* floating point and extended processor state */
439 union thread_xstate *xstate;
440 #ifdef CONFIG_X86_32
441 /* Virtual 86 mode info */
442 struct vm86_struct __user *vm86_info;
443 unsigned long screen_bitmap;
444 unsigned long v86flags;
445 unsigned long v86mask;
446 unsigned long saved_sp0;
447 unsigned int saved_fs;
448 unsigned int saved_gs;
449 #endif
450 /* IO permissions: */
451 unsigned long *io_bitmap_ptr;
452 unsigned long iopl;
453 /* Max allowed port in the bitmap, in bytes: */
454 unsigned io_bitmap_max;
455 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
456 unsigned long debugctlmsr;
457 #ifdef CONFIG_X86_DS
458 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
459 struct ds_context *ds_ctx;
460 #endif /* CONFIG_X86_DS */
461 #ifdef CONFIG_X86_PTRACE_BTS
462 /* the signal to send on a bts buffer overflow */
463 unsigned int bts_ovfl_signal;
464 #endif /* CONFIG_X86_PTRACE_BTS */
465 };
466
467 static inline unsigned long native_get_debugreg(int regno)
468 {
469 unsigned long val = 0; /* Damn you, gcc! */
470
471 switch (regno) {
472 case 0:
473 asm("mov %%db0, %0" :"=r" (val));
474 break;
475 case 1:
476 asm("mov %%db1, %0" :"=r" (val));
477 break;
478 case 2:
479 asm("mov %%db2, %0" :"=r" (val));
480 break;
481 case 3:
482 asm("mov %%db3, %0" :"=r" (val));
483 break;
484 case 6:
485 asm("mov %%db6, %0" :"=r" (val));
486 break;
487 case 7:
488 asm("mov %%db7, %0" :"=r" (val));
489 break;
490 default:
491 BUG();
492 }
493 return val;
494 }
495
496 static inline void native_set_debugreg(int regno, unsigned long value)
497 {
498 switch (regno) {
499 case 0:
500 asm("mov %0, %%db0" ::"r" (value));
501 break;
502 case 1:
503 asm("mov %0, %%db1" ::"r" (value));
504 break;
505 case 2:
506 asm("mov %0, %%db2" ::"r" (value));
507 break;
508 case 3:
509 asm("mov %0, %%db3" ::"r" (value));
510 break;
511 case 6:
512 asm("mov %0, %%db6" ::"r" (value));
513 break;
514 case 7:
515 asm("mov %0, %%db7" ::"r" (value));
516 break;
517 default:
518 BUG();
519 }
520 }
521
522 /*
523 * Set IOPL bits in EFLAGS from given mask
524 */
525 static inline void native_set_iopl_mask(unsigned mask)
526 {
527 #ifdef CONFIG_X86_32
528 unsigned int reg;
529
530 asm volatile ("pushfl;"
531 "popl %0;"
532 "andl %1, %0;"
533 "orl %2, %0;"
534 "pushl %0;"
535 "popfl"
536 : "=&r" (reg)
537 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
538 #endif
539 }
540
541 static inline void
542 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
543 {
544 tss->x86_tss.sp0 = thread->sp0;
545 #ifdef CONFIG_X86_32
546 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
547 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
548 tss->x86_tss.ss1 = thread->sysenter_cs;
549 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
550 }
551 #endif
552 }
553
554 static inline void native_swapgs(void)
555 {
556 #ifdef CONFIG_X86_64
557 asm volatile("swapgs" ::: "memory");
558 #endif
559 }
560
561 #ifdef CONFIG_PARAVIRT
562 #include <asm/paravirt.h>
563 #else
564 #define __cpuid native_cpuid
565 #define paravirt_enabled() 0
566
567 /*
568 * These special macros can be used to get or set a debugging register
569 */
570 #define get_debugreg(var, register) \
571 (var) = native_get_debugreg(register)
572 #define set_debugreg(value, register) \
573 native_set_debugreg(register, value)
574
575 static inline void load_sp0(struct tss_struct *tss,
576 struct thread_struct *thread)
577 {
578 native_load_sp0(tss, thread);
579 }
580
581 #define set_iopl_mask native_set_iopl_mask
582 #endif /* CONFIG_PARAVIRT */
583
584 /*
585 * Save the cr4 feature set we're using (ie
586 * Pentium 4MB enable and PPro Global page
587 * enable), so that any CPU's that boot up
588 * after us can get the correct flags.
589 */
590 extern unsigned long mmu_cr4_features;
591
592 static inline void set_in_cr4(unsigned long mask)
593 {
594 unsigned cr4;
595
596 mmu_cr4_features |= mask;
597 cr4 = read_cr4();
598 cr4 |= mask;
599 write_cr4(cr4);
600 }
601
602 static inline void clear_in_cr4(unsigned long mask)
603 {
604 unsigned cr4;
605
606 mmu_cr4_features &= ~mask;
607 cr4 = read_cr4();
608 cr4 &= ~mask;
609 write_cr4(cr4);
610 }
611
612 typedef struct {
613 unsigned long seg;
614 } mm_segment_t;
615
616
617 /*
618 * create a kernel thread without removing it from tasklists
619 */
620 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
621
622 /* Free all resources held by a thread. */
623 extern void release_thread(struct task_struct *);
624
625 /* Prepare to copy thread state - unlazy all lazy state */
626 extern void prepare_to_copy(struct task_struct *tsk);
627
628 unsigned long get_wchan(struct task_struct *p);
629
630 /*
631 * Generic CPUID function
632 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
633 * resulting in stale register contents being returned.
634 */
635 static inline void cpuid(unsigned int op,
636 unsigned int *eax, unsigned int *ebx,
637 unsigned int *ecx, unsigned int *edx)
638 {
639 *eax = op;
640 *ecx = 0;
641 __cpuid(eax, ebx, ecx, edx);
642 }
643
644 /* Some CPUID calls want 'count' to be placed in ecx */
645 static inline void cpuid_count(unsigned int op, int count,
646 unsigned int *eax, unsigned int *ebx,
647 unsigned int *ecx, unsigned int *edx)
648 {
649 *eax = op;
650 *ecx = count;
651 __cpuid(eax, ebx, ecx, edx);
652 }
653
654 /*
655 * CPUID functions returning a single datum
656 */
657 static inline unsigned int cpuid_eax(unsigned int op)
658 {
659 unsigned int eax, ebx, ecx, edx;
660
661 cpuid(op, &eax, &ebx, &ecx, &edx);
662
663 return eax;
664 }
665
666 static inline unsigned int cpuid_ebx(unsigned int op)
667 {
668 unsigned int eax, ebx, ecx, edx;
669
670 cpuid(op, &eax, &ebx, &ecx, &edx);
671
672 return ebx;
673 }
674
675 static inline unsigned int cpuid_ecx(unsigned int op)
676 {
677 unsigned int eax, ebx, ecx, edx;
678
679 cpuid(op, &eax, &ebx, &ecx, &edx);
680
681 return ecx;
682 }
683
684 static inline unsigned int cpuid_edx(unsigned int op)
685 {
686 unsigned int eax, ebx, ecx, edx;
687
688 cpuid(op, &eax, &ebx, &ecx, &edx);
689
690 return edx;
691 }
692
693 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
694 static inline void rep_nop(void)
695 {
696 asm volatile("rep; nop" ::: "memory");
697 }
698
699 static inline void cpu_relax(void)
700 {
701 rep_nop();
702 }
703
704 /* Stop speculative execution: */
705 static inline void sync_core(void)
706 {
707 int tmp;
708
709 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
710 : "ebx", "ecx", "edx", "memory");
711 }
712
713 static inline void __monitor(const void *eax, unsigned long ecx,
714 unsigned long edx)
715 {
716 /* "monitor %eax, %ecx, %edx;" */
717 asm volatile(".byte 0x0f, 0x01, 0xc8;"
718 :: "a" (eax), "c" (ecx), "d"(edx));
719 }
720
721 static inline void __mwait(unsigned long eax, unsigned long ecx)
722 {
723 /* "mwait %eax, %ecx;" */
724 asm volatile(".byte 0x0f, 0x01, 0xc9;"
725 :: "a" (eax), "c" (ecx));
726 }
727
728 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
729 {
730 trace_hardirqs_on();
731 /* "mwait %eax, %ecx;" */
732 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
733 :: "a" (eax), "c" (ecx));
734 }
735
736 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
737
738 extern void select_idle_routine(const struct cpuinfo_x86 *c);
739 extern void init_c1e_mask(void);
740
741 extern unsigned long boot_option_idle_override;
742 extern unsigned long idle_halt;
743 extern unsigned long idle_nomwait;
744
745 /*
746 * on systems with caches, caches must be flashed as the absolute
747 * last instruction before going into a suspended halt. Otherwise,
748 * dirty data can linger in the cache and become stale on resume,
749 * leading to strange errors.
750 *
751 * perform a variety of operations to guarantee that the compiler
752 * will not reorder instructions. wbinvd itself is serializing
753 * so the processor will not reorder.
754 *
755 * Systems without cache can just go into halt.
756 */
757 static inline void wbinvd_halt(void)
758 {
759 mb();
760 /* check for clflush to determine if wbinvd is legal */
761 if (cpu_has_clflush)
762 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
763 else
764 while (1)
765 halt();
766 }
767
768 extern void enable_sep_cpu(void);
769 extern int sysenter_setup(void);
770
771 /* Defined in head.S */
772 extern struct desc_ptr early_gdt_descr;
773
774 extern void cpu_set_gdt(int);
775 extern void switch_to_new_gdt(int);
776 extern void load_percpu_segment(int);
777 extern void cpu_init(void);
778
779 static inline unsigned long get_debugctlmsr(void)
780 {
781 unsigned long debugctlmsr = 0;
782
783 #ifndef CONFIG_X86_DEBUGCTLMSR
784 if (boot_cpu_data.x86 < 6)
785 return 0;
786 #endif
787 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
788
789 return debugctlmsr;
790 }
791
792 static inline void update_debugctlmsr(unsigned long debugctlmsr)
793 {
794 #ifndef CONFIG_X86_DEBUGCTLMSR
795 if (boot_cpu_data.x86 < 6)
796 return;
797 #endif
798 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
799 }
800
801 /*
802 * from system description table in BIOS. Mostly for MCA use, but
803 * others may find it useful:
804 */
805 extern unsigned int machine_id;
806 extern unsigned int machine_submodel_id;
807 extern unsigned int BIOS_revision;
808
809 /* Boot loader type from the setup header: */
810 extern int bootloader_type;
811
812 extern char ignore_fpu_irq;
813
814 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
815 #define ARCH_HAS_PREFETCHW
816 #define ARCH_HAS_SPINLOCK_PREFETCH
817
818 #ifdef CONFIG_X86_32
819 # define BASE_PREFETCH ASM_NOP4
820 # define ARCH_HAS_PREFETCH
821 #else
822 # define BASE_PREFETCH "prefetcht0 (%1)"
823 #endif
824
825 /*
826 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
827 *
828 * It's not worth to care about 3dnow prefetches for the K6
829 * because they are microcoded there and very slow.
830 */
831 static inline void prefetch(const void *x)
832 {
833 alternative_input(BASE_PREFETCH,
834 "prefetchnta (%1)",
835 X86_FEATURE_XMM,
836 "r" (x));
837 }
838
839 /*
840 * 3dnow prefetch to get an exclusive cache line.
841 * Useful for spinlocks to avoid one state transition in the
842 * cache coherency protocol:
843 */
844 static inline void prefetchw(const void *x)
845 {
846 alternative_input(BASE_PREFETCH,
847 "prefetchw (%1)",
848 X86_FEATURE_3DNOW,
849 "r" (x));
850 }
851
852 static inline void spin_lock_prefetch(const void *x)
853 {
854 prefetchw(x);
855 }
856
857 #ifdef CONFIG_X86_32
858 /*
859 * User space process size: 3GB (default).
860 */
861 #define TASK_SIZE PAGE_OFFSET
862 #define TASK_SIZE_MAX TASK_SIZE
863 #define STACK_TOP TASK_SIZE
864 #define STACK_TOP_MAX STACK_TOP
865
866 #define INIT_THREAD { \
867 .sp0 = sizeof(init_stack) + (long)&init_stack, \
868 .vm86_info = NULL, \
869 .sysenter_cs = __KERNEL_CS, \
870 .io_bitmap_ptr = NULL, \
871 .fs = __KERNEL_PERCPU, \
872 }
873
874 /*
875 * Note that the .io_bitmap member must be extra-big. This is because
876 * the CPU will access an additional byte beyond the end of the IO
877 * permission bitmap. The extra byte must be all 1 bits, and must
878 * be within the limit.
879 */
880 #define INIT_TSS { \
881 .x86_tss = { \
882 .sp0 = sizeof(init_stack) + (long)&init_stack, \
883 .ss0 = __KERNEL_DS, \
884 .ss1 = __KERNEL_CS, \
885 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
886 }, \
887 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
888 }
889
890 extern unsigned long thread_saved_pc(struct task_struct *tsk);
891
892 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
893 #define KSTK_TOP(info) \
894 ({ \
895 unsigned long *__ptr = (unsigned long *)(info); \
896 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
897 })
898
899 /*
900 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
901 * This is necessary to guarantee that the entire "struct pt_regs"
902 * is accessable even if the CPU haven't stored the SS/ESP registers
903 * on the stack (interrupt gate does not save these registers
904 * when switching to the same priv ring).
905 * Therefore beware: accessing the ss/esp fields of the
906 * "struct pt_regs" is possible, but they may contain the
907 * completely wrong values.
908 */
909 #define task_pt_regs(task) \
910 ({ \
911 struct pt_regs *__regs__; \
912 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
913 __regs__ - 1; \
914 })
915
916 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
917
918 #else
919 /*
920 * User space process size. 47bits minus one guard page.
921 */
922 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
923
924 /* This decides where the kernel will search for a free chunk of vm
925 * space during mmap's.
926 */
927 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
928 0xc0000000 : 0xFFFFe000)
929
930 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
931 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
932 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
933 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
934
935 #define STACK_TOP TASK_SIZE
936 #define STACK_TOP_MAX TASK_SIZE_MAX
937
938 #define INIT_THREAD { \
939 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
940 }
941
942 #define INIT_TSS { \
943 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
944 }
945
946 /*
947 * Return saved PC of a blocked thread.
948 * What is this good for? it will be always the scheduler or ret_from_fork.
949 */
950 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
951
952 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
953 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
954 #endif /* CONFIG_X86_64 */
955
956 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
957 unsigned long new_sp);
958
959 /*
960 * This decides where the kernel will search for a free chunk of vm
961 * space during mmap's.
962 */
963 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
964
965 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
966
967 /* Get/set a process' ability to use the timestamp counter instruction */
968 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
969 #define SET_TSC_CTL(val) set_tsc_mode((val))
970
971 extern int get_tsc_mode(unsigned long adr);
972 extern int set_tsc_mode(unsigned int val);
973
974 #endif /* _ASM_X86_PROCESSOR_H */
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