drivers/net/phy/qsemi.c

   1 /*
   2  * drivers/net/phy/qsemi.c
   3  *
   4  * Driver for Quality Semiconductor PHYs
   5  *
   6  * Author: Andy Fleming
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/unistd.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/skbuff.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/version.h>
  33 #include <linux/mii.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/phy.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/uaccess.h>
  40
  41 /* ------------------------------------------------------------------------- */
  42 /* The Quality Semiconductor QS6612 is used on the RPX CLLF                  */
  43
  44 /* register definitions */
  45
  46 #define MII_QS6612_MCR          17  /* Mode Control Register      */
  47 #define MII_QS6612_FTR          27  /* Factory Test Register      */
  48 #define MII_QS6612_MCO          28  /* Misc. Control Register     */
  49 #define MII_QS6612_ISR          29  /* Interrupt Source Register  */
  50 #define MII_QS6612_IMR          30  /* Interrupt Mask Register    */
  51 #define MII_QS6612_IMR_INIT     0x003a
  52 #define MII_QS6612_PCR          31  /* 100BaseTx PHY Control Reg. */
  53
  54 #define QS6612_PCR_AN_COMPLETE  0x1000
  55 #define QS6612_PCR_RLBEN        0x0200
  56 #define QS6612_PCR_DCREN        0x0100
  57 #define QS6612_PCR_4B5BEN       0x0040
  58 #define QS6612_PCR_TX_ISOLATE   0x0020
  59 #define QS6612_PCR_MLT3_DIS     0x0002
  60 #define QS6612_PCR_SCRM_DESCRM  0x0001
  61
  62 MODULE_DESCRIPTION("Quality Semiconductor PHY driver");
  63 MODULE_AUTHOR("Andy Fleming");
  64 MODULE_LICENSE("GPL");
  65
  66 /* Returns 0, unless there's a write error */
  67 static int qs6612_config_init(struct phy_device *phydev)
  68 {
  69         /* The PHY powers up isolated on the RPX,
  70          * so send a command to allow operation.
  71          * XXX - My docs indicate this should be 0x0940
  72          * ...or something.  The current value sets three
  73          * reserved bits, bit 11, which specifies it should be
  74          * set to one, bit 10, which specifies it should be set
  75          * to 0, and bit 7, which doesn't specify.  However, my
  76          * docs are preliminary, and I will leave it like this
  77          * until someone more knowledgable corrects me or it.
  78          * -- Andy Fleming
  79          */
  80         return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);
  81 }
  82
  83 static int qs6612_ack_interrupt(struct phy_device *phydev)
  84 {
  85         int err;
  86
  87         err = phy_read(phydev, MII_QS6612_ISR);
  88
  89         if (err < 0)
  90                 return err;
  91
  92         err = phy_read(phydev, MII_BMSR);
  93
  94         if (err < 0)
  95                 return err;
  96
  97         err = phy_read(phydev, MII_EXPANSION);
  98
  99         if (err < 0)
 100                 return err;
 101
 102         return 0;
 103 }
 104
 105 static int qs6612_config_intr(struct phy_device *phydev)
 106 {
 107         int err;
 108         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 109                 err = phy_write(phydev, MII_QS6612_IMR,
 110                                 MII_QS6612_IMR_INIT);
 111         else
 112                 err = phy_write(phydev, MII_QS6612_IMR, 0);
 113
 114         return err;
 115
 116 }
 117
 118 static struct phy_driver qs6612_driver = {
 119         .phy_id         = 0x00181440,
 120         .name           = "QS6612",
 121         .phy_id_mask    = 0xfffffff0,
 122         .features       = PHY_BASIC_FEATURES,
 123         .flags          = PHY_HAS_INTERRUPT,
 124         .config_init    = qs6612_config_init,
 125         .config_aneg    = genphy_config_aneg,
 126         .read_status    = genphy_read_status,
 127         .ack_interrupt  = qs6612_ack_interrupt,
 128         .config_intr    = qs6612_config_intr,
 129         .driver         = { .owner = THIS_MODULE,},
 130 };
 131
 132 static int __init qs6612_init(void)
 133 {
 134         return phy_driver_register(&qs6612_driver);
 135 }
 136
 137 static void __exit qs6612_exit(void)
 138 {
 139         phy_driver_unregister(&qs6612_driver);
 140 }
 141
 142 module_init(qs6612_init);
 143 module_exit(qs6612_exit);