2 * pata_efar.c - EFAR PIIX clone controller driver
4 * (C) 2005 Red Hat <alan@redhat.com>
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
9 * Intel ICH controllers the EFAR widened the UDMA mode register bits
10 * and doesn't require the funky clock selection.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/blkdev.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <scsi/scsi_host.h>
21 #include <linux/libata.h>
22 #include <linux/ata.h>
24 #define DRV_NAME "pata_efar"
25 #define DRV_VERSION "0.4.4"
28 * efar_pre_reset - Enable bits
30 * @deadline: deadline jiffies for the operation
32 * Perform cable detection for the EFAR ATA interface. This is
33 * different to the PIIX arrangement
36 static int efar_pre_reset(struct ata_link
*link
, unsigned long deadline
)
38 static const struct pci_bits efar_enable_bits
[] = {
39 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
40 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
42 struct ata_port
*ap
= link
->ap
;
43 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
45 if (!pci_test_config_bits(pdev
, &efar_enable_bits
[ap
->port_no
]))
48 return ata_std_prereset(link
, deadline
);
52 * efar_probe_reset - Probe specified port on PATA host controller
56 * None (inherited from caller).
59 static void efar_error_handler(struct ata_port
*ap
)
61 ata_bmdma_drive_eh(ap
, efar_pre_reset
, ata_std_softreset
, NULL
, ata_std_postreset
);
65 * efar_cable_detect - check for 40/80 pin
68 * Perform cable detection for the EFAR ATA interface. This is
69 * different to the PIIX arrangement
72 static int efar_cable_detect(struct ata_port
*ap
)
74 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
77 pci_read_config_byte(pdev
, 0x47, &tmp
);
78 if (tmp
& (2 >> ap
->port_no
))
79 return ATA_CBL_PATA40
;
80 return ATA_CBL_PATA80
;
84 * efar_set_piomode - Initialize host controller PATA PIO timings
85 * @ap: Port whose timings we are configuring
88 * Set PIO mode for device, in host controller PCI config space.
91 * None (inherited from caller).
94 static void efar_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
96 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
97 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
98 unsigned int idetm_port
= ap
->port_no
? 0x42 : 0x40;
103 * See Intel Document 298600-004 for the timing programing rules
104 * for PIIX/ICH. The EFAR is a clone so very similar
107 static const /* ISP RTC */
108 u8 timings
[][2] = { { 0, 0 },
115 control
|= 1; /* TIME1 enable */
116 if (ata_pio_need_iordy(adev
)) /* PIO 3/4 require IORDY */
117 control
|= 2; /* IE enable */
118 /* Intel specifies that the PPE functionality is for disk only */
119 if (adev
->class == ATA_DEV_ATA
)
120 control
|= 4; /* PPE enable */
122 pci_read_config_word(dev
, idetm_port
, &idetm_data
);
124 /* Enable PPE, IE and TIME as appropriate */
126 if (adev
->devno
== 0) {
127 idetm_data
&= 0xCCF0;
128 idetm_data
|= control
;
129 idetm_data
|= (timings
[pio
][0] << 12) |
130 (timings
[pio
][1] << 8);
132 int shift
= 4 * ap
->port_no
;
135 idetm_data
&= 0xCC0F;
136 idetm_data
|= (control
<< 4);
138 /* Slave timing in separate register */
139 pci_read_config_byte(dev
, 0x44, &slave_data
);
140 slave_data
&= 0x0F << shift
;
141 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << shift
;
142 pci_write_config_byte(dev
, 0x44, slave_data
);
145 idetm_data
|= 0x4000; /* Ensure SITRE is enabled */
146 pci_write_config_word(dev
, idetm_port
, idetm_data
);
150 * efar_set_dmamode - Initialize host controller PATA DMA timings
151 * @ap: Port whose timings we are configuring
152 * @adev: Device to program
154 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
157 * None (inherited from caller).
160 static void efar_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
162 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
163 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
165 u8 speed
= adev
->dma_mode
;
166 int devid
= adev
->devno
+ 2 * ap
->port_no
;
169 static const /* ISP RTC */
170 u8 timings
[][2] = { { 0, 0 },
176 pci_read_config_word(dev
, master_port
, &master_data
);
177 pci_read_config_byte(dev
, 0x48, &udma_enable
);
179 if (speed
>= XFER_UDMA_0
) {
180 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
183 udma_enable
|= (1 << devid
);
185 /* Load the UDMA mode number */
186 pci_read_config_word(dev
, 0x4A, &udma_timing
);
187 udma_timing
&= ~(7 << (4 * devid
));
188 udma_timing
|= udma
<< (4 * devid
);
189 pci_write_config_word(dev
, 0x4A, udma_timing
);
192 * MWDMA is driven by the PIO timings. We must also enable
193 * IORDY unconditionally along with TIME1. PPE has already
194 * been set when the PIO timing was set.
196 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
197 unsigned int control
;
199 const unsigned int needed_pio
[3] = {
200 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
202 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
204 control
= 3; /* IORDY|TIME1 */
206 /* If the drive MWDMA is faster than it can do PIO then
207 we must force PIO into PIO0 */
209 if (adev
->pio_mode
< needed_pio
[mwdma
])
210 /* Enable DMA timing only */
211 control
|= 8; /* PIO cycles in PIO0 */
213 if (adev
->devno
) { /* Slave */
214 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
215 master_data
|= control
<< 4;
216 pci_read_config_byte(dev
, 0x44, &slave_data
);
217 slave_data
&= (0x0F + 0xE1 * ap
->port_no
);
218 /* Load the matching timing */
219 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
220 pci_write_config_byte(dev
, 0x44, slave_data
);
221 } else { /* Master */
222 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
223 and master timing bits */
224 master_data
|= control
;
226 (timings
[pio
][0] << 12) |
227 (timings
[pio
][1] << 8);
229 udma_enable
&= ~(1 << devid
);
230 pci_write_config_word(dev
, master_port
, master_data
);
232 pci_write_config_byte(dev
, 0x48, udma_enable
);
235 static struct scsi_host_template efar_sht
= {
236 ATA_BMDMA_SHT(DRV_NAME
),
239 static const struct ata_port_operations efar_ops
= {
240 .set_piomode
= efar_set_piomode
,
241 .set_dmamode
= efar_set_dmamode
,
242 .mode_filter
= ata_pci_default_filter
,
244 .tf_load
= ata_tf_load
,
245 .tf_read
= ata_tf_read
,
246 .check_status
= ata_check_status
,
247 .exec_command
= ata_exec_command
,
248 .dev_select
= ata_std_dev_select
,
250 .freeze
= ata_bmdma_freeze
,
251 .thaw
= ata_bmdma_thaw
,
252 .error_handler
= efar_error_handler
,
253 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
254 .cable_detect
= efar_cable_detect
,
256 .bmdma_setup
= ata_bmdma_setup
,
257 .bmdma_start
= ata_bmdma_start
,
258 .bmdma_stop
= ata_bmdma_stop
,
259 .bmdma_status
= ata_bmdma_status
,
260 .qc_prep
= ata_qc_prep
,
261 .qc_issue
= ata_qc_issue_prot
,
262 .data_xfer
= ata_data_xfer
,
264 .irq_handler
= ata_interrupt
,
265 .irq_clear
= ata_bmdma_irq_clear
,
266 .irq_on
= ata_irq_on
,
268 .port_start
= ata_sff_port_start
,
273 * efar_init_one - Register EFAR ATA PCI device with kernel services
274 * @pdev: PCI device to register
275 * @ent: Entry in efar_pci_tbl matching with @pdev
277 * Called from kernel PCI layer.
280 * Inherited from PCI layer (may sleep).
283 * Zero on success, or -ERRNO value.
286 static int efar_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
288 static int printed_version
;
289 static const struct ata_port_info info
= {
291 .flags
= ATA_FLAG_SLAVE_POSS
,
292 .pio_mask
= 0x1f, /* pio0-4 */
293 .mwdma_mask
= 0x07, /* mwdma1-2 */
294 .udma_mask
= 0x0f, /* UDMA 66 */
295 .port_ops
= &efar_ops
,
297 const struct ata_port_info
*ppi
[] = { &info
, NULL
};
299 if (!printed_version
++)
300 dev_printk(KERN_DEBUG
, &pdev
->dev
,
301 "version " DRV_VERSION
"\n");
303 return ata_pci_init_one(pdev
, ppi
);
306 static const struct pci_device_id efar_pci_tbl
[] = {
307 { PCI_VDEVICE(EFAR
, 0x9130), },
309 { } /* terminate list */
312 static struct pci_driver efar_pci_driver
= {
314 .id_table
= efar_pci_tbl
,
315 .probe
= efar_init_one
,
316 .remove
= ata_pci_remove_one
,
318 .suspend
= ata_pci_device_suspend
,
319 .resume
= ata_pci_device_resume
,
323 static int __init
efar_init(void)
325 return pci_register_driver(&efar_pci_driver
);
328 static void __exit
efar_exit(void)
330 pci_unregister_driver(&efar_pci_driver
);
333 module_init(efar_init
);
334 module_exit(efar_exit
);
336 MODULE_AUTHOR("Alan Cox");
337 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
338 MODULE_LICENSE("GPL");
339 MODULE_DEVICE_TABLE(pci
, efar_pci_tbl
);
340 MODULE_VERSION(DRV_VERSION
);