2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
96 #include "gianfar_mii.h"
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
102 const char gfar_driver_name
[] = "Gianfar Ethernet";
103 const char gfar_driver_version
[] = "1.3";
105 static int gfar_enet_open(struct net_device
*dev
);
106 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
107 static void gfar_reset_task(struct work_struct
*work
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct of_device
*ofdev
,
122 const struct of_device_id
*match
);
123 static int gfar_remove(struct of_device
*ofdev
);
124 static void free_skb_resources(struct gfar_private
*priv
);
125 static void gfar_set_multi(struct net_device
*dev
);
126 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
127 static void gfar_configure_serdes(struct net_device
*dev
);
128 static int gfar_poll(struct napi_struct
*napi
, int budget
);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device
*dev
);
132 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
133 static int gfar_clean_tx_ring(struct net_device
*dev
);
134 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
136 static void gfar_vlan_rx_register(struct net_device
*netdev
,
137 struct vlan_group
*grp
);
138 void gfar_halt(struct net_device
*dev
);
139 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 extern const struct ethtool_ops gfar_ethtool_ops
;
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
153 return priv
->vlgrp
|| priv
->rx_csum_enable
;
156 static int gfar_of_init(struct net_device
*dev
)
158 struct device_node
*phy
, *mdio
;
159 const unsigned int *id
;
162 const void *mac_addr
;
166 struct gfar_private
*priv
= netdev_priv(dev
);
167 struct device_node
*np
= priv
->node
;
168 char bus_name
[MII_BUS_ID_SIZE
];
170 if (!np
|| !of_device_is_available(np
))
173 /* get a pointer to the register memory */
174 addr
= of_translate_address(np
, of_get_address(np
, 0, &size
, NULL
));
175 priv
->regs
= ioremap(addr
, size
);
177 if (priv
->regs
== NULL
)
180 priv
->interruptTransmit
= irq_of_parse_and_map(np
, 0);
182 model
= of_get_property(np
, "model", NULL
);
184 /* If we aren't the FEC we have multiple interrupts */
185 if (model
&& strcasecmp(model
, "FEC")) {
186 priv
->interruptReceive
= irq_of_parse_and_map(np
, 1);
188 priv
->interruptError
= irq_of_parse_and_map(np
, 2);
190 if (priv
->interruptTransmit
< 0 ||
191 priv
->interruptReceive
< 0 ||
192 priv
->interruptError
< 0) {
198 mac_addr
= of_get_mac_address(np
);
200 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
202 if (model
&& !strcasecmp(model
, "TSEC"))
204 FSL_GIANFAR_DEV_HAS_GIGABIT
|
205 FSL_GIANFAR_DEV_HAS_COALESCE
|
206 FSL_GIANFAR_DEV_HAS_RMON
|
207 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
208 if (model
&& !strcasecmp(model
, "eTSEC"))
210 FSL_GIANFAR_DEV_HAS_GIGABIT
|
211 FSL_GIANFAR_DEV_HAS_COALESCE
|
212 FSL_GIANFAR_DEV_HAS_RMON
|
213 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
214 FSL_GIANFAR_DEV_HAS_PADDING
|
215 FSL_GIANFAR_DEV_HAS_CSUM
|
216 FSL_GIANFAR_DEV_HAS_VLAN
|
217 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
218 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
220 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
222 /* We only care about rgmii-id. The rest are autodetected */
223 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
224 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
226 priv
->interface
= PHY_INTERFACE_MODE_MII
;
228 if (of_get_property(np
, "fsl,magic-packet", NULL
))
229 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
231 ph
= of_get_property(np
, "phy-handle", NULL
);
235 fixed_link
= (u32
*)of_get_property(np
, "fixed-link", NULL
);
241 snprintf(priv
->phy_bus_id
, BUS_ID_SIZE
, PHY_ID_FMT
, "0",
244 phy
= of_find_node_by_phandle(*ph
);
251 mdio
= of_get_parent(phy
);
253 id
= of_get_property(phy
, "reg", NULL
);
258 gfar_mdio_bus_name(bus_name
, mdio
);
259 snprintf(priv
->phy_bus_id
, BUS_ID_SIZE
, "%s:%02x",
263 /* Find the TBI PHY. If it's not there, we don't support SGMII */
264 ph
= of_get_property(np
, "tbi-handle", NULL
);
266 struct device_node
*tbi
= of_find_node_by_phandle(*ph
);
267 struct of_device
*ofdev
;
273 mdio
= of_get_parent(tbi
);
277 ofdev
= of_find_device_by_node(mdio
);
281 id
= of_get_property(tbi
, "reg", NULL
);
287 bus
= dev_get_drvdata(&ofdev
->dev
);
289 priv
->tbiphy
= bus
->phy_map
[*id
];
299 /* Set up the ethernet device structure, private data,
300 * and anything else we need before we start */
301 static int gfar_probe(struct of_device
*ofdev
,
302 const struct of_device_id
*match
)
305 struct net_device
*dev
= NULL
;
306 struct gfar_private
*priv
= NULL
;
307 DECLARE_MAC_BUF(mac
);
311 /* Create an ethernet device instance */
312 dev
= alloc_etherdev(sizeof (*priv
));
317 priv
= netdev_priv(dev
);
319 priv
->node
= ofdev
->node
;
321 err
= gfar_of_init(dev
);
326 spin_lock_init(&priv
->txlock
);
327 spin_lock_init(&priv
->rxlock
);
328 spin_lock_init(&priv
->bflock
);
329 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
331 dev_set_drvdata(&ofdev
->dev
, priv
);
333 /* Stop the DMA engine now, in case it was running before */
334 /* (The firmware could have used it, and left it running). */
337 /* Reset MAC layer */
338 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
340 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
341 gfar_write(&priv
->regs
->maccfg1
, tempval
);
343 /* Initialize MACCFG2. */
344 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
346 /* Initialize ECNTRL */
347 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
349 /* Set the dev->base_addr to the gfar reg region */
350 dev
->base_addr
= (unsigned long) (priv
->regs
);
352 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
354 /* Fill in the dev structure */
355 dev
->open
= gfar_enet_open
;
356 dev
->hard_start_xmit
= gfar_start_xmit
;
357 dev
->tx_timeout
= gfar_timeout
;
358 dev
->watchdog_timeo
= TX_TIMEOUT
;
359 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
360 #ifdef CONFIG_NET_POLL_CONTROLLER
361 dev
->poll_controller
= gfar_netpoll
;
363 dev
->stop
= gfar_close
;
364 dev
->change_mtu
= gfar_change_mtu
;
366 dev
->set_multicast_list
= gfar_set_multi
;
368 dev
->ethtool_ops
= &gfar_ethtool_ops
;
370 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
371 priv
->rx_csum_enable
= 1;
372 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
374 priv
->rx_csum_enable
= 0;
378 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
379 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
381 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
384 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
385 priv
->extended_hash
= 1;
386 priv
->hash_width
= 9;
388 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
389 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
390 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
391 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
392 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
393 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
394 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
395 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
396 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
397 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
398 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
399 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
400 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
401 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
402 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
403 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
406 priv
->extended_hash
= 0;
407 priv
->hash_width
= 8;
409 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
410 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
411 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
412 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
413 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
414 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
415 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
416 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
419 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
420 priv
->padding
= DEFAULT_PADDING
;
424 if (dev
->features
& NETIF_F_IP_CSUM
)
425 dev
->hard_header_len
+= GMAC_FCB_LEN
;
427 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
428 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
429 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
430 priv
->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
432 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
433 priv
->txic
= DEFAULT_TXIC
;
434 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
435 priv
->rxic
= DEFAULT_RXIC
;
437 /* Enable most messages by default */
438 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
440 /* Carrier starts down, phylib will bring it up */
441 netif_carrier_off(dev
);
443 err
= register_netdev(dev
);
446 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
451 /* fill out IRQ number and name fields */
452 len_devname
= strlen(dev
->name
);
453 strncpy(&priv
->int_name_tx
[0], dev
->name
, len_devname
);
454 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
455 strncpy(&priv
->int_name_tx
[len_devname
],
456 "_tx", sizeof("_tx") + 1);
458 strncpy(&priv
->int_name_rx
[0], dev
->name
, len_devname
);
459 strncpy(&priv
->int_name_rx
[len_devname
],
460 "_rx", sizeof("_rx") + 1);
462 strncpy(&priv
->int_name_er
[0], dev
->name
, len_devname
);
463 strncpy(&priv
->int_name_er
[len_devname
],
464 "_er", sizeof("_er") + 1);
466 priv
->int_name_tx
[len_devname
] = '\0';
468 /* Create all the sysfs files */
469 gfar_init_sysfs(dev
);
471 /* Print out the device info */
472 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
474 /* Even more device info helps when determining which kernel */
475 /* provided which set of benchmarks. */
476 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
477 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
478 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
489 static int gfar_remove(struct of_device
*ofdev
)
491 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
493 dev_set_drvdata(&ofdev
->dev
, NULL
);
496 free_netdev(priv
->dev
);
502 static int gfar_suspend(struct of_device
*ofdev
, pm_message_t state
)
504 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
505 struct net_device
*dev
= priv
->dev
;
509 int magic_packet
= priv
->wol_en
&&
510 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
512 netif_device_detach(dev
);
514 if (netif_running(dev
)) {
515 spin_lock_irqsave(&priv
->txlock
, flags
);
516 spin_lock(&priv
->rxlock
);
518 gfar_halt_nodisable(dev
);
520 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
521 tempval
= gfar_read(&priv
->regs
->maccfg1
);
523 tempval
&= ~MACCFG1_TX_EN
;
526 tempval
&= ~MACCFG1_RX_EN
;
528 gfar_write(&priv
->regs
->maccfg1
, tempval
);
530 spin_unlock(&priv
->rxlock
);
531 spin_unlock_irqrestore(&priv
->txlock
, flags
);
533 napi_disable(&priv
->napi
);
536 /* Enable interrupt on Magic Packet */
537 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
539 /* Enable Magic Packet mode */
540 tempval
= gfar_read(&priv
->regs
->maccfg2
);
541 tempval
|= MACCFG2_MPEN
;
542 gfar_write(&priv
->regs
->maccfg2
, tempval
);
544 phy_stop(priv
->phydev
);
551 static int gfar_resume(struct of_device
*ofdev
)
553 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
554 struct net_device
*dev
= priv
->dev
;
557 int magic_packet
= priv
->wol_en
&&
558 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
560 if (!netif_running(dev
)) {
561 netif_device_attach(dev
);
565 if (!magic_packet
&& priv
->phydev
)
566 phy_start(priv
->phydev
);
568 /* Disable Magic Packet mode, in case something
572 spin_lock_irqsave(&priv
->txlock
, flags
);
573 spin_lock(&priv
->rxlock
);
575 tempval
= gfar_read(&priv
->regs
->maccfg2
);
576 tempval
&= ~MACCFG2_MPEN
;
577 gfar_write(&priv
->regs
->maccfg2
, tempval
);
581 spin_unlock(&priv
->rxlock
);
582 spin_unlock_irqrestore(&priv
->txlock
, flags
);
584 netif_device_attach(dev
);
586 napi_enable(&priv
->napi
);
591 #define gfar_suspend NULL
592 #define gfar_resume NULL
595 /* Reads the controller's registers to determine what interface
596 * connects it to the PHY.
598 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
600 struct gfar_private
*priv
= netdev_priv(dev
);
601 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
603 if (ecntrl
& ECNTRL_SGMII_MODE
)
604 return PHY_INTERFACE_MODE_SGMII
;
606 if (ecntrl
& ECNTRL_TBI_MODE
) {
607 if (ecntrl
& ECNTRL_REDUCED_MODE
)
608 return PHY_INTERFACE_MODE_RTBI
;
610 return PHY_INTERFACE_MODE_TBI
;
613 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
614 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
615 return PHY_INTERFACE_MODE_RMII
;
617 phy_interface_t interface
= priv
->interface
;
620 * This isn't autodetected right now, so it must
621 * be set by the device tree or platform code.
623 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
624 return PHY_INTERFACE_MODE_RGMII_ID
;
626 return PHY_INTERFACE_MODE_RGMII
;
630 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
631 return PHY_INTERFACE_MODE_GMII
;
633 return PHY_INTERFACE_MODE_MII
;
637 /* Initializes driver's PHY state, and attaches to the PHY.
638 * Returns 0 on success.
640 static int init_phy(struct net_device
*dev
)
642 struct gfar_private
*priv
= netdev_priv(dev
);
643 uint gigabit_support
=
644 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
645 SUPPORTED_1000baseT_Full
: 0;
646 struct phy_device
*phydev
;
647 phy_interface_t interface
;
651 priv
->oldduplex
= -1;
653 interface
= gfar_get_interface(dev
);
655 phydev
= phy_connect(dev
, priv
->phy_bus_id
, &adjust_link
, 0, interface
);
657 if (interface
== PHY_INTERFACE_MODE_SGMII
)
658 gfar_configure_serdes(dev
);
660 if (IS_ERR(phydev
)) {
661 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
662 return PTR_ERR(phydev
);
665 /* Remove any features not supported by the controller */
666 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
667 phydev
->advertising
= phydev
->supported
;
669 priv
->phydev
= phydev
;
675 * Initialize TBI PHY interface for communicating with the
676 * SERDES lynx PHY on the chip. We communicate with this PHY
677 * through the MDIO bus on each controller, treating it as a
678 * "normal" PHY at the address found in the TBIPA register. We assume
679 * that the TBIPA register is valid. Either the MDIO bus code will set
680 * it to a value that doesn't conflict with other PHYs on the bus, or the
681 * value doesn't matter, as there are no other PHYs on the bus.
683 static void gfar_configure_serdes(struct net_device
*dev
)
685 struct gfar_private
*priv
= netdev_priv(dev
);
688 printk(KERN_WARNING
"SGMII mode requires that the device "
689 "tree specify a tbi-handle\n");
694 * If the link is already up, we must already be ok, and don't need to
695 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
696 * everything for us? Resetting it takes the link down and requires
697 * several seconds for it to come back.
699 if (phy_read(priv
->tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
702 /* Single clk mode, mii mode off(for serdes communication) */
703 phy_write(priv
->tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
705 phy_write(priv
->tbiphy
, MII_ADVERTISE
,
706 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
707 ADVERTISE_1000XPSE_ASYM
);
709 phy_write(priv
->tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
710 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
713 static void init_registers(struct net_device
*dev
)
715 struct gfar_private
*priv
= netdev_priv(dev
);
718 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
720 /* Initialize IMASK */
721 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
723 /* Init hash registers to zero */
724 gfar_write(&priv
->regs
->igaddr0
, 0);
725 gfar_write(&priv
->regs
->igaddr1
, 0);
726 gfar_write(&priv
->regs
->igaddr2
, 0);
727 gfar_write(&priv
->regs
->igaddr3
, 0);
728 gfar_write(&priv
->regs
->igaddr4
, 0);
729 gfar_write(&priv
->regs
->igaddr5
, 0);
730 gfar_write(&priv
->regs
->igaddr6
, 0);
731 gfar_write(&priv
->regs
->igaddr7
, 0);
733 gfar_write(&priv
->regs
->gaddr0
, 0);
734 gfar_write(&priv
->regs
->gaddr1
, 0);
735 gfar_write(&priv
->regs
->gaddr2
, 0);
736 gfar_write(&priv
->regs
->gaddr3
, 0);
737 gfar_write(&priv
->regs
->gaddr4
, 0);
738 gfar_write(&priv
->regs
->gaddr5
, 0);
739 gfar_write(&priv
->regs
->gaddr6
, 0);
740 gfar_write(&priv
->regs
->gaddr7
, 0);
742 /* Zero out the rmon mib registers if it has them */
743 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
744 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
746 /* Mask off the CAM interrupts */
747 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
748 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
751 /* Initialize the max receive buffer length */
752 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
754 /* Initialize the Minimum Frame Length Register */
755 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
759 /* Halt the receive and transmit queues */
760 static void gfar_halt_nodisable(struct net_device
*dev
)
762 struct gfar_private
*priv
= netdev_priv(dev
);
763 struct gfar __iomem
*regs
= priv
->regs
;
766 /* Mask all interrupts */
767 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
769 /* Clear all interrupts */
770 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
772 /* Stop the DMA, and wait for it to stop */
773 tempval
= gfar_read(&priv
->regs
->dmactrl
);
774 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
775 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
776 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
777 gfar_write(&priv
->regs
->dmactrl
, tempval
);
779 while (!(gfar_read(&priv
->regs
->ievent
) &
780 (IEVENT_GRSC
| IEVENT_GTSC
)))
785 /* Halt the receive and transmit queues */
786 void gfar_halt(struct net_device
*dev
)
788 struct gfar_private
*priv
= netdev_priv(dev
);
789 struct gfar __iomem
*regs
= priv
->regs
;
792 gfar_halt_nodisable(dev
);
794 /* Disable Rx and Tx */
795 tempval
= gfar_read(®s
->maccfg1
);
796 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
797 gfar_write(®s
->maccfg1
, tempval
);
800 void stop_gfar(struct net_device
*dev
)
802 struct gfar_private
*priv
= netdev_priv(dev
);
803 struct gfar __iomem
*regs
= priv
->regs
;
806 phy_stop(priv
->phydev
);
809 spin_lock_irqsave(&priv
->txlock
, flags
);
810 spin_lock(&priv
->rxlock
);
814 spin_unlock(&priv
->rxlock
);
815 spin_unlock_irqrestore(&priv
->txlock
, flags
);
818 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
819 free_irq(priv
->interruptError
, dev
);
820 free_irq(priv
->interruptTransmit
, dev
);
821 free_irq(priv
->interruptReceive
, dev
);
823 free_irq(priv
->interruptTransmit
, dev
);
826 free_skb_resources(priv
);
828 dma_free_coherent(&dev
->dev
,
829 sizeof(struct txbd8
)*priv
->tx_ring_size
830 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
832 gfar_read(®s
->tbase0
));
835 /* If there are any tx skbs or rx skbs still around, free them.
836 * Then free tx_skbuff and rx_skbuff */
837 static void free_skb_resources(struct gfar_private
*priv
)
843 /* Go through all the buffer descriptors and free their data buffers */
844 txbdp
= priv
->tx_bd_base
;
846 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
847 if (!priv
->tx_skbuff
[i
])
850 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
851 txbdp
->length
, DMA_TO_DEVICE
);
853 for (j
= 0; j
< skb_shinfo(priv
->tx_skbuff
[i
])->nr_frags
; j
++) {
855 dma_unmap_page(&priv
->dev
->dev
, txbdp
->bufPtr
,
856 txbdp
->length
, DMA_TO_DEVICE
);
859 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
860 priv
->tx_skbuff
[i
] = NULL
;
863 kfree(priv
->tx_skbuff
);
865 rxbdp
= priv
->rx_bd_base
;
867 /* rx_skbuff is not guaranteed to be allocated, so only
868 * free it and its contents if it is allocated */
869 if(priv
->rx_skbuff
!= NULL
) {
870 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
871 if (priv
->rx_skbuff
[i
]) {
872 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
873 priv
->rx_buffer_size
,
876 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
877 priv
->rx_skbuff
[i
] = NULL
;
886 kfree(priv
->rx_skbuff
);
890 void gfar_start(struct net_device
*dev
)
892 struct gfar_private
*priv
= netdev_priv(dev
);
893 struct gfar __iomem
*regs
= priv
->regs
;
896 /* Enable Rx and Tx in MACCFG1 */
897 tempval
= gfar_read(®s
->maccfg1
);
898 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
899 gfar_write(®s
->maccfg1
, tempval
);
901 /* Initialize DMACTRL to have WWR and WOP */
902 tempval
= gfar_read(&priv
->regs
->dmactrl
);
903 tempval
|= DMACTRL_INIT_SETTINGS
;
904 gfar_write(&priv
->regs
->dmactrl
, tempval
);
906 /* Make sure we aren't stopped */
907 tempval
= gfar_read(&priv
->regs
->dmactrl
);
908 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
909 gfar_write(&priv
->regs
->dmactrl
, tempval
);
911 /* Clear THLT/RHLT, so that the DMA starts polling now */
912 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
913 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
915 /* Unmask the interrupts we look for */
916 gfar_write(®s
->imask
, IMASK_DEFAULT
);
918 dev
->trans_start
= jiffies
;
921 /* Bring the controller up and running */
922 int startup_gfar(struct net_device
*dev
)
929 struct gfar_private
*priv
= netdev_priv(dev
);
930 struct gfar __iomem
*regs
= priv
->regs
;
935 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
937 /* Allocate memory for the buffer descriptors */
938 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
939 sizeof (struct txbd8
) * priv
->tx_ring_size
+
940 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
944 if (netif_msg_ifup(priv
))
945 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
950 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
952 /* enet DMA only understands physical addresses */
953 gfar_write(®s
->tbase0
, addr
);
955 /* Start the rx descriptor ring where the tx ring leaves off */
956 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
957 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
958 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
959 gfar_write(®s
->rbase0
, addr
);
961 /* Setup the skbuff rings */
963 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
964 priv
->tx_ring_size
, GFP_KERNEL
);
966 if (NULL
== priv
->tx_skbuff
) {
967 if (netif_msg_ifup(priv
))
968 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
974 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
975 priv
->tx_skbuff
[i
] = NULL
;
978 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
979 priv
->rx_ring_size
, GFP_KERNEL
);
981 if (NULL
== priv
->rx_skbuff
) {
982 if (netif_msg_ifup(priv
))
983 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
989 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
990 priv
->rx_skbuff
[i
] = NULL
;
992 /* Initialize some variables in our dev structure */
993 priv
->num_txbdfree
= priv
->tx_ring_size
;
994 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
995 priv
->cur_rx
= priv
->rx_bd_base
;
996 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
999 /* Initialize Transmit Descriptor Ring */
1000 txbdp
= priv
->tx_bd_base
;
1001 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
1007 /* Set the last descriptor in the ring to indicate wrap */
1009 txbdp
->status
|= TXBD_WRAP
;
1011 rxbdp
= priv
->rx_bd_base
;
1012 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
1013 struct sk_buff
*skb
;
1015 skb
= gfar_new_skb(dev
);
1018 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
1021 goto err_rxalloc_fail
;
1024 priv
->rx_skbuff
[i
] = skb
;
1026 gfar_new_rxbdp(dev
, rxbdp
, skb
);
1031 /* Set the last descriptor in the ring to wrap */
1033 rxbdp
->status
|= RXBD_WRAP
;
1035 /* If the device has multiple interrupts, register for
1036 * them. Otherwise, only register for the one */
1037 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1038 /* Install our interrupt handlers for Error,
1039 * Transmit, and Receive */
1040 if (request_irq(priv
->interruptError
, gfar_error
,
1041 0, priv
->int_name_er
, dev
) < 0) {
1042 if (netif_msg_intr(priv
))
1043 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1044 dev
->name
, priv
->interruptError
);
1050 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
1051 0, priv
->int_name_tx
, dev
) < 0) {
1052 if (netif_msg_intr(priv
))
1053 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1054 dev
->name
, priv
->interruptTransmit
);
1061 if (request_irq(priv
->interruptReceive
, gfar_receive
,
1062 0, priv
->int_name_rx
, dev
) < 0) {
1063 if (netif_msg_intr(priv
))
1064 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
1065 dev
->name
, priv
->interruptReceive
);
1071 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
1072 0, priv
->int_name_tx
, dev
) < 0) {
1073 if (netif_msg_intr(priv
))
1074 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1075 dev
->name
, priv
->interruptTransmit
);
1082 phy_start(priv
->phydev
);
1084 /* Configure the coalescing support */
1085 gfar_write(®s
->txic
, 0);
1086 if (priv
->txcoalescing
)
1087 gfar_write(®s
->txic
, priv
->txic
);
1089 gfar_write(®s
->rxic
, 0);
1090 if (priv
->rxcoalescing
)
1091 gfar_write(®s
->rxic
, priv
->rxic
);
1093 if (priv
->rx_csum_enable
)
1094 rctrl
|= RCTRL_CHECKSUMMING
;
1096 if (priv
->extended_hash
) {
1097 rctrl
|= RCTRL_EXTHASH
;
1099 gfar_clear_exact_match(dev
);
1100 rctrl
|= RCTRL_EMEN
;
1103 if (priv
->padding
) {
1104 rctrl
&= ~RCTRL_PAL_MASK
;
1105 rctrl
|= RCTRL_PADDING(priv
->padding
);
1108 /* Init rctrl based on our settings */
1109 gfar_write(&priv
->regs
->rctrl
, rctrl
);
1111 if (dev
->features
& NETIF_F_IP_CSUM
)
1112 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
1114 /* Set the extraction length and index */
1115 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
1116 ATTRELI_EI(priv
->rx_stash_index
);
1118 gfar_write(&priv
->regs
->attreli
, attrs
);
1120 /* Start with defaults, and add stashing or locking
1121 * depending on the approprate variables */
1122 attrs
= ATTR_INIT_SETTINGS
;
1124 if (priv
->bd_stash_en
)
1125 attrs
|= ATTR_BDSTASH
;
1127 if (priv
->rx_stash_size
!= 0)
1128 attrs
|= ATTR_BUFSTASH
;
1130 gfar_write(&priv
->regs
->attr
, attrs
);
1132 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1133 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1134 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1136 /* Start the controller */
1142 free_irq(priv
->interruptTransmit
, dev
);
1144 free_irq(priv
->interruptError
, dev
);
1148 free_skb_resources(priv
);
1150 dma_free_coherent(&dev
->dev
,
1151 sizeof(struct txbd8
)*priv
->tx_ring_size
1152 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1154 gfar_read(®s
->tbase0
));
1159 /* Called when something needs to use the ethernet device */
1160 /* Returns 0 for success. */
1161 static int gfar_enet_open(struct net_device
*dev
)
1163 struct gfar_private
*priv
= netdev_priv(dev
);
1166 napi_enable(&priv
->napi
);
1168 /* Initialize a bunch of registers */
1169 init_registers(dev
);
1171 gfar_set_mac_address(dev
);
1173 err
= init_phy(dev
);
1176 napi_disable(&priv
->napi
);
1180 err
= startup_gfar(dev
);
1182 napi_disable(&priv
->napi
);
1186 netif_start_queue(dev
);
1191 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1193 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1195 cacheable_memzero(fcb
, GMAC_FCB_LEN
);
1200 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1204 /* If we're here, it's a IP packet with a TCP or UDP
1205 * payload. We set it to checksum, using a pseudo-header
1208 flags
= TXFCB_DEFAULT
;
1210 /* Tell the controller what the protocol is */
1211 /* And provide the already calculated phcs */
1212 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1214 fcb
->phcs
= udp_hdr(skb
)->check
;
1216 fcb
->phcs
= tcp_hdr(skb
)->check
;
1218 /* l3os is the distance between the start of the
1219 * frame (skb->data) and the start of the IP hdr.
1220 * l4os is the distance between the start of the
1221 * l3 hdr and the l4 hdr */
1222 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1223 fcb
->l4os
= skb_network_header_len(skb
);
1228 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1230 fcb
->flags
|= TXFCB_VLN
;
1231 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1234 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1235 struct txbd8
*base
, int ring_size
)
1237 struct txbd8
*new_bd
= bdp
+ stride
;
1239 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1242 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1245 return skip_txbd(bdp
, 1, base
, ring_size
);
1248 /* This is called by the kernel when a frame is ready for transmission. */
1249 /* It is pointed to by the dev->hard_start_xmit function pointer */
1250 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1252 struct gfar_private
*priv
= netdev_priv(dev
);
1253 struct txfcb
*fcb
= NULL
;
1254 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1258 unsigned long flags
;
1259 unsigned int nr_frags
, length
;
1261 base
= priv
->tx_bd_base
;
1263 /* total number of fragments in the SKB */
1264 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1266 spin_lock_irqsave(&priv
->txlock
, flags
);
1268 /* check if there is space to queue this packet */
1269 if (nr_frags
> priv
->num_txbdfree
) {
1270 /* no space, stop the queue */
1271 netif_stop_queue(dev
);
1272 dev
->stats
.tx_fifo_errors
++;
1273 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1274 return NETDEV_TX_BUSY
;
1277 /* Update transmit stats */
1278 dev
->stats
.tx_bytes
+= skb
->len
;
1280 txbdp
= txbdp_start
= priv
->cur_tx
;
1282 if (nr_frags
== 0) {
1283 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1285 /* Place the fragment addresses and lengths into the TxBDs */
1286 for (i
= 0; i
< nr_frags
; i
++) {
1287 /* Point at the next BD, wrapping as needed */
1288 txbdp
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1290 length
= skb_shinfo(skb
)->frags
[i
].size
;
1292 lstatus
= txbdp
->lstatus
| length
|
1293 BD_LFLAG(TXBD_READY
);
1295 /* Handle the last BD specially */
1296 if (i
== nr_frags
- 1)
1297 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1299 bufaddr
= dma_map_page(&dev
->dev
,
1300 skb_shinfo(skb
)->frags
[i
].page
,
1301 skb_shinfo(skb
)->frags
[i
].page_offset
,
1305 /* set the TxBD length and buffer pointer */
1306 txbdp
->bufPtr
= bufaddr
;
1307 txbdp
->lstatus
= lstatus
;
1310 lstatus
= txbdp_start
->lstatus
;
1313 /* Set up checksumming */
1314 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1315 fcb
= gfar_add_fcb(skb
);
1316 lstatus
|= BD_LFLAG(TXBD_TOE
);
1317 gfar_tx_checksum(skb
, fcb
);
1320 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1321 if (unlikely(NULL
== fcb
)) {
1322 fcb
= gfar_add_fcb(skb
);
1323 lstatus
|= BD_LFLAG(TXBD_TOE
);
1326 gfar_tx_vlan(skb
, fcb
);
1329 /* setup the TxBD length and buffer pointer for the first BD */
1330 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1331 txbdp_start
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1332 skb_headlen(skb
), DMA_TO_DEVICE
);
1334 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1337 * The powerpc-specific eieio() is used, as wmb() has too strong
1338 * semantics (it requires synchronization between cacheable and
1339 * uncacheable mappings, which eieio doesn't provide and which we
1340 * don't need), thus requiring a more expensive sync instruction. At
1341 * some point, the set of architecture-independent barrier functions
1342 * should be expanded to include weaker barriers.
1346 txbdp_start
->lstatus
= lstatus
;
1348 /* Update the current skb pointer to the next entry we will use
1349 * (wrapping if necessary) */
1350 priv
->skb_curtx
= (priv
->skb_curtx
+ 1) &
1351 TX_RING_MOD_MASK(priv
->tx_ring_size
);
1353 priv
->cur_tx
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1355 /* reduce TxBD free count */
1356 priv
->num_txbdfree
-= (nr_frags
+ 1);
1358 dev
->trans_start
= jiffies
;
1360 /* If the next BD still needs to be cleaned up, then the bds
1361 are full. We need to tell the kernel to stop sending us stuff. */
1362 if (!priv
->num_txbdfree
) {
1363 netif_stop_queue(dev
);
1365 dev
->stats
.tx_fifo_errors
++;
1368 /* Tell the DMA to go go go */
1369 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1372 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1377 /* Stops the kernel queue, and halts the controller */
1378 static int gfar_close(struct net_device
*dev
)
1380 struct gfar_private
*priv
= netdev_priv(dev
);
1382 napi_disable(&priv
->napi
);
1384 cancel_work_sync(&priv
->reset_task
);
1387 /* Disconnect from the PHY */
1388 phy_disconnect(priv
->phydev
);
1389 priv
->phydev
= NULL
;
1391 netif_stop_queue(dev
);
1396 /* Changes the mac address if the controller is not running. */
1397 static int gfar_set_mac_address(struct net_device
*dev
)
1399 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1405 /* Enables and disables VLAN insertion/extraction */
1406 static void gfar_vlan_rx_register(struct net_device
*dev
,
1407 struct vlan_group
*grp
)
1409 struct gfar_private
*priv
= netdev_priv(dev
);
1410 unsigned long flags
;
1411 struct vlan_group
*old_grp
;
1414 spin_lock_irqsave(&priv
->rxlock
, flags
);
1416 old_grp
= priv
->vlgrp
;
1422 /* Enable VLAN tag insertion */
1423 tempval
= gfar_read(&priv
->regs
->tctrl
);
1424 tempval
|= TCTRL_VLINS
;
1426 gfar_write(&priv
->regs
->tctrl
, tempval
);
1428 /* Enable VLAN tag extraction */
1429 tempval
= gfar_read(&priv
->regs
->rctrl
);
1430 tempval
|= RCTRL_VLEX
;
1431 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
1432 gfar_write(&priv
->regs
->rctrl
, tempval
);
1434 /* Disable VLAN tag insertion */
1435 tempval
= gfar_read(&priv
->regs
->tctrl
);
1436 tempval
&= ~TCTRL_VLINS
;
1437 gfar_write(&priv
->regs
->tctrl
, tempval
);
1439 /* Disable VLAN tag extraction */
1440 tempval
= gfar_read(&priv
->regs
->rctrl
);
1441 tempval
&= ~RCTRL_VLEX
;
1442 /* If parse is no longer required, then disable parser */
1443 if (tempval
& RCTRL_REQ_PARSER
)
1444 tempval
|= RCTRL_PRSDEP_INIT
;
1446 tempval
&= ~RCTRL_PRSDEP_INIT
;
1447 gfar_write(&priv
->regs
->rctrl
, tempval
);
1450 gfar_change_mtu(dev
, dev
->mtu
);
1452 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1455 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1457 int tempsize
, tempval
;
1458 struct gfar_private
*priv
= netdev_priv(dev
);
1459 int oldsize
= priv
->rx_buffer_size
;
1460 int frame_size
= new_mtu
+ ETH_HLEN
;
1463 frame_size
+= VLAN_HLEN
;
1465 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1466 if (netif_msg_drv(priv
))
1467 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1472 if (gfar_uses_fcb(priv
))
1473 frame_size
+= GMAC_FCB_LEN
;
1475 frame_size
+= priv
->padding
;
1478 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1479 INCREMENTAL_BUFFER_SIZE
;
1481 /* Only stop and start the controller if it isn't already
1482 * stopped, and we changed something */
1483 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1486 priv
->rx_buffer_size
= tempsize
;
1490 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1491 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1493 /* If the mtu is larger than the max size for standard
1494 * ethernet frames (ie, a jumbo frame), then set maccfg2
1495 * to allow huge frames, and to check the length */
1496 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1498 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1499 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1501 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1503 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1505 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1511 /* gfar_reset_task gets scheduled when a packet has not been
1512 * transmitted after a set amount of time.
1513 * For now, assume that clearing out all the structures, and
1514 * starting over will fix the problem.
1516 static void gfar_reset_task(struct work_struct
*work
)
1518 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1520 struct net_device
*dev
= priv
->dev
;
1522 if (dev
->flags
& IFF_UP
) {
1527 netif_tx_schedule_all(dev
);
1530 static void gfar_timeout(struct net_device
*dev
)
1532 struct gfar_private
*priv
= netdev_priv(dev
);
1534 dev
->stats
.tx_errors
++;
1535 schedule_work(&priv
->reset_task
);
1538 /* Interrupt Handler for Transmit complete */
1539 static int gfar_clean_tx_ring(struct net_device
*dev
)
1541 struct gfar_private
*priv
= netdev_priv(dev
);
1543 struct txbd8
*lbdp
= NULL
;
1544 struct txbd8
*base
= priv
->tx_bd_base
;
1545 struct sk_buff
*skb
;
1547 int tx_ring_size
= priv
->tx_ring_size
;
1553 bdp
= priv
->dirty_tx
;
1554 skb_dirtytx
= priv
->skb_dirtytx
;
1556 while ((skb
= priv
->tx_skbuff
[skb_dirtytx
])) {
1557 frags
= skb_shinfo(skb
)->nr_frags
;
1558 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
1560 lstatus
= lbdp
->lstatus
;
1562 /* Only clean completed frames */
1563 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
1564 (lstatus
& BD_LENGTH_MASK
))
1567 dma_unmap_single(&dev
->dev
,
1572 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1573 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1575 for (i
= 0; i
< frags
; i
++) {
1576 dma_unmap_page(&dev
->dev
,
1580 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1581 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1584 dev_kfree_skb_any(skb
);
1585 priv
->tx_skbuff
[skb_dirtytx
] = NULL
;
1587 skb_dirtytx
= (skb_dirtytx
+ 1) &
1588 TX_RING_MOD_MASK(tx_ring_size
);
1591 priv
->num_txbdfree
+= frags
+ 1;
1594 /* If we freed a buffer, we can restart transmission, if necessary */
1595 if (netif_queue_stopped(dev
) && priv
->num_txbdfree
)
1596 netif_wake_queue(dev
);
1598 /* Update dirty indicators */
1599 priv
->skb_dirtytx
= skb_dirtytx
;
1600 priv
->dirty_tx
= bdp
;
1602 dev
->stats
.tx_packets
+= howmany
;
1607 static void gfar_schedule_cleanup(struct net_device
*dev
)
1609 struct gfar_private
*priv
= netdev_priv(dev
);
1610 if (netif_rx_schedule_prep(&priv
->napi
)) {
1611 gfar_write(&priv
->regs
->imask
, IMASK_RTX_DISABLED
);
1612 __netif_rx_schedule(&priv
->napi
);
1616 /* Interrupt Handler for Transmit complete */
1617 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1619 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1623 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1624 struct sk_buff
*skb
)
1626 struct gfar_private
*priv
= netdev_priv(dev
);
1629 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1630 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1632 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
1634 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1635 lstatus
|= BD_LFLAG(RXBD_WRAP
);
1639 bdp
->lstatus
= lstatus
;
1643 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1645 unsigned int alignamount
;
1646 struct gfar_private
*priv
= netdev_priv(dev
);
1647 struct sk_buff
*skb
= NULL
;
1649 /* We have to allocate the skb, so keep trying till we succeed */
1650 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1655 alignamount
= RXBUF_ALIGNMENT
-
1656 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1658 /* We need the data buffer to be aligned properly. We will reserve
1659 * as many bytes as needed to align the data properly
1661 skb_reserve(skb
, alignamount
);
1666 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1668 struct gfar_private
*priv
= netdev_priv(dev
);
1669 struct net_device_stats
*stats
= &dev
->stats
;
1670 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1672 /* If the packet was truncated, none of the other errors
1674 if (status
& RXBD_TRUNCATED
) {
1675 stats
->rx_length_errors
++;
1681 /* Count the errors, if there were any */
1682 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1683 stats
->rx_length_errors
++;
1685 if (status
& RXBD_LARGE
)
1690 if (status
& RXBD_NONOCTET
) {
1691 stats
->rx_frame_errors
++;
1692 estats
->rx_nonoctet
++;
1694 if (status
& RXBD_CRCERR
) {
1695 estats
->rx_crcerr
++;
1696 stats
->rx_crc_errors
++;
1698 if (status
& RXBD_OVERRUN
) {
1699 estats
->rx_overrun
++;
1700 stats
->rx_crc_errors
++;
1704 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1706 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1710 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1712 /* If valid headers were found, and valid sums
1713 * were verified, then we tell the kernel that no
1714 * checksumming is necessary. Otherwise, it is */
1715 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1716 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1718 skb
->ip_summed
= CHECKSUM_NONE
;
1722 /* gfar_process_frame() -- handle one incoming packet if skb
1724 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1727 struct gfar_private
*priv
= netdev_priv(dev
);
1728 struct rxfcb
*fcb
= NULL
;
1732 /* fcb is at the beginning if exists */
1733 fcb
= (struct rxfcb
*)skb
->data
;
1735 /* Remove the FCB from the skb */
1736 /* Remove the padded bytes, if there are any */
1738 skb_pull(skb
, amount_pull
);
1740 if (priv
->rx_csum_enable
)
1741 gfar_rx_checksum(skb
, fcb
);
1743 /* Tell the skb what kind of packet this is */
1744 skb
->protocol
= eth_type_trans(skb
, dev
);
1746 /* Send the packet up the stack */
1747 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1748 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
1750 ret
= netif_receive_skb(skb
);
1752 if (NET_RX_DROP
== ret
)
1753 priv
->extra_stats
.kernel_dropped
++;
1758 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1759 * until the budget/quota has been reached. Returns the number
1762 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1764 struct rxbd8
*bdp
, *base
;
1765 struct sk_buff
*skb
;
1769 struct gfar_private
*priv
= netdev_priv(dev
);
1771 /* Get the first full descriptor */
1773 base
= priv
->rx_bd_base
;
1775 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
1778 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1779 struct sk_buff
*newskb
;
1782 /* Add another skb for the future */
1783 newskb
= gfar_new_skb(dev
);
1785 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1787 dma_unmap_single(&priv
->dev
->dev
, bdp
->bufPtr
,
1788 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1790 /* We drop the frame if we failed to allocate a new buffer */
1791 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1792 bdp
->status
& RXBD_ERR
)) {
1793 count_errors(bdp
->status
, dev
);
1795 if (unlikely(!newskb
))
1798 dev_kfree_skb_any(skb
);
1800 /* Increment the number of packets */
1801 dev
->stats
.rx_packets
++;
1805 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
1806 /* Remove the FCS from the packet length */
1807 skb_put(skb
, pkt_len
);
1808 dev
->stats
.rx_bytes
+= pkt_len
;
1810 gfar_process_frame(dev
, skb
, amount_pull
);
1813 if (netif_msg_rx_err(priv
))
1815 "%s: Missing skb!\n", dev
->name
);
1816 dev
->stats
.rx_dropped
++;
1817 priv
->extra_stats
.rx_skbmissing
++;
1822 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1824 /* Setup the new bdp */
1825 gfar_new_rxbdp(dev
, bdp
, newskb
);
1827 /* Update to the next pointer */
1828 bdp
= next_bd(bdp
, base
, priv
->rx_ring_size
);
1830 /* update to point at the next skb */
1832 (priv
->skb_currx
+ 1) &
1833 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1836 /* Update the current rxbd pointer to be the next one */
1842 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1844 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1845 struct net_device
*dev
= priv
->dev
;
1848 unsigned long flags
;
1850 /* Clear IEVENT, so interrupts aren't called again
1851 * because of the packets that have already arrived */
1852 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1854 /* If we fail to get the lock, don't bother with the TX BDs */
1855 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1856 tx_cleaned
= gfar_clean_tx_ring(dev
);
1857 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1860 rx_cleaned
= gfar_clean_rx_ring(dev
, budget
);
1865 if (rx_cleaned
< budget
) {
1866 netif_rx_complete(napi
);
1868 /* Clear the halt bit in RSTAT */
1869 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1871 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1873 /* If we are coalescing interrupts, update the timer */
1874 /* Otherwise, clear it */
1875 if (likely(priv
->rxcoalescing
)) {
1876 gfar_write(&priv
->regs
->rxic
, 0);
1877 gfar_write(&priv
->regs
->rxic
, priv
->rxic
);
1879 if (likely(priv
->txcoalescing
)) {
1880 gfar_write(&priv
->regs
->txic
, 0);
1881 gfar_write(&priv
->regs
->txic
, priv
->txic
);
1888 #ifdef CONFIG_NET_POLL_CONTROLLER
1890 * Polling 'interrupt' - used by things like netconsole to send skbs
1891 * without having to re-enable interrupts. It's not called while
1892 * the interrupt routine is executing.
1894 static void gfar_netpoll(struct net_device
*dev
)
1896 struct gfar_private
*priv
= netdev_priv(dev
);
1898 /* If the device has multiple interrupts, run tx/rx */
1899 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1900 disable_irq(priv
->interruptTransmit
);
1901 disable_irq(priv
->interruptReceive
);
1902 disable_irq(priv
->interruptError
);
1903 gfar_interrupt(priv
->interruptTransmit
, dev
);
1904 enable_irq(priv
->interruptError
);
1905 enable_irq(priv
->interruptReceive
);
1906 enable_irq(priv
->interruptTransmit
);
1908 disable_irq(priv
->interruptTransmit
);
1909 gfar_interrupt(priv
->interruptTransmit
, dev
);
1910 enable_irq(priv
->interruptTransmit
);
1915 /* The interrupt handler for devices with one interrupt */
1916 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1918 struct net_device
*dev
= dev_id
;
1919 struct gfar_private
*priv
= netdev_priv(dev
);
1921 /* Save ievent for future reference */
1922 u32 events
= gfar_read(&priv
->regs
->ievent
);
1924 /* Check for reception */
1925 if (events
& IEVENT_RX_MASK
)
1926 gfar_receive(irq
, dev_id
);
1928 /* Check for transmit completion */
1929 if (events
& IEVENT_TX_MASK
)
1930 gfar_transmit(irq
, dev_id
);
1932 /* Check for errors */
1933 if (events
& IEVENT_ERR_MASK
)
1934 gfar_error(irq
, dev_id
);
1939 /* Called every time the controller might need to be made
1940 * aware of new link state. The PHY code conveys this
1941 * information through variables in the phydev structure, and this
1942 * function converts those variables into the appropriate
1943 * register values, and can bring down the device if needed.
1945 static void adjust_link(struct net_device
*dev
)
1947 struct gfar_private
*priv
= netdev_priv(dev
);
1948 struct gfar __iomem
*regs
= priv
->regs
;
1949 unsigned long flags
;
1950 struct phy_device
*phydev
= priv
->phydev
;
1953 spin_lock_irqsave(&priv
->txlock
, flags
);
1955 u32 tempval
= gfar_read(®s
->maccfg2
);
1956 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1958 /* Now we make sure that we can be in full duplex mode.
1959 * If not, we operate in half-duplex mode. */
1960 if (phydev
->duplex
!= priv
->oldduplex
) {
1962 if (!(phydev
->duplex
))
1963 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1965 tempval
|= MACCFG2_FULL_DUPLEX
;
1967 priv
->oldduplex
= phydev
->duplex
;
1970 if (phydev
->speed
!= priv
->oldspeed
) {
1972 switch (phydev
->speed
) {
1975 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1980 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1982 /* Reduced mode distinguishes
1983 * between 10 and 100 */
1984 if (phydev
->speed
== SPEED_100
)
1985 ecntrl
|= ECNTRL_R100
;
1987 ecntrl
&= ~(ECNTRL_R100
);
1990 if (netif_msg_link(priv
))
1992 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1993 dev
->name
, phydev
->speed
);
1997 priv
->oldspeed
= phydev
->speed
;
2000 gfar_write(®s
->maccfg2
, tempval
);
2001 gfar_write(®s
->ecntrl
, ecntrl
);
2003 if (!priv
->oldlink
) {
2007 } else if (priv
->oldlink
) {
2011 priv
->oldduplex
= -1;
2014 if (new_state
&& netif_msg_link(priv
))
2015 phy_print_status(phydev
);
2017 spin_unlock_irqrestore(&priv
->txlock
, flags
);
2020 /* Update the hash table based on the current list of multicast
2021 * addresses we subscribe to. Also, change the promiscuity of
2022 * the device based on the flags (this function is called
2023 * whenever dev->flags is changed */
2024 static void gfar_set_multi(struct net_device
*dev
)
2026 struct dev_mc_list
*mc_ptr
;
2027 struct gfar_private
*priv
= netdev_priv(dev
);
2028 struct gfar __iomem
*regs
= priv
->regs
;
2031 if(dev
->flags
& IFF_PROMISC
) {
2032 /* Set RCTRL to PROM */
2033 tempval
= gfar_read(®s
->rctrl
);
2034 tempval
|= RCTRL_PROM
;
2035 gfar_write(®s
->rctrl
, tempval
);
2037 /* Set RCTRL to not PROM */
2038 tempval
= gfar_read(®s
->rctrl
);
2039 tempval
&= ~(RCTRL_PROM
);
2040 gfar_write(®s
->rctrl
, tempval
);
2043 if(dev
->flags
& IFF_ALLMULTI
) {
2044 /* Set the hash to rx all multicast frames */
2045 gfar_write(®s
->igaddr0
, 0xffffffff);
2046 gfar_write(®s
->igaddr1
, 0xffffffff);
2047 gfar_write(®s
->igaddr2
, 0xffffffff);
2048 gfar_write(®s
->igaddr3
, 0xffffffff);
2049 gfar_write(®s
->igaddr4
, 0xffffffff);
2050 gfar_write(®s
->igaddr5
, 0xffffffff);
2051 gfar_write(®s
->igaddr6
, 0xffffffff);
2052 gfar_write(®s
->igaddr7
, 0xffffffff);
2053 gfar_write(®s
->gaddr0
, 0xffffffff);
2054 gfar_write(®s
->gaddr1
, 0xffffffff);
2055 gfar_write(®s
->gaddr2
, 0xffffffff);
2056 gfar_write(®s
->gaddr3
, 0xffffffff);
2057 gfar_write(®s
->gaddr4
, 0xffffffff);
2058 gfar_write(®s
->gaddr5
, 0xffffffff);
2059 gfar_write(®s
->gaddr6
, 0xffffffff);
2060 gfar_write(®s
->gaddr7
, 0xffffffff);
2065 /* zero out the hash */
2066 gfar_write(®s
->igaddr0
, 0x0);
2067 gfar_write(®s
->igaddr1
, 0x0);
2068 gfar_write(®s
->igaddr2
, 0x0);
2069 gfar_write(®s
->igaddr3
, 0x0);
2070 gfar_write(®s
->igaddr4
, 0x0);
2071 gfar_write(®s
->igaddr5
, 0x0);
2072 gfar_write(®s
->igaddr6
, 0x0);
2073 gfar_write(®s
->igaddr7
, 0x0);
2074 gfar_write(®s
->gaddr0
, 0x0);
2075 gfar_write(®s
->gaddr1
, 0x0);
2076 gfar_write(®s
->gaddr2
, 0x0);
2077 gfar_write(®s
->gaddr3
, 0x0);
2078 gfar_write(®s
->gaddr4
, 0x0);
2079 gfar_write(®s
->gaddr5
, 0x0);
2080 gfar_write(®s
->gaddr6
, 0x0);
2081 gfar_write(®s
->gaddr7
, 0x0);
2083 /* If we have extended hash tables, we need to
2084 * clear the exact match registers to prepare for
2086 if (priv
->extended_hash
) {
2087 em_num
= GFAR_EM_NUM
+ 1;
2088 gfar_clear_exact_match(dev
);
2095 if(dev
->mc_count
== 0)
2098 /* Parse the list, and set the appropriate bits */
2099 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2101 gfar_set_mac_for_addr(dev
, idx
,
2105 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2113 /* Clears each of the exact match registers to zero, so they
2114 * don't interfere with normal reception */
2115 static void gfar_clear_exact_match(struct net_device
*dev
)
2118 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2120 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2121 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2124 /* Set the appropriate hash bit for the given addr */
2125 /* The algorithm works like so:
2126 * 1) Take the Destination Address (ie the multicast address), and
2127 * do a CRC on it (little endian), and reverse the bits of the
2129 * 2) Use the 8 most significant bits as a hash into a 256-entry
2130 * table. The table is controlled through 8 32-bit registers:
2131 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2132 * gaddr7. This means that the 3 most significant bits in the
2133 * hash index which gaddr register to use, and the 5 other bits
2134 * indicate which bit (assuming an IBM numbering scheme, which
2135 * for PowerPC (tm) is usually the case) in the register holds
2137 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2140 struct gfar_private
*priv
= netdev_priv(dev
);
2141 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2142 int width
= priv
->hash_width
;
2143 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2144 u8 whichreg
= result
>> (32 - width
+ 5);
2145 u32 value
= (1 << (31-whichbit
));
2147 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2149 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2155 /* There are multiple MAC Address register pairs on some controllers
2156 * This function sets the numth pair to a given address
2158 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2160 struct gfar_private
*priv
= netdev_priv(dev
);
2162 char tmpbuf
[MAC_ADDR_LEN
];
2164 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2168 /* Now copy it into the mac registers backwards, cuz */
2169 /* little endian is silly */
2170 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2171 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2173 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2175 tempval
= *((u32
*) (tmpbuf
+ 4));
2177 gfar_write(macptr
+1, tempval
);
2180 /* GFAR error interrupt handler */
2181 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2183 struct net_device
*dev
= dev_id
;
2184 struct gfar_private
*priv
= netdev_priv(dev
);
2186 /* Save ievent for future reference */
2187 u32 events
= gfar_read(&priv
->regs
->ievent
);
2190 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2192 /* Magic Packet is not an error. */
2193 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2194 (events
& IEVENT_MAG
))
2195 events
&= ~IEVENT_MAG
;
2198 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2199 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2200 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2202 /* Update the error counters */
2203 if (events
& IEVENT_TXE
) {
2204 dev
->stats
.tx_errors
++;
2206 if (events
& IEVENT_LC
)
2207 dev
->stats
.tx_window_errors
++;
2208 if (events
& IEVENT_CRL
)
2209 dev
->stats
.tx_aborted_errors
++;
2210 if (events
& IEVENT_XFUN
) {
2211 if (netif_msg_tx_err(priv
))
2212 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2213 "packet dropped.\n", dev
->name
);
2214 dev
->stats
.tx_dropped
++;
2215 priv
->extra_stats
.tx_underrun
++;
2217 /* Reactivate the Tx Queues */
2218 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2220 if (netif_msg_tx_err(priv
))
2221 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2223 if (events
& IEVENT_BSY
) {
2224 dev
->stats
.rx_errors
++;
2225 priv
->extra_stats
.rx_bsy
++;
2227 gfar_receive(irq
, dev_id
);
2229 if (netif_msg_rx_err(priv
))
2230 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2231 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2233 if (events
& IEVENT_BABR
) {
2234 dev
->stats
.rx_errors
++;
2235 priv
->extra_stats
.rx_babr
++;
2237 if (netif_msg_rx_err(priv
))
2238 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2240 if (events
& IEVENT_EBERR
) {
2241 priv
->extra_stats
.eberr
++;
2242 if (netif_msg_rx_err(priv
))
2243 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2245 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2246 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2248 if (events
& IEVENT_BABT
) {
2249 priv
->extra_stats
.tx_babt
++;
2250 if (netif_msg_tx_err(priv
))
2251 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2256 /* work with hotplug and coldplug */
2257 MODULE_ALIAS("platform:fsl-gianfar");
2259 static struct of_device_id gfar_match
[] =
2263 .compatible
= "gianfar",
2268 /* Structure for a device driver */
2269 static struct of_platform_driver gfar_driver
= {
2270 .name
= "fsl-gianfar",
2271 .match_table
= gfar_match
,
2273 .probe
= gfar_probe
,
2274 .remove
= gfar_remove
,
2275 .suspend
= gfar_suspend
,
2276 .resume
= gfar_resume
,
2279 static int __init
gfar_init(void)
2281 int err
= gfar_mdio_init();
2286 err
= of_register_platform_driver(&gfar_driver
);
2294 static void __exit
gfar_exit(void)
2296 of_unregister_platform_driver(&gfar_driver
);
2300 module_init(gfar_init
);
2301 module_exit(gfar_exit
);