2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/procinfo.h>
35 #include <asm/ptrace.h>
38 * This is the maximum size of an area which will be invalidated
39 * using the single invalidate entry instructions. Anything larger
40 * than this, and we go for the whole cache.
42 * This value should be chosen such that we choose the cheapest
45 #define MAX_AREA_SIZE 32768
48 * The size of one data cache line.
50 #define CACHE_DLINESIZE 32
53 * The number of data cache segments.
55 #define CACHE_DSEGMENTS 16
58 * The number of lines in a cache segment.
60 #define CACHE_DENTRIES 64
63 * This is the size at which it becomes more efficient to
64 * clean the whole cache, rather than using the individual
65 * cache line maintainence instructions.
67 #define CACHE_DLIMIT 32768
71 * cpu_arm1020e_proc_init()
73 ENTRY(cpu_arm1020e_proc_init)
77 * cpu_arm1020e_proc_fin()
79 ENTRY(cpu_arm1020e_proc_fin)
81 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
83 bl arm1020e_flush_kern_cache_all
84 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
85 bic r0, r0, #0x1000 @ ...i............
86 bic r0, r0, #0x000e @ ............wca.
87 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 * cpu_arm1020e_reset(loc)
93 * Perform a soft reset of the system. Put the CPU into the
94 * same state as it would be if it had been reset, and branch
95 * to what would be the reset vector.
97 * loc: location to jump to for soft reset
100 ENTRY(cpu_arm1020e_reset)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
108 bic ip, ip, #0x000f @ ............wcam
109 bic ip, ip, #0x1100 @ ...i...s........
110 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 * cpu_arm1020e_do_idle()
117 ENTRY(cpu_arm1020e_do_idle)
118 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 /* ================================= CACHE ================================ */
125 * flush_user_cache_all()
127 * Invalidate all cache entries in a particular address
130 ENTRY(arm1020e_flush_user_cache_all)
133 * flush_kern_cache_all()
135 * Clean and invalidate the entire cache.
137 ENTRY(arm1020e_flush_kern_cache_all)
141 #ifndef CONFIG_CPU_DCACHE_DISABLE
142 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
144 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
145 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
146 subs r3, r3, #1 << 26
147 bcs 2b @ entries 63 to 0
149 bcs 1b @ segments 15 to 0
152 #ifndef CONFIG_CPU_ICACHE_DISABLE
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 * flush_user_cache_range(start, end, flags)
161 * Invalidate a range of cache entries in the specified
164 * - start - start address (inclusive)
165 * - end - end address (exclusive)
166 * - flags - vm_flags for this space
168 ENTRY(arm1020e_flush_user_cache_range)
170 sub r3, r1, r0 @ calculate total size
171 cmp r3, #CACHE_DLIMIT
172 bhs __flush_whole_cache
174 #ifndef CONFIG_CPU_DCACHE_DISABLE
175 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 add r0, r0, #CACHE_DLINESIZE
181 #ifndef CONFIG_CPU_ICACHE_DISABLE
182 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
184 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 * coherent_kern_range(start, end)
190 * Ensure coherency between the Icache and the Dcache in the
191 * region described by start. If you have non-snooping
192 * Harvard caches, you need to implement this function.
194 * - start - virtual start address
195 * - end - virtual end address
197 ENTRY(arm1020e_coherent_kern_range)
200 * coherent_user_range(start, end)
202 * Ensure coherency between the Icache and the Dcache in the
203 * region described by start. If you have non-snooping
204 * Harvard caches, you need to implement this function.
206 * - start - virtual start address
207 * - end - virtual end address
209 ENTRY(arm1020e_coherent_user_range)
211 bic r0, r0, #CACHE_DLINESIZE - 1
213 #ifndef CONFIG_CPU_DCACHE_DISABLE
214 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 #ifndef CONFIG_CPU_ICACHE_DISABLE
217 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
222 mcr p15, 0, ip, c7, c10, 4 @ drain WB
226 * flush_kern_dcache_page(void *page)
228 * Ensure no D cache aliasing occurs, either with itself or
231 * - page - page aligned address
233 ENTRY(arm1020e_flush_kern_dcache_page)
235 #ifndef CONFIG_CPU_DCACHE_DISABLE
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
238 add r0, r0, #CACHE_DLINESIZE
242 mcr p15, 0, ip, c7, c10, 4 @ drain WB
246 * dma_inv_range(start, end)
248 * Invalidate (discard) the specified virtual address range.
249 * May not write back any entries. If 'start' or 'end'
250 * are not cache line aligned, those lines must be written
253 * - start - virtual start address
254 * - end - virtual end address
258 ENTRY(arm1020e_dma_inv_range)
260 #ifndef CONFIG_CPU_DCACHE_DISABLE
261 tst r0, #CACHE_DLINESIZE - 1
262 bic r0, r0, #CACHE_DLINESIZE - 1
263 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
264 tst r1, #CACHE_DLINESIZE - 1
265 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
267 add r0, r0, #CACHE_DLINESIZE
271 mcr p15, 0, ip, c7, c10, 4 @ drain WB
275 * dma_clean_range(start, end)
277 * Clean the specified virtual address range.
279 * - start - virtual start address
280 * - end - virtual end address
284 ENTRY(arm1020e_dma_clean_range)
286 #ifndef CONFIG_CPU_DCACHE_DISABLE
287 bic r0, r0, #CACHE_DLINESIZE - 1
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
289 add r0, r0, #CACHE_DLINESIZE
293 mcr p15, 0, ip, c7, c10, 4 @ drain WB
297 * dma_flush_range(start, end)
299 * Clean and invalidate the specified virtual address range.
301 * - start - virtual start address
302 * - end - virtual end address
304 ENTRY(arm1020e_dma_flush_range)
306 #ifndef CONFIG_CPU_DCACHE_DISABLE
307 bic r0, r0, #CACHE_DLINESIZE - 1
308 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
309 add r0, r0, #CACHE_DLINESIZE
313 mcr p15, 0, ip, c7, c10, 4 @ drain WB
316 ENTRY(arm1020e_cache_fns)
317 .long arm1020e_flush_kern_cache_all
318 .long arm1020e_flush_user_cache_all
319 .long arm1020e_flush_user_cache_range
320 .long arm1020e_coherent_kern_range
321 .long arm1020e_coherent_user_range
322 .long arm1020e_flush_kern_dcache_page
323 .long arm1020e_dma_inv_range
324 .long arm1020e_dma_clean_range
325 .long arm1020e_dma_flush_range
328 ENTRY(cpu_arm1020e_dcache_clean_area)
329 #ifndef CONFIG_CPU_DCACHE_DISABLE
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 add r0, r0, #CACHE_DLINESIZE
333 subs r1, r1, #CACHE_DLINESIZE
338 /* =============================== PageTable ============================== */
341 * cpu_arm1020e_switch_mm(pgd)
343 * Set the translation base pointer to be as described by pgd.
345 * pgd: new page tables
348 ENTRY(cpu_arm1020e_switch_mm)
350 #ifndef CONFIG_CPU_DCACHE_DISABLE
351 mcr p15, 0, r3, c7, c10, 4
352 mov r1, #0xF @ 16 segments
353 1: mov r3, #0x3F @ 64 entries
354 2: mov ip, r3, LSL #26 @ shift up entry
355 orr ip, ip, r1, LSL #5 @ shift in/up index
356 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
360 bge 2b @ entries 3F to 0
363 bge 1b @ segments 15 to 0
367 #ifndef CONFIG_CPU_ICACHE_DISABLE
368 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
370 mcr p15, 0, r1, c7, c10, 4 @ drain WB
371 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
372 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
377 * cpu_arm1020e_set_pte(ptep, pte)
379 * Set a PTE and flush it out
382 ENTRY(cpu_arm1020e_set_pte)
384 str r1, [r0], #-2048 @ linux version
386 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
388 bic r2, r1, #PTE_SMALL_AP_MASK
389 bic r2, r2, #PTE_TYPE_MASK
390 orr r2, r2, #PTE_TYPE_SMALL
392 tst r1, #L_PTE_USER @ User?
393 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
395 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
396 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
398 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
401 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
402 eor r3, r1, #0x0a @ C & small page?
406 str r2, [r0] @ hardware version
408 #ifndef CONFIG_CPU_DCACHE_DISABLE
409 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
411 #endif /* CONFIG_MMU */
416 .type __arm1020e_setup, #function
419 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
420 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
422 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424 mrc p15, 0, r0, c1, c0 @ get control register v4
425 ldr r5, arm1020e_cr1_clear
427 ldr r5, arm1020e_cr1_set
429 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
430 orr r0, r0, #0x4000 @ .R.. .... .... ....
433 .size __arm1020e_setup, . - __arm1020e_setup
437 * .RVI ZFRS BLDP WCAM
438 * .011 1001 ..11 0101
440 .type arm1020e_cr1_clear, #object
441 .type arm1020e_cr1_set, #object
450 * Purpose : Function pointers used to access above functions - all calls
453 .type arm1020e_processor_functions, #object
454 arm1020e_processor_functions:
455 .word v4t_early_abort
456 .word cpu_arm1020e_proc_init
457 .word cpu_arm1020e_proc_fin
458 .word cpu_arm1020e_reset
459 .word cpu_arm1020e_do_idle
460 .word cpu_arm1020e_dcache_clean_area
461 .word cpu_arm1020e_switch_mm
462 .word cpu_arm1020e_set_pte
463 .size arm1020e_processor_functions, . - arm1020e_processor_functions
467 .type cpu_arch_name, #object
470 .size cpu_arch_name, . - cpu_arch_name
472 .type cpu_elf_name, #object
475 .size cpu_elf_name, . - cpu_elf_name
477 .type cpu_arm1020e_name, #object
480 #ifndef CONFIG_CPU_ICACHE_DISABLE
483 #ifndef CONFIG_CPU_DCACHE_DISABLE
485 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
491 #ifndef CONFIG_CPU_BPREDICT_DISABLE
494 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
498 .size cpu_arm1020e_name, . - cpu_arm1020e_name
502 .section ".proc.info.init", #alloc, #execinstr
504 .type __arm1020e_proc_info,#object
505 __arm1020e_proc_info:
506 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
508 .long PMD_TYPE_SECT | \
510 PMD_SECT_AP_WRITE | \
515 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
516 .long cpu_arm1020e_name
517 .long arm1020e_processor_functions
520 .long arm1020e_cache_fns
521 .size __arm1020e_proc_info, . - __arm1020e_proc_info