arch/mips/mips-boards/sim/sim_time.c

   1 #include <linux/types.h>
   2 #include <linux/init.h>
   3 #include <linux/kernel_stat.h>
   4 #include <linux/sched.h>
   5 #include <linux/spinlock.h>
   6
   7 #include <asm/mipsregs.h>
   8 #include <asm/ptrace.h>
   9 #include <asm/hardirq.h>
  10 #include <asm/div64.h>
  11 #include <asm/cpu.h>
  12 #include <asm/time.h>
  13
  14 #include <linux/interrupt.h>
  15 #include <linux/mc146818rtc.h>
  16 #include <linux/timex.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/hardirq.h>
  20 #include <asm/irq.h>
  21 #include <asm/div64.h>
  22 #include <asm/cpu.h>
  23 #include <asm/time.h>
  24 #include <asm/mc146818-time.h>
  25 #include <asm/msc01_ic.h>
  26
  27 #include <asm/mips-boards/generic.h>
  28 #include <asm/mips-boards/prom.h>
  29 #include <asm/mips-boards/simint.h>
  30 #include <asm/mc146818-time.h>
  31 #include <asm/smp.h>
  32
  33
  34 unsigned long cpu_khz;
  35
  36 extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
  37
  38 irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  39 {
  40 #ifdef CONFIG_SMP
  41         int cpu = smp_processor_id();
  42
  43         /*
  44          * CPU 0 handles the global timer interrupt job
  45          * resets count/compare registers to trigger next timer int.
  46          */
  47 #ifndef CONFIG_MIPS_MT_SMTC
  48         if (cpu == 0) {
  49                 timer_interrupt(irq, dev_id, regs);
  50         }
  51         else {
  52                 /* Everyone else needs to reset the timer int here as
  53                    ll_local_timer_interrupt doesn't */
  54                 /*
  55                  * FIXME: need to cope with counter underflow.
  56                  * More support needs to be added to kernel/time for
  57                  * counter/timer interrupts on multiple CPU's
  58                  */
  59                 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
  60         }
  61 #else /* SMTC */
  62         /*
  63          *  In SMTC system, one Count/Compare set exists per VPE.
  64          *  Which TC within a VPE gets the interrupt is essentially
  65          *  random - we only know that it shouldn't be one with
  66          *  IXMT set. Whichever TC gets the interrupt needs to
  67          *  send special interprocessor interrupts to the other
  68          *  TCs to make sure that they schedule, etc.
  69          *
  70          *  That code is specific to the SMTC kernel, not to
  71          *  the simulation platform, so it's invoked from
  72          *  the general MIPS timer_interrupt routine.
  73          *
  74          * We have a problem in that the interrupt vector code
  75          * had to turn off the timer IM bit to avoid redundant
  76          * entries, but we may never get to mips_cpu_irq_end
  77          * to turn it back on again if the scheduler gets
  78          * involved.  So we clear the pending timer here,
  79          * and re-enable the mask...
  80          */
  81
  82         int vpflags = dvpe();
  83         write_c0_compare (read_c0_count() - 1);
  84         clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR);
  85         set_c0_status(0x100 << MIPSCPU_INT_CPUCTR);
  86         irq_enable_hazard();
  87         evpe(vpflags);
  88
  89         if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs);
  90         else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
  91         smtc_timer_broadcast(cpu_data[cpu].vpe_id);
  92
  93 #endif /* CONFIG_MIPS_MT_SMTC */
  94
  95         /*
  96          * every CPU should do profiling and process accounting
  97          */
  98         local_timer_interrupt (irq, dev_id, regs);
  99         return IRQ_HANDLED;
 100 #else
 101         return timer_interrupt (irq, dev_id, regs);
 102 #endif
 103 }
 104
 105
 106
 107 /*
 108  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
 109  */
 110 static unsigned int __init estimate_cpu_frequency(void)
 111 {
 112         unsigned int prid = read_c0_prid() & 0xffff00;
 113         unsigned int count;
 114
 115 #if 1
 116         /*
 117          * hardwire the board frequency to 12MHz.
 118          */
 119
 120         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 121             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 122                 count = 12000000;
 123         else
 124                 count =  6000000;
 125 #else
 126         unsigned int flags;
 127
 128         local_irq_save(flags);
 129
 130         /* Start counter exactly on falling edge of update flag */
 131         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 132         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 133
 134         /* Start r4k counter. */
 135         write_c0_count(0);
 136
 137         /* Read counter exactly on falling edge of update flag */
 138         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 139         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 140
 141         count = read_c0_count();
 142
 143         /* restore interrupts */
 144         local_irq_restore(flags);
 145 #endif
 146
 147         mips_hpt_frequency = count;
 148
 149         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 150             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 151                 count *= 2;
 152
 153         count += 5000;    /* round */
 154         count -= count%10000;
 155
 156         return count;
 157 }
 158
 159 void __init sim_time_init(void)
 160 {
 161         unsigned int est_freq, flags;
 162
 163         local_irq_save(flags);
 164
 165
 166         /* Set Data mode - binary. */
 167         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 168
 169
 170         est_freq = estimate_cpu_frequency ();
 171
 172         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 173                (est_freq%1000000)*100/1000000);
 174
 175         cpu_khz = est_freq / 1000;
 176
 177         local_irq_restore(flags);
 178 }
 179
 180 static int mips_cpu_timer_irq;
 181
 182 static void mips_timer_dispatch (struct pt_regs *regs)
 183 {
 184         do_IRQ (mips_cpu_timer_irq, regs);
 185 }
 186
 187
 188 void __init sim_timer_setup(struct irqaction *irq)
 189 {
 190         if (cpu_has_veic) {
 191                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 192                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 193         }
 194         else {
 195                 if (cpu_has_vint)
 196                         set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 197                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 198         }
 199
 200         /* we are using the cpu counter for timer interrupts */
 201         irq->handler = sim_timer_interrupt;
 202         setup_irq(mips_cpu_timer_irq, irq);
 203
 204 #ifdef CONFIG_SMP
 205         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 206            on seperate cpu's the first one tries to handle the second interrupt.
 207            The effect is that the int remains disabled on the second cpu.
 208            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 209         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 210 #endif
 211
 212         /* to generate the first timer interrupt */
 213         write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 214 }