arch/mips/sibyte/sb1250/time.c

   1 /*
   2  * Copyright (C) 2000, 2001 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20  * These are routines to set up and handle interrupts from the
  21  * sb1250 general purpose timer 0.  We're using the timer as a
  22  * system clock, so we set it up to run at 100 Hz.  On every
  23  * interrupt, we update our idea of what the time of day is,
  24  * then call do_timer() in the architecture-independent kernel
  25  * code to do general bookkeeping (e.g. update jiffies, run
  26  * bottom halves, etc.)
  27  */
  28 #include <linux/interrupt.h>
  29 #include <linux/sched.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/kernel_stat.h>
  32
  33 #include <asm/irq.h>
  34 #include <asm/ptrace.h>
  35 #include <asm/addrspace.h>
  36 #include <asm/time.h>
  37 #include <asm/io.h>
  38
  39 #include <asm/sibyte/sb1250.h>
  40 #include <asm/sibyte/sb1250_regs.h>
  41 #include <asm/sibyte/sb1250_int.h>
  42 #include <asm/sibyte/sb1250_scd.h>
  43
  44
  45 #define IMR_IP2_VAL     K_INT_MAP_I0
  46 #define IMR_IP3_VAL     K_INT_MAP_I1
  47 #define IMR_IP4_VAL     K_INT_MAP_I2
  48
  49 #define SB1250_HPT_NUM          3
  50 #define SB1250_HPT_VALUE        M_SCD_TIMER_CNT /* max value */
  51 #define SB1250_HPT_SHIFT        ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
  52
  53
  54 extern int sb1250_steal_irq(int irq);
  55
  56 static unsigned int sb1250_hpt_read(void);
  57 static void sb1250_hpt_init(unsigned int);
  58
  59 static unsigned int hpt_offset;
  60
  61 void __init sb1250_hpt_setup(void)
  62 {
  63         int cpu = smp_processor_id();
  64
  65         if (!cpu) {
  66                 /* Setup hpt using timer #3 but do not enable irq for it */
  67                 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
  68                 __raw_writeq(SB1250_HPT_VALUE,
  69                              IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
  70                 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
  71                              IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
  72
  73                 /*
  74                  * we need to fill 32 bits, so just use the upper 23 bits and pretend
  75                  * the timer is going 512Mhz instead of 1Mhz
  76                  */
  77                 mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
  78                 mips_hpt_init = sb1250_hpt_init;
  79                 mips_hpt_read = sb1250_hpt_read;
  80         }
  81 }
  82
  83
  84 void sb1250_time_init(void)
  85 {
  86         int cpu = smp_processor_id();
  87         int irq = K_INT_TIMER_0+cpu;
  88
  89         /* Only have 4 general purpose timers, and we use last one as hpt */
  90         if (cpu > 2) {
  91                 BUG();
  92         }
  93
  94         sb1250_mask_irq(cpu, irq);
  95
  96         /* Map the timer interrupt to ip[4] of this cpu */
  97         __raw_writeq(IMR_IP4_VAL,
  98                      IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
  99                             (irq << 3)));
 100
 101         /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
 102         /* Disable the timer and set up the count */
 103         __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 104 #ifdef CONFIG_SIMULATION
 105         __raw_writeq((50000 / HZ) - 1,
 106                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 107 #else
 108         __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
 109                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 110 #endif
 111
 112         /* Set the timer running */
 113         __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
 114                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 115
 116         sb1250_unmask_irq(cpu, irq);
 117         sb1250_steal_irq(irq);
 118         /*
 119          * This interrupt is "special" in that it doesn't use the request_irq
 120          * way to hook the irq line.  The timer interrupt is initialized early
 121          * enough to make this a major pain, and it's also firing enough to
 122          * warrant a bit of special case code.  sb1250_timer_interrupt is
 123          * called directly from irq_handler.S when IP[4] is set during an
 124          * interrupt
 125          */
 126 }
 127
 128 void sb1250_timer_interrupt(struct pt_regs *regs)
 129 {
 130         int cpu = smp_processor_id();
 131         int irq = K_INT_TIMER_0 + cpu;
 132
 133         /* ACK interrupt */
 134         ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
 135                        IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 136
 137         if (cpu == 0) {
 138                 /*
 139                  * CPU 0 handles the global timer interrupt job
 140                  */
 141                 ll_timer_interrupt(irq, regs);
 142         }
 143         else {
 144                 /*
 145                  * other CPUs should just do profiling and process accounting
 146                  */
 147                 ll_local_timer_interrupt(irq, regs);
 148         }
 149 }
 150
 151 /*
 152  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
 153  * again. There's no easy way to set to a specific value so store init value
 154  * in hpt_offset and subtract each time.
 155  *
 156  * Note: Timer isn't full 32bits so shift it into the upper part making
 157  *       it appear to run at a higher frequency.
 158  */
 159 static unsigned int sb1250_hpt_read(void)
 160 {
 161         unsigned int count;
 162
 163         count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
 164
 165         count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
 166
 167         return count - hpt_offset;
 168 }
 169
 170 static void sb1250_hpt_init(unsigned int count)
 171 {
 172         hpt_offset = count;
 173         return;
 174 }