drivers/edac/amd76x_edac.c

   1 /*
   2  * AMD 76x Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_ids.h>
  19 #include <linux/slab.h>
  20 #include "edac_mc.h"
  21
  22 #define amd76x_printk(level, fmt, arg...) \
  23         edac_printk(level, "amd76x", fmt, ##arg)
  24
  25 #define amd76x_mc_printk(mci, level, fmt, arg...) \
  26         edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
  27
  28 #define AMD76X_NR_CSROWS 8
  29 #define AMD76X_NR_CHANS  1
  30 #define AMD76X_NR_DIMMS  4
  31
  32 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
  33
  34 #define AMD76X_ECC_MODE_STATUS  0x48    /* Mode and status of ECC (32b)
  35                                          *
  36                                          * 31:16 reserved
  37                                          * 15:14 SERR enabled: x1=ue 1x=ce
  38                                          * 13    reserved
  39                                          * 12    diag: disabled, enabled
  40                                          * 11:10 mode: dis, EC, ECC, ECC+scrub
  41                                          *  9:8  status: x1=ue 1x=ce
  42                                          *  7:4  UE cs row
  43                                          *  3:0  CE cs row
  44                                          */
  45
  46 #define AMD76X_DRAM_MODE_STATUS 0x58    /* DRAM Mode and status (32b)
  47                                          *
  48                                          * 31:26 clock disable 5 - 0
  49                                          * 25    SDRAM init
  50                                          * 24    reserved
  51                                          * 23    mode register service
  52                                          * 22:21 suspend to RAM
  53                                          * 20    burst refresh enable
  54                                          * 19    refresh disable
  55                                          * 18    reserved
  56                                          * 17:16 cycles-per-refresh
  57                                          * 15:8  reserved
  58                                          *  7:0  x4 mode enable 7 - 0
  59                                          */
  60
  61 #define AMD76X_MEM_BASE_ADDR    0xC0    /* Memory base address (8 x 32b)
  62                                          *
  63                                          * 31:23 chip-select base
  64                                          * 22:16 reserved
  65                                          * 15:7  chip-select mask
  66                                          *  6:3  reserved
  67                                          *  2:1  address mode
  68                                          *  0    chip-select enable
  69                                          */
  70
  71 struct amd76x_error_info {
  72         u32 ecc_mode_status;
  73 };
  74
  75 enum amd76x_chips {
  76         AMD761 = 0,
  77         AMD762
  78 };
  79
  80 struct amd76x_dev_info {
  81         const char *ctl_name;
  82 };
  83
  84 static const struct amd76x_dev_info amd76x_devs[] = {
  85         [AMD761] = {
  86                 .ctl_name = "AMD761"
  87         },
  88         [AMD762] = {
  89                 .ctl_name = "AMD762"
  90         },
  91 };
  92
  93 /**
  94  *      amd76x_get_error_info   -       fetch error information
  95  *      @mci: Memory controller
  96  *      @info: Info to fill in
  97  *
  98  *      Fetch and store the AMD76x ECC status. Clear pending status
  99  *      on the chip so that further errors will be reported
 100  */
 101 static void amd76x_get_error_info(struct mem_ctl_info *mci,
 102                 struct amd76x_error_info *info)
 103 {
 104         pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
 105                                 &info->ecc_mode_status);
 106
 107         if (info->ecc_mode_status & BIT(8))
 108                 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
 109                                 (u32) BIT(8), (u32) BIT(8));
 110
 111         if (info->ecc_mode_status & BIT(9))
 112                 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
 113                                 (u32) BIT(9), (u32) BIT(9));
 114 }
 115
 116 /**
 117  *      amd76x_process_error_info       -       Error check
 118  *      @mci: Memory controller
 119  *      @info: Previously fetched information from chip
 120  *      @handle_errors: 1 if we should do recovery
 121  *
 122  *      Process the chip state and decide if an error has occurred.
 123  *      A return of 1 indicates an error. Also if handle_errors is true
 124  *      then attempt to handle and clean up after the error
 125  */
 126 static int amd76x_process_error_info(struct mem_ctl_info *mci,
 127                 struct amd76x_error_info *info, int handle_errors)
 128 {
 129         int error_found;
 130         u32 row;
 131
 132         error_found = 0;
 133
 134         /*
 135          *      Check for an uncorrectable error
 136          */
 137         if (info->ecc_mode_status & BIT(8)) {
 138                 error_found = 1;
 139
 140                 if (handle_errors) {
 141                         row = (info->ecc_mode_status >> 4) & 0xf;
 142                         edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
 143                                 row, mci->ctl_name);
 144                 }
 145         }
 146
 147         /*
 148          *      Check for a correctable error
 149          */
 150         if (info->ecc_mode_status & BIT(9)) {
 151                 error_found = 1;
 152
 153                 if (handle_errors) {
 154                         row = info->ecc_mode_status & 0xf;
 155                         edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
 156                                 0, row, 0, mci->ctl_name);
 157                 }
 158         }
 159
 160         return error_found;
 161 }
 162
 163 /**
 164  *      amd76x_check    -       Poll the controller
 165  *      @mci: Memory controller
 166  *
 167  *      Called by the poll handlers this function reads the status
 168  *      from the controller and checks for errors.
 169  */
 170 static void amd76x_check(struct mem_ctl_info *mci)
 171 {
 172         struct amd76x_error_info info;
 173         debugf3("%s()\n", __func__);
 174         amd76x_get_error_info(mci, &info);
 175         amd76x_process_error_info(mci, &info, 1);
 176 }
 177
 178 /**
 179  *      amd76x_probe1   -       Perform set up for detected device
 180  *      @pdev; PCI device detected
 181  *      @dev_idx: Device type index
 182  *
 183  *      We have found an AMD76x and now need to set up the memory
 184  *      controller status reporting. We configure and set up the
 185  *      memory controller reporting and claim the device.
 186  */
 187 static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
 188 {
 189         int rc = -ENODEV;
 190         int index;
 191         struct mem_ctl_info *mci = NULL;
 192         enum edac_type ems_modes[] = {
 193                 EDAC_NONE,
 194                 EDAC_EC,
 195                 EDAC_SECDED,
 196                 EDAC_SECDED
 197         };
 198         u32 ems;
 199         u32 ems_mode;
 200         struct amd76x_error_info discard;
 201
 202         debugf0("%s()\n", __func__);
 203         pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
 204         ems_mode = (ems >> 10) & 0x3;
 205         mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
 206
 207         if (mci == NULL) {
 208                 rc = -ENOMEM;
 209                 goto fail;
 210         }
 211
 212         debugf0("%s(): mci = %p\n", __func__, mci);
 213         mci->pdev = pdev;
 214         mci->mtype_cap = MEM_FLAG_RDDR;
 215         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 216         mci->edac_cap = ems_mode ?
 217                         (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
 218         mci->mod_name = EDAC_MOD_STR;
 219         mci->mod_ver = "$Revision: 1.4.2.5 $";
 220         mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
 221         mci->edac_check = amd76x_check;
 222         mci->ctl_page_to_phys = NULL;
 223
 224         for (index = 0; index < mci->nr_csrows; index++) {
 225                 struct csrow_info *csrow = &mci->csrows[index];
 226                 u32 mba;
 227                 u32 mba_base;
 228                 u32 mba_mask;
 229                 u32 dms;
 230
 231                 /* find the DRAM Chip Select Base address and mask */
 232                 pci_read_config_dword(mci->pdev,
 233                                 AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
 234
 235                 if (!(mba & BIT(0)))
 236                         continue;
 237
 238                 mba_base = mba & 0xff800000UL;
 239                 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
 240                 pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
 241                                 &dms);
 242                 csrow->first_page = mba_base >> PAGE_SHIFT;
 243                 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
 244                 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
 245                 csrow->page_mask = mba_mask >> PAGE_SHIFT;
 246                 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
 247                 csrow->mtype = MEM_RDDR;
 248                 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
 249                 csrow->edac_mode = ems_modes[ems_mode];
 250         }
 251
 252         amd76x_get_error_info(mci, &discard);  /* clear counters */
 253
 254         if (edac_mc_add_mc(mci)) {
 255                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 256                 goto fail;
 257         }
 258
 259         /* get this far and it's successful */
 260         debugf3("%s(): success\n", __func__);
 261         return 0;
 262
 263 fail:
 264         if (mci != NULL)
 265                 edac_mc_free(mci);
 266         return rc;
 267 }
 268
 269 /* returns count (>= 0), or negative on error */
 270 static int __devinit amd76x_init_one(struct pci_dev *pdev,
 271                 const struct pci_device_id *ent)
 272 {
 273         debugf0("%s()\n", __func__);
 274
 275         /* don't need to call pci_device_enable() */
 276         return amd76x_probe1(pdev, ent->driver_data);
 277 }
 278
 279 /**
 280  *      amd76x_remove_one       -       driver shutdown
 281  *      @pdev: PCI device being handed back
 282  *
 283  *      Called when the driver is unloaded. Find the matching mci
 284  *      structure for the device then delete the mci and free the
 285  *      resources.
 286  */
 287 static void __devexit amd76x_remove_one(struct pci_dev *pdev)
 288 {
 289         struct mem_ctl_info *mci;
 290
 291         debugf0("%s()\n", __func__);
 292
 293         if ((mci = edac_mc_del_mc(pdev)) == NULL)
 294                 return;
 295
 296         edac_mc_free(mci);
 297 }
 298
 299 static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
 300         {
 301                 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 302                 AMD762
 303         },
 304         {
 305                 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 306                 AMD761
 307         },
 308         {
 309                 0,
 310         }       /* 0 terminated list. */
 311 };
 312
 313 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
 314
 315 static struct pci_driver amd76x_driver = {
 316         .name = EDAC_MOD_STR,
 317         .probe = amd76x_init_one,
 318         .remove = __devexit_p(amd76x_remove_one),
 319         .id_table = amd76x_pci_tbl,
 320 };
 321
 322 static int __init amd76x_init(void)
 323 {
 324         return pci_register_driver(&amd76x_driver);
 325 }
 326
 327 static void __exit amd76x_exit(void)
 328 {
 329         pci_unregister_driver(&amd76x_driver);
 330 }
 331
 332 module_init(amd76x_init);
 333 module_exit(amd76x_exit);
 334
 335 MODULE_LICENSE("GPL");
 336 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
 337 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");