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Remove obsolete #include <linux/config.h>
[linux-2.6/verdex.git] / drivers / edac / e752x_edac.c
bloba52573b3280ce321372941a127eabcea2843b4ad
1 /*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/pci_ids.h>
24 #include <linux/slab.h>
25 #include "edac_mc.h"
26
27 static int force_function_unhide;
28
29 #define e752x_printk(level, fmt, arg...) \
30 edac_printk(level, "e752x", fmt, ##arg)
31
32 #define e752x_mc_printk(mci, level, fmt, arg...) \
33 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
34
35 #ifndef PCI_DEVICE_ID_INTEL_7520_0
36 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
37 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
38
39 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
40 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
41 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
42
43 #ifndef PCI_DEVICE_ID_INTEL_7525_0
44 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
45 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
46
47 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
48 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
49 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
50
51 #ifndef PCI_DEVICE_ID_INTEL_7320_0
52 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
53 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
54
55 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
56 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
57 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
58
59 #define E752X_NR_CSROWS 8 /* number of csrows */
60
61 /* E752X register addresses - device 0 function 0 */
62 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
63 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
64 /*
65 * 31:30 Device width row 7
66 * 01=x8 10=x4 11=x8 DDR2
67 * 27:26 Device width row 6
68 * 23:22 Device width row 5
69 * 19:20 Device width row 4
70 * 15:14 Device width row 3
71 * 11:10 Device width row 2
72 * 7:6 Device width row 1
73 * 3:2 Device width row 0
74 */
75 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
76 /* FIXME:IS THIS RIGHT? */
77 /*
78 * 22 Number channels 0=1,1=2
79 * 19:18 DRB Granularity 32/64MB
80 */
81 #define E752X_DRM 0x80 /* Dimm mapping register */
82 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
83 /*
84 * 14:12 1 single A, 2 single B, 3 dual
85 */
86 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
87 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
88 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
89 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
90
91 /* E752X register addresses - device 0 function 1 */
92 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
93 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
94 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
95 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
96 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
97 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
98 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
99 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
100 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
101 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
102 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
103 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
104 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
105 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
106 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
107 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
108 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
109 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
110 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
111 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
112 /* error address register (32b) */
113 /*
114 * 31 Reserved
115 * 30:2 CE address (64 byte block 34:6)
116 * 1 Reserved
117 * 0 HiLoCS
118 */
119 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
120 /* error address register (32b) */
121 /*
122 * 31 Reserved
123 * 30:2 CE address (64 byte block 34:6)
124 * 1 Reserved
125 * 0 HiLoCS
126 */
127 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
128 /* error address register (32b) */
129 /*
130 * 31 Reserved
131 * 30:2 CE address (64 byte block 34:6)
132 * 1 Reserved
133 * 0 HiLoCS
134 */
135 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
136 /* error address register (32b) */
137 /*
138 * 31 Reserved
139 * 30:2 CE address (64 byte block 34:6)
140 * 1 Reserved
141 * 0 HiLoCS
142 */
143 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
144 /* error syndrome register (16b) */
145 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
146 /* error syndrome register (16b) */
147 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
148
149 /* ICH5R register addresses - device 30 function 0 */
150 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
151 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
152 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
153
154 enum e752x_chips {
155 E7520 = 0,
156 E7525 = 1,
157 E7320 = 2
158 };
159
160 struct e752x_pvt {
161 struct pci_dev *bridge_ck;
162 struct pci_dev *dev_d0f0;
163 struct pci_dev *dev_d0f1;
164 u32 tolm;
165 u32 remapbase;
166 u32 remaplimit;
167 int mc_symmetric;
168 u8 map[8];
169 int map_type;
170 const struct e752x_dev_info *dev_info;
171 };
172
173 struct e752x_dev_info {
174 u16 err_dev;
175 u16 ctl_dev;
176 const char *ctl_name;
177 };
178
179 struct e752x_error_info {
180 u32 ferr_global;
181 u32 nerr_global;
182 u8 hi_ferr;
183 u8 hi_nerr;
184 u16 sysbus_ferr;
185 u16 sysbus_nerr;
186 u8 buf_ferr;
187 u8 buf_nerr;
188 u16 dram_ferr;
189 u16 dram_nerr;
190 u32 dram_sec1_add;
191 u32 dram_sec2_add;
192 u16 dram_sec1_syndrome;
193 u16 dram_sec2_syndrome;
194 u32 dram_ded_add;
195 u32 dram_scrb_add;
196 u32 dram_retr_add;
197 };
198
199 static const struct e752x_dev_info e752x_devs[] = {
200 [E7520] = {
201 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
202 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
203 .ctl_name = "E7520"
204 },
205 [E7525] = {
206 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
207 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
208 .ctl_name = "E7525"
209 },
210 [E7320] = {
211 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
212 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
213 .ctl_name = "E7320"
214 },
215 };
216
217 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
218 unsigned long page)
219 {
220 u32 remap;
221 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
222
223 debugf3("%s()\n", __func__);
224
225 if (page < pvt->tolm)
226 return page;
227
228 if ((page >= 0x100000) && (page < pvt->remapbase))
229 return page;
230
231 remap = (page - pvt->tolm) + pvt->remapbase;
232
233 if (remap < pvt->remaplimit)
234 return remap;
235
236 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
237 return pvt->tolm - 1;
238 }
239
240 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
241 u32 sec1_add, u16 sec1_syndrome)
242 {
243 u32 page;
244 int row;
245 int channel;
246 int i;
247 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
248
249 debugf3("%s()\n", __func__);
250
251 /* convert the addr to 4k page */
252 page = sec1_add >> (PAGE_SHIFT - 4);
253
254 /* FIXME - check for -1 */
255 if (pvt->mc_symmetric) {
256 /* chip select are bits 14 & 13 */
257 row = ((page >> 1) & 3);
258 e752x_printk(KERN_WARNING,
259 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
260 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
261 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
262
263 /* test for channel remapping */
264 for (i = 0; i < 8; i++) {
265 if (pvt->map[i] == row)
266 break;
267 }
268
269 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
270
271 if (i < 8)
272 row = i;
273 else
274 e752x_mc_printk(mci, KERN_WARNING,
275 "row %d not found in remap table\n", row);
276 } else
277 row = edac_mc_find_csrow_by_page(mci, page);
278
279 /* 0 = channel A, 1 = channel B */
280 channel = !(error_one & 1);
281
282 if (!pvt->map_type)
283 row = 7 - row;
284
285 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
286 "e752x CE");
287 }
288
289 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
290 u32 sec1_add, u16 sec1_syndrome, int *error_found,
291 int handle_error)
292 {
293 *error_found = 1;
294
295 if (handle_error)
296 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
297 }
298
299 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
300 u32 ded_add, u32 scrb_add)
301 {
302 u32 error_2b, block_page;
303 int row;
304 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
305
306 debugf3("%s()\n", __func__);
307
308 if (error_one & 0x0202) {
309 error_2b = ded_add;
310
311 /* convert to 4k address */
312 block_page = error_2b >> (PAGE_SHIFT - 4);
313
314 row = pvt->mc_symmetric ?
315 /* chip select are bits 14 & 13 */
316 ((block_page >> 1) & 3) :
317 edac_mc_find_csrow_by_page(mci, block_page);
318
319 edac_mc_handle_ue(mci, block_page, 0, row,
320 "e752x UE from Read");
321 }
322 if (error_one & 0x0404) {
323 error_2b = scrb_add;
324
325 /* convert to 4k address */
326 block_page = error_2b >> (PAGE_SHIFT - 4);
327
328 row = pvt->mc_symmetric ?
329 /* chip select are bits 14 & 13 */
330 ((block_page >> 1) & 3) :
331 edac_mc_find_csrow_by_page(mci, block_page);
332
333 edac_mc_handle_ue(mci, block_page, 0, row,
334 "e752x UE from Scruber");
335 }
336 }
337
338 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
339 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
340 {
341 *error_found = 1;
342
343 if (handle_error)
344 do_process_ue(mci, error_one, ded_add, scrb_add);
345 }
346
347 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
348 int *error_found, int handle_error)
349 {
350 *error_found = 1;
351
352 if (!handle_error)
353 return;
354
355 debugf3("%s()\n", __func__);
356 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
357 }
358
359 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
360 u32 retry_add)
361 {
362 u32 error_1b, page;
363 int row;
364 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
365
366 error_1b = retry_add;
367 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
368 row = pvt->mc_symmetric ?
369 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
370 edac_mc_find_csrow_by_page(mci, page);
371 e752x_mc_printk(mci, KERN_WARNING,
372 "CE page 0x%lx, row %d : Memory read retry\n",
373 (long unsigned int) page, row);
374 }
375
376 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
377 u32 retry_add, int *error_found, int handle_error)
378 {
379 *error_found = 1;
380
381 if (handle_error)
382 do_process_ded_retry(mci, error, retry_add);
383 }
384
385 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
386 int *error_found, int handle_error)
387 {
388 *error_found = 1;
389
390 if (handle_error)
391 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
392 }
393
394 static char *global_message[11] = {
395 "PCI Express C1", "PCI Express C", "PCI Express B1",
396 "PCI Express B", "PCI Express A1", "PCI Express A",
397 "DMA Controler", "HUB Interface", "System Bus",
398 "DRAM Controler", "Internal Buffer"
399 };
400
401 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
402
403 static void do_global_error(int fatal, u32 errors)
404 {
405 int i;
406
407 for (i = 0; i < 11; i++) {
408 if (errors & (1 << i))
409 e752x_printk(KERN_WARNING, "%sError %s\n",
410 fatal_message[fatal], global_message[i]);
411 }
412 }
413
414 static inline void global_error(int fatal, u32 errors, int *error_found,
415 int handle_error)
416 {
417 *error_found = 1;
418
419 if (handle_error)
420 do_global_error(fatal, errors);
421 }
422
423 static char *hub_message[7] = {
424 "HI Address or Command Parity", "HI Illegal Access",
425 "HI Internal Parity", "Out of Range Access",
426 "HI Data Parity", "Enhanced Config Access",
427 "Hub Interface Target Abort"
428 };
429
430 static void do_hub_error(int fatal, u8 errors)
431 {
432 int i;
433
434 for (i = 0; i < 7; i++) {
435 if (errors & (1 << i))
436 e752x_printk(KERN_WARNING, "%sError %s\n",
437 fatal_message[fatal], hub_message[i]);
438 }
439 }
440
441 static inline void hub_error(int fatal, u8 errors, int *error_found,
442 int handle_error)
443 {
444 *error_found = 1;
445
446 if (handle_error)
447 do_hub_error(fatal, errors);
448 }
449
450 static char *membuf_message[4] = {
451 "Internal PMWB to DRAM parity",
452 "Internal PMWB to System Bus Parity",
453 "Internal System Bus or IO to PMWB Parity",
454 "Internal DRAM to PMWB Parity"
455 };
456
457 static void do_membuf_error(u8 errors)
458 {
459 int i;
460
461 for (i = 0; i < 4; i++) {
462 if (errors & (1 << i))
463 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
464 membuf_message[i]);
465 }
466 }
467
468 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
469 {
470 *error_found = 1;
471
472 if (handle_error)
473 do_membuf_error(errors);
474 }
475
476 static char *sysbus_message[10] = {
477 "Addr or Request Parity",
478 "Data Strobe Glitch",
479 "Addr Strobe Glitch",
480 "Data Parity",
481 "Addr Above TOM",
482 "Non DRAM Lock Error",
483 "MCERR", "BINIT",
484 "Memory Parity",
485 "IO Subsystem Parity"
486 };
487
488 static void do_sysbus_error(int fatal, u32 errors)
489 {
490 int i;
491
492 for (i = 0; i < 10; i++) {
493 if (errors & (1 << i))
494 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
495 fatal_message[fatal], sysbus_message[i]);
496 }
497 }
498
499 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
500 int handle_error)
501 {
502 *error_found = 1;
503
504 if (handle_error)
505 do_sysbus_error(fatal, errors);
506 }
507
508 static void e752x_check_hub_interface(struct e752x_error_info *info,
509 int *error_found, int handle_error)
510 {
511 u8 stat8;
512
513 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
514
515 stat8 = info->hi_ferr;
516
517 if(stat8 & 0x7f) { /* Error, so process */
518 stat8 &= 0x7f;
519
520 if(stat8 & 0x2b)
521 hub_error(1, stat8 & 0x2b, error_found, handle_error);
522
523 if(stat8 & 0x54)
524 hub_error(0, stat8 & 0x54, error_found, handle_error);
525 }
526
527 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
528
529 stat8 = info->hi_nerr;
530
531 if(stat8 & 0x7f) { /* Error, so process */
532 stat8 &= 0x7f;
533
534 if (stat8 & 0x2b)
535 hub_error(1, stat8 & 0x2b, error_found, handle_error);
536
537 if(stat8 & 0x54)
538 hub_error(0, stat8 & 0x54, error_found, handle_error);
539 }
540 }
541
542 static void e752x_check_sysbus(struct e752x_error_info *info,
543 int *error_found, int handle_error)
544 {
545 u32 stat32, error32;
546
547 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
548 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
549
550 if (stat32 == 0)
551 return; /* no errors */
552
553 error32 = (stat32 >> 16) & 0x3ff;
554 stat32 = stat32 & 0x3ff;
555
556 if(stat32 & 0x083)
557 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
558
559 if(stat32 & 0x37c)
560 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
561
562 if(error32 & 0x083)
563 sysbus_error(1, error32 & 0x083, error_found, handle_error);
564
565 if(error32 & 0x37c)
566 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
567 }
568
569 static void e752x_check_membuf (struct e752x_error_info *info,
570 int *error_found, int handle_error)
571 {
572 u8 stat8;
573
574 stat8 = info->buf_ferr;
575
576 if (stat8 & 0x0f) { /* Error, so process */
577 stat8 &= 0x0f;
578 membuf_error(stat8, error_found, handle_error);
579 }
580
581 stat8 = info->buf_nerr;
582
583 if (stat8 & 0x0f) { /* Error, so process */
584 stat8 &= 0x0f;
585 membuf_error(stat8, error_found, handle_error);
586 }
587 }
588
589 static void e752x_check_dram (struct mem_ctl_info *mci,
590 struct e752x_error_info *info, int *error_found,
591 int handle_error)
592 {
593 u16 error_one, error_next;
594
595 error_one = info->dram_ferr;
596 error_next = info->dram_nerr;
597
598 /* decode and report errors */
599 if(error_one & 0x0101) /* check first error correctable */
600 process_ce(mci, error_one, info->dram_sec1_add,
601 info->dram_sec1_syndrome, error_found,
602 handle_error);
603
604 if(error_next & 0x0101) /* check next error correctable */
605 process_ce(mci, error_next, info->dram_sec2_add,
606 info->dram_sec2_syndrome, error_found,
607 handle_error);
608
609 if(error_one & 0x4040)
610 process_ue_no_info_wr(mci, error_found, handle_error);
611
612 if(error_next & 0x4040)
613 process_ue_no_info_wr(mci, error_found, handle_error);
614
615 if(error_one & 0x2020)
616 process_ded_retry(mci, error_one, info->dram_retr_add,
617 error_found, handle_error);
618
619 if(error_next & 0x2020)
620 process_ded_retry(mci, error_next, info->dram_retr_add,
621 error_found, handle_error);
622
623 if(error_one & 0x0808)
624 process_threshold_ce(mci, error_one, error_found,
625 handle_error);
626
627 if(error_next & 0x0808)
628 process_threshold_ce(mci, error_next, error_found,
629 handle_error);
630
631 if(error_one & 0x0606)
632 process_ue(mci, error_one, info->dram_ded_add,
633 info->dram_scrb_add, error_found, handle_error);
634
635 if(error_next & 0x0606)
636 process_ue(mci, error_next, info->dram_ded_add,
637 info->dram_scrb_add, error_found, handle_error);
638 }
639
640 static void e752x_get_error_info (struct mem_ctl_info *mci,
641 struct e752x_error_info *info)
642 {
643 struct pci_dev *dev;
644 struct e752x_pvt *pvt;
645
646 memset(info, 0, sizeof(*info));
647 pvt = (struct e752x_pvt *) mci->pvt_info;
648 dev = pvt->dev_d0f1;
649 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
650
651 if (info->ferr_global) {
652 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
653 pci_read_config_word(dev, E752X_SYSBUS_FERR,
654 &info->sysbus_ferr);
655 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
656 pci_read_config_word(dev, E752X_DRAM_FERR,
657 &info->dram_ferr);
658 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
659 &info->dram_sec1_add);
660 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
661 &info->dram_sec1_syndrome);
662 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
663 &info->dram_ded_add);
664 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
665 &info->dram_scrb_add);
666 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
667 &info->dram_retr_add);
668
669 if (info->hi_ferr & 0x7f)
670 pci_write_config_byte(dev, E752X_HI_FERR,
671 info->hi_ferr);
672
673 if (info->sysbus_ferr)
674 pci_write_config_word(dev, E752X_SYSBUS_FERR,
675 info->sysbus_ferr);
676
677 if (info->buf_ferr & 0x0f)
678 pci_write_config_byte(dev, E752X_BUF_FERR,
679 info->buf_ferr);
680
681 if (info->dram_ferr)
682 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
683 info->dram_ferr, info->dram_ferr);
684
685 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
686 info->ferr_global);
687 }
688
689 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
690
691 if (info->nerr_global) {
692 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
693 pci_read_config_word(dev, E752X_SYSBUS_NERR,
694 &info->sysbus_nerr);
695 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
696 pci_read_config_word(dev, E752X_DRAM_NERR,
697 &info->dram_nerr);
698 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
699 &info->dram_sec2_add);
700 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
701 &info->dram_sec2_syndrome);
702
703 if (info->hi_nerr & 0x7f)
704 pci_write_config_byte(dev, E752X_HI_NERR,
705 info->hi_nerr);
706
707 if (info->sysbus_nerr)
708 pci_write_config_word(dev, E752X_SYSBUS_NERR,
709 info->sysbus_nerr);
710
711 if (info->buf_nerr & 0x0f)
712 pci_write_config_byte(dev, E752X_BUF_NERR,
713 info->buf_nerr);
714
715 if (info->dram_nerr)
716 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
717 info->dram_nerr, info->dram_nerr);
718
719 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
720 info->nerr_global);
721 }
722 }
723
724 static int e752x_process_error_info (struct mem_ctl_info *mci,
725 struct e752x_error_info *info, int handle_errors)
726 {
727 u32 error32, stat32;
728 int error_found;
729
730 error_found = 0;
731 error32 = (info->ferr_global >> 18) & 0x3ff;
732 stat32 = (info->ferr_global >> 4) & 0x7ff;
733
734 if (error32)
735 global_error(1, error32, &error_found, handle_errors);
736
737 if (stat32)
738 global_error(0, stat32, &error_found, handle_errors);
739
740 error32 = (info->nerr_global >> 18) & 0x3ff;
741 stat32 = (info->nerr_global >> 4) & 0x7ff;
742
743 if (error32)
744 global_error(1, error32, &error_found, handle_errors);
745
746 if (stat32)
747 global_error(0, stat32, &error_found, handle_errors);
748
749 e752x_check_hub_interface(info, &error_found, handle_errors);
750 e752x_check_sysbus(info, &error_found, handle_errors);
751 e752x_check_membuf(info, &error_found, handle_errors);
752 e752x_check_dram(mci, info, &error_found, handle_errors);
753 return error_found;
754 }
755
756 static void e752x_check(struct mem_ctl_info *mci)
757 {
758 struct e752x_error_info info;
759
760 debugf3("%s()\n", __func__);
761 e752x_get_error_info(mci, &info);
762 e752x_process_error_info(mci, &info, 1);
763 }
764
765 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
766 {
767 int rc = -ENODEV;
768 int index;
769 u16 pci_data;
770 u8 stat8;
771 struct mem_ctl_info *mci = NULL;
772 struct e752x_pvt *pvt = NULL;
773 u16 ddrcsr;
774 u32 drc;
775 int drc_chan; /* Number of channels 0=1chan,1=2chan */
776 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
777 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
778 u32 dra;
779 unsigned long last_cumul_size;
780 struct pci_dev *dev = NULL;
781 struct e752x_error_info discard;
782
783 debugf0("%s(): mci\n", __func__);
784 debugf0("Starting Probe1\n");
785
786 /* check to see if device 0 function 1 is enabled; if it isn't, we
787 * assume the BIOS has reserved it for a reason and is expecting
788 * exclusive access, we take care not to violate that assumption and
789 * fail the probe. */
790 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
791 if (!force_function_unhide && !(stat8 & (1 << 5))) {
792 printk(KERN_INFO "Contact your BIOS vendor to see if the "
793 "E752x error registers can be safely un-hidden\n");
794 goto fail;
795 }
796 stat8 |= (1 << 5);
797 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
798
799 /* need to find out the number of channels */
800 pci_read_config_dword(pdev, E752X_DRC, &drc);
801 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
802 /* FIXME: should check >>12 or 0xf, true for all? */
803 /* Dual channel = 1, Single channel = 0 */
804 drc_chan = (((ddrcsr >> 12) & 3) == 3);
805 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
806 drc_ddim = (drc >> 20) & 0x3;
807
808 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
809
810 if (mci == NULL) {
811 rc = -ENOMEM;
812 goto fail;
813 }
814
815 debugf3("%s(): init mci\n", __func__);
816 mci->mtype_cap = MEM_FLAG_RDDR;
817 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
818 EDAC_FLAG_S4ECD4ED;
819 /* FIXME - what if different memory types are in different csrows? */
820 mci->mod_name = EDAC_MOD_STR;
821 mci->mod_ver = "$Revision: 1.5.2.11 $";
822 mci->pdev = pdev;
823
824 debugf3("%s(): init pvt\n", __func__);
825 pvt = (struct e752x_pvt *) mci->pvt_info;
826 pvt->dev_info = &e752x_devs[dev_idx];
827 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
828 pvt->dev_info->err_dev,
829 pvt->bridge_ck);
830
831 if (pvt->bridge_ck == NULL)
832 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
833 PCI_DEVFN(0, 1));
834
835 if (pvt->bridge_ck == NULL) {
836 e752x_printk(KERN_ERR, "error reporting device not found:"
837 "vendor %x device 0x%x (broken BIOS?)\n",
838 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
839 goto fail;
840 }
841
842 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
843 debugf3("%s(): more mci init\n", __func__);
844 mci->ctl_name = pvt->dev_info->ctl_name;
845 mci->edac_check = e752x_check;
846 mci->ctl_page_to_phys = ctl_page_to_phys;
847
848 /* find out the device types */
849 pci_read_config_dword(pdev, E752X_DRA, &dra);
850
851 /*
852 * The dram row boundary (DRB) reg values are boundary address for
853 * each DRAM row with a granularity of 64 or 128MB (single/dual
854 * channel operation). DRB regs are cumulative; therefore DRB7 will
855 * contain the total memory contained in all eight rows.
856 */
857 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
858 u8 value;
859 u32 cumul_size;
860
861 /* mem_dev 0=x8, 1=x4 */
862 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
863 struct csrow_info *csrow = &mci->csrows[index];
864
865 mem_dev = (mem_dev == 2);
866 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
867 /* convert a 128 or 64 MiB DRB to a page size. */
868 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
869 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
870 cumul_size);
871
872 if (cumul_size == last_cumul_size)
873 continue; /* not populated */
874
875 csrow->first_page = last_cumul_size;
876 csrow->last_page = cumul_size - 1;
877 csrow->nr_pages = cumul_size - last_cumul_size;
878 last_cumul_size = cumul_size;
879 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
880 csrow->mtype = MEM_RDDR; /* only one type supported */
881 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
882
883 /*
884 * if single channel or x8 devices then SECDED
885 * if dual channel and x4 then S4ECD4ED
886 */
887 if (drc_ddim) {
888 if (drc_chan && mem_dev) {
889 csrow->edac_mode = EDAC_S4ECD4ED;
890 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
891 } else {
892 csrow->edac_mode = EDAC_SECDED;
893 mci->edac_cap |= EDAC_FLAG_SECDED;
894 }
895 } else
896 csrow->edac_mode = EDAC_NONE;
897 }
898
899 /* Fill in the memory map table */
900 {
901 u8 value;
902 u8 last = 0;
903 u8 row = 0;
904
905 for (index = 0; index < 8; index += 2) {
906 pci_read_config_byte(mci->pdev, E752X_DRB + index,
907 &value);
908
909 /* test if there is a dimm in this slot */
910 if (value == last) {
911 /* no dimm in the slot, so flag it as empty */
912 pvt->map[index] = 0xff;
913 pvt->map[index + 1] = 0xff;
914 } else { /* there is a dimm in the slot */
915 pvt->map[index] = row;
916 row++;
917 last = value;
918 /* test the next value to see if the dimm is
919 double sided */
920 pci_read_config_byte(mci->pdev,
921 E752X_DRB + index + 1,
922 &value);
923 pvt->map[index + 1] = (value == last) ?
924 0xff : /* the dimm is single sided,
925 * so flag as empty
926 */
927 row; /* this is a double sided dimm
928 * to save the next row #
929 */
930 row++;
931 last = value;
932 }
933 }
934 }
935
936 /* set the map type. 1 = normal, 0 = reversed */
937 pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
938 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
939
940 mci->edac_cap |= EDAC_FLAG_NONE;
941 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
942
943 /* load the top of low memory, remap base, and remap limit vars */
944 pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
945 pvt->tolm = ((u32) pci_data) << 4;
946 pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
947 pvt->remapbase = ((u32) pci_data) << 14;
948 pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
949 pvt->remaplimit = ((u32) pci_data) << 14;
950 e752x_printk(KERN_INFO,
951 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
952 pvt->remapbase, pvt->remaplimit);
953
954 if (edac_mc_add_mc(mci)) {
955 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
956 goto fail;
957 }
958
959 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
960 NULL);
961 pvt->dev_d0f0 = dev;
962 /* find the error reporting device and clear errors */
963 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
964 /* Turn off error disable & SMI in case the BIOS turned it on */
965 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
966 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
967 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
968 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
969 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
970 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
971 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
972 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
973
974 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
975
976 /* get this far and it's successful */
977 debugf3("%s(): success\n", __func__);
978 return 0;
979
980 fail:
981 if (mci) {
982 if (pvt->dev_d0f0)
983 pci_dev_put(pvt->dev_d0f0);
984
985 if (pvt->dev_d0f1)
986 pci_dev_put(pvt->dev_d0f1);
987
988 if (pvt->bridge_ck)
989 pci_dev_put(pvt->bridge_ck);
990
991 edac_mc_free(mci);
992 }
993
994 return rc;
995 }
996
997 /* returns count (>= 0), or negative on error */
998 static int __devinit e752x_init_one(struct pci_dev *pdev,
999 const struct pci_device_id *ent)
1000 {
1001 debugf0("%s()\n", __func__);
1002
1003 /* wake up and enable device */
1004 if(pci_enable_device(pdev) < 0)
1005 return -EIO;
1006
1007 return e752x_probe1(pdev, ent->driver_data);
1008 }
1009
1010 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1011 {
1012 struct mem_ctl_info *mci;
1013 struct e752x_pvt *pvt;
1014
1015 debugf0("%s()\n", __func__);
1016
1017 if ((mci = edac_mc_del_mc(pdev)) == NULL)
1018 return;
1019
1020 pvt = (struct e752x_pvt *) mci->pvt_info;
1021 pci_dev_put(pvt->dev_d0f0);
1022 pci_dev_put(pvt->dev_d0f1);
1023 pci_dev_put(pvt->bridge_ck);
1024 edac_mc_free(mci);
1025 }
1026
1027 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1028 {
1029 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1030 E7520
1031 },
1032 {
1033 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1034 E7525
1035 },
1036 {
1037 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1038 E7320
1039 },
1040 {
1041 0,
1042 } /* 0 terminated list. */
1043 };
1044
1045 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1046
1047 static struct pci_driver e752x_driver = {
1048 .name = EDAC_MOD_STR,
1049 .probe = e752x_init_one,
1050 .remove = __devexit_p(e752x_remove_one),
1051 .id_table = e752x_pci_tbl,
1052 };
1053
1054 static int __init e752x_init(void)
1055 {
1056 int pci_rc;
1057
1058 debugf3("%s()\n", __func__);
1059 pci_rc = pci_register_driver(&e752x_driver);
1060 return (pci_rc < 0) ? pci_rc : 0;
1061 }
1062
1063 static void __exit e752x_exit(void)
1064 {
1065 debugf3("%s()\n", __func__);
1066 pci_unregister_driver(&e752x_driver);
1067 }
1068
1069 module_init(e752x_init);
1070 module_exit(e752x_exit);
1071
1072 MODULE_LICENSE("GPL");
1073 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1074 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1075
1076 module_param(force_function_unhide, int, 0444);
1077 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1078 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1079
Verdex Pro support