arch/arm/mach-pxa/cm-x270-pci.c

   1 /*
   2  * linux/arch/arm/mach-pxa/cm-x270-pci.c
   3  *
   4  * PCI bios-type initialisation for PCI machines
   5  *
   6  * Bits taken from various places.
   7  *
   8  * Copyright (C) 2007 Compulab, Ltd.
   9  * Mike Rapoport <mike@compulab.co.il>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22
  23 #include <asm/mach/pci.h>
  24 #include <asm/arch/cm-x270.h>
  25 #include <asm/arch/pxa-regs.h>
  26 #include <asm/mach-types.h>
  27
  28 #include <asm/hardware/it8152.h>
  29
  30 unsigned long it8152_base_address = CMX270_IT8152_VIRT;
  31
  32 /*
  33  * Only first 64MB of memory can be accessed via PCI.
  34  * We use GFP_DMA to allocate safe buffers to do map/unmap.
  35  * This is really ugly and we need a better way of specifying
  36  * DMA-capable regions of memory.
  37  */
  38 void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
  39         unsigned long *zhole_size)
  40 {
  41         unsigned int sz = SZ_64M >> PAGE_SHIFT;
  42
  43         printk(KERN_INFO "Adjusting zones for CM-x270\n");
  44
  45         /*
  46          * Only adjust if > 64M on current system
  47          */
  48         if (node || (zone_size[0] <= sz))
  49                 return;
  50
  51         zone_size[1] = zone_size[0] - sz;
  52         zone_size[0] = sz;
  53         zhole_size[1] = zhole_size[0];
  54         zhole_size[0] = 0;
  55 }
  56
  57 static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
  58 {
  59         /* clear our parent irq */
  60         GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
  61
  62         it8152_irq_demux(irq, desc);
  63 }
  64
  65 void __cmx270_pci_init_irq(void)
  66 {
  67         it8152_init_irq();
  68         pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
  69         set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
  70
  71         set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
  72                                 cmx270_it8152_irq_demux);
  73 }
  74
  75 #ifdef CONFIG_PM
  76 static unsigned long sleep_save_ite[10];
  77
  78 void __cmx270_pci_suspend(void)
  79 {
  80         /* save ITE state */
  81         sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
  82         sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
  83         sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
  84
  85         /* Clear ITE IRQ's */
  86         __raw_writel((0), IT8152_INTC_PDCNIRR);
  87         __raw_writel((0), IT8152_INTC_LPCNIRR);
  88 }
  89
  90 void __cmx270_pci_resume(void)
  91 {
  92         /* restore IT8152 state */
  93         __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
  94         __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
  95         __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
  96 }
  97 #else
  98 void cmx270_pci_suspend(void) {}
  99 void cmx270_pci_resume(void) {}
 100 #endif
 101
 102 /* PCI IRQ mapping*/
 103 static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 104 {
 105         int irq;
 106
 107         printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__,
 108                pci_name(dev), slot, pin);
 109
 110         irq = it8152_pci_map_irq(dev, slot, pin);
 111         if (irq)
 112                 return irq;
 113
 114         /*
 115           Here comes the ugly part. The routing is baseboard specific,
 116           but defining a platform for each possible base of CM-x270 is
 117           unrealistic. Here we keep mapping for ATXBase and SB-x270.
 118         */
 119         /* ATXBASE PCI slot */
 120         if (slot == 7)
 121                 return IT8152_PCI_INTA;
 122
 123         /* ATXBase/SB-x270 CardBus */
 124         if (slot == 8 || slot == 0)
 125                 return IT8152_PCI_INTB;
 126
 127         /* ATXBase Ethernet */
 128         if (slot == 9)
 129                 return IT8152_PCI_INTA;
 130
 131         /* SB-x270 Ethernet */
 132         if (slot == 16)
 133                 return IT8152_PCI_INTA;
 134
 135         /* PC104+ interrupt routing */
 136         if ((slot == 17) || (slot == 19))
 137                 return IT8152_PCI_INTA;
 138         if ((slot == 18) || (slot == 20))
 139                 return IT8152_PCI_INTB;
 140
 141         return(0);
 142 }
 143
 144 static struct pci_bus * __init
 145 cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
 146 {
 147         printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n");
 148
 149         __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
 150         if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
 151                 printk(KERN_INFO "PCI Bridge found.\n");
 152
 153                 /* set PCI I/O base at 0 */
 154                 writel(0x848, IT8152_PCI_CFG_ADDR);
 155                 writel(0, IT8152_PCI_CFG_DATA);
 156
 157                 /* set PCI memory base at 0 */
 158                 writel(0x840, IT8152_PCI_CFG_ADDR);
 159                 writel(0, IT8152_PCI_CFG_DATA);
 160
 161                 writel(0x20, IT8152_GPIO_GPDR);
 162
 163                 /* CardBus Controller on ATXbase baseboard */
 164                 writel(0x4000, IT8152_PCI_CFG_ADDR);
 165                 if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
 166                         printk(KERN_INFO "CardBus Bridge found.\n");
 167
 168                         /* Configure socket 0 */
 169                         writel(0x408C, IT8152_PCI_CFG_ADDR);
 170                         writel(0x1022, IT8152_PCI_CFG_DATA);
 171
 172                         writel(0x4080, IT8152_PCI_CFG_ADDR);
 173                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 174
 175                         writel(0x4090, IT8152_PCI_CFG_ADDR);
 176                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 177                                 0x60440000),
 178                                IT8152_PCI_CFG_DATA);
 179
 180                         writel(0x4018, IT8152_PCI_CFG_ADDR);
 181                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 182
 183                         /* Configure socket 1 */
 184                         writel(0x418C, IT8152_PCI_CFG_ADDR);
 185                         writel(0x1022, IT8152_PCI_CFG_DATA);
 186
 187                         writel(0x4180, IT8152_PCI_CFG_ADDR);
 188                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 189
 190                         writel(0x4190, IT8152_PCI_CFG_ADDR);
 191                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 192                                 0x60440000),
 193                                IT8152_PCI_CFG_DATA);
 194
 195                         writel(0x4118, IT8152_PCI_CFG_ADDR);
 196                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 197                 }
 198         }
 199         return it8152_pci_scan_bus(nr, sys);
 200 }
 201
 202 static struct hw_pci cmx270_pci __initdata = {
 203         .swizzle        = pci_std_swizzle,
 204         .map_irq        = cmx270_pci_map_irq,
 205         .nr_controllers = 1,
 206         .setup          = it8152_pci_setup,
 207         .scan           = cmx270_pci_scan_bus,
 208 };
 209
 210 static int __init cmx270_init_pci(void)
 211 {
 212         if (machine_is_armcore())
 213                 pci_common_init(&cmx270_pci);
 214
 215         return 0;
 216 }
 217
 218 subsys_initcall(cmx270_init_pci);