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[ALSA] cs4231-lib: replace common delay loop by function
[linux-2.6/verdex.git] / arch / mips / au1000 / common / irq.c
bloba6640b998c6e06f99fca5982cb039562f15e3ccc
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/kernel_stat.h>
33 #include <linux/module.h>
34 #include <linux/signal.h>
35 #include <linux/sched.h>
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/timex.h>
40 #include <linux/slab.h>
41 #include <linux/random.h>
42 #include <linux/delay.h>
43 #include <linux/bitops.h>
44
45 #include <asm/bootinfo.h>
46 #include <asm/io.h>
47 #include <asm/mipsregs.h>
48 #include <asm/system.h>
49 #include <asm/mach-au1x00/au1000.h>
50 #ifdef CONFIG_MIPS_PB1000
51 #include <asm/mach-pb1x00/pb1000.h>
52 #endif
53
54 #undef DEBUG_IRQ
55 #ifdef DEBUG_IRQ
56 /* note: prints function name for you */
57 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
58 #else
59 #define DPRINTK(fmt, args...)
60 #endif
61
62 #define EXT_INTC0_REQ0 2 /* IP 2 */
63 #define EXT_INTC0_REQ1 3 /* IP 3 */
64 #define EXT_INTC1_REQ0 4 /* IP 4 */
65 #define EXT_INTC1_REQ1 5 /* IP 5 */
66 #define MIPS_TIMER_IP 7 /* IP 7 */
67
68 void (*board_init_irq)(void);
69
70 static DEFINE_SPINLOCK(irq_lock);
71
72
73 inline void local_enable_irq(unsigned int irq_nr)
74 {
75 if (irq_nr > AU1000_LAST_INTC0_INT) {
76 au_writel(1<<(irq_nr-32), IC1_MASKSET);
77 au_writel(1<<(irq_nr-32), IC1_WAKESET);
78 }
79 else {
80 au_writel(1<<irq_nr, IC0_MASKSET);
81 au_writel(1<<irq_nr, IC0_WAKESET);
82 }
83 au_sync();
84 }
85
86
87 inline void local_disable_irq(unsigned int irq_nr)
88 {
89 if (irq_nr > AU1000_LAST_INTC0_INT) {
90 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
91 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
92 }
93 else {
94 au_writel(1<<irq_nr, IC0_MASKCLR);
95 au_writel(1<<irq_nr, IC0_WAKECLR);
96 }
97 au_sync();
98 }
99
100
101 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
102 {
103 if (irq_nr > AU1000_LAST_INTC0_INT) {
104 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
105 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
106 }
107 else {
108 au_writel(1<<irq_nr, IC0_RISINGCLR);
109 au_writel(1<<irq_nr, IC0_MASKCLR);
110 }
111 au_sync();
112 }
113
114
115 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
116 {
117 if (irq_nr > AU1000_LAST_INTC0_INT) {
118 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
119 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
120 }
121 else {
122 au_writel(1<<irq_nr, IC0_FALLINGCLR);
123 au_writel(1<<irq_nr, IC0_MASKCLR);
124 }
125 au_sync();
126 }
127
128
129 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
130 {
131 /* This may assume that we don't get interrupts from
132 * both edges at once, or if we do, that we don't care.
133 */
134 if (irq_nr > AU1000_LAST_INTC0_INT) {
135 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
136 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
137 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
138 }
139 else {
140 au_writel(1<<irq_nr, IC0_FALLINGCLR);
141 au_writel(1<<irq_nr, IC0_RISINGCLR);
142 au_writel(1<<irq_nr, IC0_MASKCLR);
143 }
144 au_sync();
145 }
146
147
148 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
149 {
150
151 local_disable_irq(irq_nr);
152 au_sync();
153 #if defined(CONFIG_MIPS_PB1000)
154 if (irq_nr == AU1000_GPIO_15) {
155 au_writel(0x8000, PB1000_MDR); /* ack int */
156 au_sync();
157 }
158 #endif
159 return;
160 }
161
162
163 static void end_irq(unsigned int irq_nr)
164 {
165 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
166 local_enable_irq(irq_nr);
167 }
168 #if defined(CONFIG_MIPS_PB1000)
169 if (irq_nr == AU1000_GPIO_15) {
170 au_writel(0x4000, PB1000_MDR); /* enable int */
171 au_sync();
172 }
173 #endif
174 }
175
176 unsigned long save_local_and_disable(int controller)
177 {
178 int i;
179 unsigned long flags, mask;
180
181 spin_lock_irqsave(&irq_lock, flags);
182 if (controller) {
183 mask = au_readl(IC1_MASKSET);
184 for (i=32; i<64; i++) {
185 local_disable_irq(i);
186 }
187 }
188 else {
189 mask = au_readl(IC0_MASKSET);
190 for (i=0; i<32; i++) {
191 local_disable_irq(i);
192 }
193 }
194 spin_unlock_irqrestore(&irq_lock, flags);
195
196 return mask;
197 }
198
199 void restore_local_and_enable(int controller, unsigned long mask)
200 {
201 int i;
202 unsigned long flags, new_mask;
203
204 spin_lock_irqsave(&irq_lock, flags);
205 for (i=0; i<32; i++) {
206 if (mask & (1<<i)) {
207 if (controller)
208 local_enable_irq(i+32);
209 else
210 local_enable_irq(i);
211 }
212 }
213 if (controller)
214 new_mask = au_readl(IC1_MASKSET);
215 else
216 new_mask = au_readl(IC0_MASKSET);
217
218 spin_unlock_irqrestore(&irq_lock, flags);
219 }
220
221
222 static struct irq_chip rise_edge_irq_type = {
223 .name = "Au1000 Rise Edge",
224 .ack = mask_and_ack_rise_edge_irq,
225 .mask = local_disable_irq,
226 .mask_ack = mask_and_ack_rise_edge_irq,
227 .unmask = local_enable_irq,
228 .end = end_irq,
229 };
230
231 static struct irq_chip fall_edge_irq_type = {
232 .name = "Au1000 Fall Edge",
233 .ack = mask_and_ack_fall_edge_irq,
234 .mask = local_disable_irq,
235 .mask_ack = mask_and_ack_fall_edge_irq,
236 .unmask = local_enable_irq,
237 .end = end_irq,
238 };
239
240 static struct irq_chip either_edge_irq_type = {
241 .name = "Au1000 Rise or Fall Edge",
242 .ack = mask_and_ack_either_edge_irq,
243 .mask = local_disable_irq,
244 .mask_ack = mask_and_ack_either_edge_irq,
245 .unmask = local_enable_irq,
246 .end = end_irq,
247 };
248
249 static struct irq_chip level_irq_type = {
250 .name = "Au1000 Level",
251 .ack = mask_and_ack_level_irq,
252 .mask = local_disable_irq,
253 .mask_ack = mask_and_ack_level_irq,
254 .unmask = local_enable_irq,
255 .end = end_irq,
256 };
257
258 #ifdef CONFIG_PM
259 void startup_match20_interrupt(irq_handler_t handler)
260 {
261 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
262
263 static struct irqaction action;
264 memset(&action, 0, sizeof(struct irqaction));
265
266 /* This is a big problem.... since we didn't use request_irq
267 * when kernel/irq.c calls probe_irq_xxx this interrupt will
268 * be probed for usage. This will end up disabling the device :(
269 * Give it a bogus "action" pointer -- this will keep it from
270 * getting auto-probed!
271 *
272 * By setting the status to match that of request_irq() we
273 * can avoid it. --cgray
274 */
275 action.dev_id = handler;
276 action.flags = IRQF_DISABLED;
277 cpus_clear(action.mask);
278 action.name = "Au1xxx TOY";
279 action.handler = handler;
280 action.next = NULL;
281
282 desc->action = &action;
283 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
284
285 local_enable_irq(AU1000_TOY_MATCH2_INT);
286 }
287 #endif
288
289 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
290 {
291 if (irq_nr > AU1000_MAX_INTR) return;
292 /* Config2[n], Config1[n], Config0[n] */
293 if (irq_nr > AU1000_LAST_INTC0_INT) {
294 switch (type) {
295 case INTC_INT_RISE_EDGE: /* 0:0:1 */
296 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
297 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
298 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
299 set_irq_chip(irq_nr, &rise_edge_irq_type);
300 break;
301 case INTC_INT_FALL_EDGE: /* 0:1:0 */
302 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
303 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
304 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
305 set_irq_chip(irq_nr, &fall_edge_irq_type);
306 break;
307 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
308 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
309 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
310 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
311 set_irq_chip(irq_nr, &either_edge_irq_type);
312 break;
313 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
314 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
315 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
316 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
317 set_irq_chip(irq_nr, &level_irq_type);
318 break;
319 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
320 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
321 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
322 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
323 set_irq_chip(irq_nr, &level_irq_type);
324 break;
325 case INTC_INT_DISABLED: /* 0:0:0 */
326 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
327 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 break;
330 default: /* disable the interrupt */
331 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
332 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
333 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 return;
336 }
337 if (int_req) /* assign to interrupt request 1 */
338 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
339 else /* assign to interrupt request 0 */
340 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
341 au_writel(1<<(irq_nr-32), IC1_SRCSET);
342 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
343 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
344 }
345 else {
346 switch (type) {
347 case INTC_INT_RISE_EDGE: /* 0:0:1 */
348 au_writel(1<<irq_nr, IC0_CFG2CLR);
349 au_writel(1<<irq_nr, IC0_CFG1CLR);
350 au_writel(1<<irq_nr, IC0_CFG0SET);
351 set_irq_chip(irq_nr, &rise_edge_irq_type);
352 break;
353 case INTC_INT_FALL_EDGE: /* 0:1:0 */
354 au_writel(1<<irq_nr, IC0_CFG2CLR);
355 au_writel(1<<irq_nr, IC0_CFG1SET);
356 au_writel(1<<irq_nr, IC0_CFG0CLR);
357 set_irq_chip(irq_nr, &fall_edge_irq_type);
358 break;
359 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
360 au_writel(1<<irq_nr, IC0_CFG2CLR);
361 au_writel(1<<irq_nr, IC0_CFG1SET);
362 au_writel(1<<irq_nr, IC0_CFG0SET);
363 set_irq_chip(irq_nr, &either_edge_irq_type);
364 break;
365 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
366 au_writel(1<<irq_nr, IC0_CFG2SET);
367 au_writel(1<<irq_nr, IC0_CFG1CLR);
368 au_writel(1<<irq_nr, IC0_CFG0SET);
369 set_irq_chip(irq_nr, &level_irq_type);
370 break;
371 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
372 au_writel(1<<irq_nr, IC0_CFG2SET);
373 au_writel(1<<irq_nr, IC0_CFG1SET);
374 au_writel(1<<irq_nr, IC0_CFG0CLR);
375 set_irq_chip(irq_nr, &level_irq_type);
376 break;
377 case INTC_INT_DISABLED: /* 0:0:0 */
378 au_writel(1<<irq_nr, IC0_CFG0CLR);
379 au_writel(1<<irq_nr, IC0_CFG1CLR);
380 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 break;
382 default: /* disable the interrupt */
383 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
384 au_writel(1<<irq_nr, IC0_CFG0CLR);
385 au_writel(1<<irq_nr, IC0_CFG1CLR);
386 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 return;
388 }
389 if (int_req) /* assign to interrupt request 1 */
390 au_writel(1<<irq_nr, IC0_ASSIGNCLR);
391 else /* assign to interrupt request 0 */
392 au_writel(1<<irq_nr, IC0_ASSIGNSET);
393 au_writel(1<<irq_nr, IC0_SRCSET);
394 au_writel(1<<irq_nr, IC0_MASKCLR);
395 au_writel(1<<irq_nr, IC0_WAKECLR);
396 }
397 au_sync();
398 }
399
400
401 void __init arch_init_irq(void)
402 {
403 int i;
404 unsigned long cp0_status;
405 au1xxx_irq_map_t *imp;
406 extern au1xxx_irq_map_t au1xxx_irq_map[];
407 extern au1xxx_irq_map_t au1xxx_ic0_map[];
408 extern int au1xxx_nr_irqs;
409 extern int au1xxx_ic0_nr_irqs;
410
411 cp0_status = read_c0_status();
412
413 /* Initialize interrupt controllers to a safe state.
414 */
415 au_writel(0xffffffff, IC0_CFG0CLR);
416 au_writel(0xffffffff, IC0_CFG1CLR);
417 au_writel(0xffffffff, IC0_CFG2CLR);
418 au_writel(0xffffffff, IC0_MASKCLR);
419 au_writel(0xffffffff, IC0_ASSIGNSET);
420 au_writel(0xffffffff, IC0_WAKECLR);
421 au_writel(0xffffffff, IC0_SRCSET);
422 au_writel(0xffffffff, IC0_FALLINGCLR);
423 au_writel(0xffffffff, IC0_RISINGCLR);
424 au_writel(0x00000000, IC0_TESTBIT);
425
426 au_writel(0xffffffff, IC1_CFG0CLR);
427 au_writel(0xffffffff, IC1_CFG1CLR);
428 au_writel(0xffffffff, IC1_CFG2CLR);
429 au_writel(0xffffffff, IC1_MASKCLR);
430 au_writel(0xffffffff, IC1_ASSIGNSET);
431 au_writel(0xffffffff, IC1_WAKECLR);
432 au_writel(0xffffffff, IC1_SRCSET);
433 au_writel(0xffffffff, IC1_FALLINGCLR);
434 au_writel(0xffffffff, IC1_RISINGCLR);
435 au_writel(0x00000000, IC1_TESTBIT);
436
437 /* Initialize IC0, which is fixed per processor.
438 */
439 imp = au1xxx_ic0_map;
440 for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
441 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
442 imp++;
443 }
444
445 /* Now set up the irq mapping for the board.
446 */
447 imp = au1xxx_irq_map;
448 for (i=0; i<au1xxx_nr_irqs; i++) {
449 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
450 imp++;
451 }
452
453 set_c0_status(ALLINTS);
454
455 /* Board specific IRQ initialization.
456 */
457 if (board_init_irq)
458 (*board_init_irq)();
459 }
460
461
462 /*
463 * Interrupts are nested. Even if an interrupt handler is registered
464 * as "fast", we might get another interrupt before we return from
465 * intcX_reqX_irqdispatch().
466 */
467
468 static void intc0_req0_irqdispatch(void)
469 {
470 int irq = 0;
471 static unsigned long intc0_req0 = 0;
472
473 intc0_req0 |= au_readl(IC0_REQ0INT);
474
475 if (!intc0_req0)
476 return;
477 #ifdef AU1000_USB_DEV_REQ_INT
478 /*
479 * Because of the tight timing of SETUP token to reply
480 * transactions, the USB devices-side packet complete
481 * interrupt needs the highest priority.
482 */
483 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
484 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
485 do_IRQ(AU1000_USB_DEV_REQ_INT);
486 return;
487 }
488 #endif
489 irq = au_ffs(intc0_req0) - 1;
490 intc0_req0 &= ~(1<<irq);
491 do_IRQ(irq);
492 }
493
494
495 static void intc0_req1_irqdispatch(void)
496 {
497 int irq = 0;
498 static unsigned long intc0_req1 = 0;
499
500 intc0_req1 |= au_readl(IC0_REQ1INT);
501
502 if (!intc0_req1)
503 return;
504
505 irq = au_ffs(intc0_req1) - 1;
506 intc0_req1 &= ~(1<<irq);
507 do_IRQ(irq);
508 }
509
510
511 /*
512 * Interrupt Controller 1:
513 * interrupts 32 - 63
514 */
515 static void intc1_req0_irqdispatch(void)
516 {
517 int irq = 0;
518 static unsigned long intc1_req0 = 0;
519
520 intc1_req0 |= au_readl(IC1_REQ0INT);
521
522 if (!intc1_req0)
523 return;
524
525 irq = au_ffs(intc1_req0) - 1;
526 intc1_req0 &= ~(1<<irq);
527 irq += 32;
528 do_IRQ(irq);
529 }
530
531
532 static void intc1_req1_irqdispatch(void)
533 {
534 int irq = 0;
535 static unsigned long intc1_req1 = 0;
536
537 intc1_req1 |= au_readl(IC1_REQ1INT);
538
539 if (!intc1_req1)
540 return;
541
542 irq = au_ffs(intc1_req1) - 1;
543 intc1_req1 &= ~(1<<irq);
544 irq += 32;
545 do_IRQ(irq);
546 }
547
548 #ifdef CONFIG_PM
549
550 /* Save/restore the interrupt controller state.
551 * Called from the save/restore core registers as part of the
552 * au_sleep function in power.c.....maybe I should just pm_register()
553 * them instead?
554 */
555 static unsigned int sleep_intctl_config0[2];
556 static unsigned int sleep_intctl_config1[2];
557 static unsigned int sleep_intctl_config2[2];
558 static unsigned int sleep_intctl_src[2];
559 static unsigned int sleep_intctl_assign[2];
560 static unsigned int sleep_intctl_wake[2];
561 static unsigned int sleep_intctl_mask[2];
562
563 void
564 save_au1xxx_intctl(void)
565 {
566 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
567 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
568 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
569 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
570 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
571 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
572 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
573
574 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
575 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
576 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
577 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
578 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
579 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
580 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
581 }
582
583 /* For most restore operations, we clear the entire register and
584 * then set the bits we found during the save.
585 */
586 void
587 restore_au1xxx_intctl(void)
588 {
589 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
590
591 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
592 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
593 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
594 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
595 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
596 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
597 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
598 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
599 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
600 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
601 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
602 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
603 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
604 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
605 au_writel(0x00000000, IC0_TESTBIT); au_sync();
606
607 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
608
609 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
610 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
611 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
612 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
613 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
614 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
615 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
616 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
617 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
618 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
619 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
620 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
621 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
622 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
623 au_writel(0x00000000, IC1_TESTBIT); au_sync();
624
625 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
626
627 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
628 }
629 #endif /* CONFIG_PM */
630
631 asmlinkage void plat_irq_dispatch(void)
632 {
633 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
634
635 if (pending & CAUSEF_IP7)
636 do_IRQ(63);
637 else if (pending & CAUSEF_IP2)
638 intc0_req0_irqdispatch();
639 else if (pending & CAUSEF_IP3)
640 intc0_req1_irqdispatch();
641 else if (pending & CAUSEF_IP4)
642 intc1_req0_irqdispatch();
643 else if (pending & CAUSEF_IP5)
644 intc1_req1_irqdispatch();
645 else
646 spurious_interrupt();
647 }
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