arch/mips/kernel/i8253.c

   1 /*
   2  * i8253.c  8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/spinlock.h>
  11
  12 #include <asm/delay.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15
  16 static DEFINE_SPINLOCK(i8253_lock);
  17
  18 /*
  19  * Initialize the PIT timer.
  20  *
  21  * This is also called after resume to bring the PIT into operation again.
  22  */
  23 static void init_pit_timer(enum clock_event_mode mode,
  24                            struct clock_event_device *evt)
  25 {
  26         unsigned long flags;
  27
  28         spin_lock_irqsave(&i8253_lock, flags);
  29
  30         switch(mode) {
  31         case CLOCK_EVT_MODE_PERIODIC:
  32                 /* binary, mode 2, LSB/MSB, ch 0 */
  33                 outb_p(0x34, PIT_MODE);
  34                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
  35                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
  36                 break;
  37
  38         case CLOCK_EVT_MODE_SHUTDOWN:
  39         case CLOCK_EVT_MODE_UNUSED:
  40                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  41                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  42                         outb_p(0x30, PIT_MODE);
  43                         outb_p(0, PIT_CH0);
  44                         outb_p(0, PIT_CH0);
  45                 }
  46                 break;
  47
  48         case CLOCK_EVT_MODE_ONESHOT:
  49                 /* One shot setup */
  50                 outb_p(0x38, PIT_MODE);
  51                 break;
  52
  53         case CLOCK_EVT_MODE_RESUME:
  54                 /* Nothing to do here */
  55                 break;
  56         }
  57         spin_unlock_irqrestore(&i8253_lock, flags);
  58 }
  59
  60 /*
  61  * Program the next event in oneshot mode
  62  *
  63  * Delta is given in PIT ticks
  64  */
  65 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  66 {
  67         unsigned long flags;
  68
  69         spin_lock_irqsave(&i8253_lock, flags);
  70         outb_p(delta & 0xff , PIT_CH0); /* LSB */
  71         outb(delta >> 8 , PIT_CH0);     /* MSB */
  72         spin_unlock_irqrestore(&i8253_lock, flags);
  73
  74         return 0;
  75 }
  76
  77 /*
  78  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  79  * it can be solely used for the global tick.
  80  *
  81  * The profiling and update capabilites are switched off once the local apic is
  82  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  83  * !using_apic_timer decisions in do_timer_interrupt_hook()
  84  */
  85 struct clock_event_device pit_clockevent = {
  86         .name           = "pit",
  87         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  88         .set_mode       = init_pit_timer,
  89         .set_next_event = pit_next_event,
  90         .shift          = 32,
  91         .irq            = 0,
  92 };
  93
  94 irqreturn_t timer_interrupt(int irq, void *dev_id)
  95 {
  96         pit_clockevent.event_handler(&pit_clockevent);
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 static struct irqaction irq0  = {
 102         .handler = timer_interrupt,
 103         .flags = IRQF_DISABLED | IRQF_NOBALANCING,
 104         .mask = CPU_MASK_NONE,
 105         .name = "timer"
 106 };
 107
 108 /*
 109  * Initialize the conversion factor and the min/max deltas of the clock event
 110  * structure and register the clock event source with the framework.
 111  */
 112 void __init setup_pit_timer(void)
 113 {
 114         /*
 115          * Start pit with the boot cpu mask and make it global after the
 116          * IO_APIC has been initialized.
 117          */
 118         pit_clockevent.cpumask = cpumask_of_cpu(0);
 119         pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
 120         pit_clockevent.max_delta_ns =
 121                 clockevent_delta2ns(0x7FFF, &pit_clockevent);
 122         pit_clockevent.min_delta_ns =
 123                 clockevent_delta2ns(0xF, &pit_clockevent);
 124         clockevents_register_device(&pit_clockevent);
 125
 126         irq0.mask = cpumask_of_cpu(0);
 127         setup_irq(0, &irq0);
 128 }
 129
 130 /*
 131  * Since the PIT overflows every tick, its not very useful
 132  * to just read by itself. So use jiffies to emulate a free
 133  * running counter:
 134  */
 135 static cycle_t pit_read(void)
 136 {
 137         unsigned long flags;
 138         int count;
 139         u32 jifs;
 140         static int old_count;
 141         static u32 old_jifs;
 142
 143         spin_lock_irqsave(&i8253_lock, flags);
 144         /*
 145          * Although our caller may have the read side of xtime_lock,
 146          * this is now a seqlock, and we are cheating in this routine
 147          * by having side effects on state that we cannot undo if
 148          * there is a collision on the seqlock and our caller has to
 149          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 150          * jiffies as volatile despite the lock.  We read jiffies
 151          * before latching the timer count to guarantee that although
 152          * the jiffies value might be older than the count (that is,
 153          * the counter may underflow between the last point where
 154          * jiffies was incremented and the point where we latch the
 155          * count), it cannot be newer.
 156          */
 157         jifs = jiffies;
 158         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
 159         count = inb_p(PIT_CH0); /* read the latched count */
 160         count |= inb_p(PIT_CH0) << 8;
 161
 162         /* VIA686a test code... reset the latch if count > max + 1 */
 163         if (count > LATCH) {
 164                 outb_p(0x34, PIT_MODE);
 165                 outb_p(LATCH & 0xff, PIT_CH0);
 166                 outb(LATCH >> 8, PIT_CH0);
 167                 count = LATCH - 1;
 168         }
 169
 170         /*
 171          * It's possible for count to appear to go the wrong way for a
 172          * couple of reasons:
 173          *
 174          *  1. The timer counter underflows, but we haven't handled the
 175          *     resulting interrupt and incremented jiffies yet.
 176          *  2. Hardware problem with the timer, not giving us continuous time,
 177          *     the counter does small "jumps" upwards on some Pentium systems,
 178          *     (see c't 95/10 page 335 for Neptun bug.)
 179          *
 180          * Previous attempts to handle these cases intelligently were
 181          * buggy, so we just do the simple thing now.
 182          */
 183         if (count > old_count && jifs == old_jifs) {
 184                 count = old_count;
 185         }
 186         old_count = count;
 187         old_jifs = jifs;
 188
 189         spin_unlock_irqrestore(&i8253_lock, flags);
 190
 191         count = (LATCH - 1) - count;
 192
 193         return (cycle_t)(jifs * LATCH) + count;
 194 }
 195
 196 static struct clocksource clocksource_pit = {
 197         .name   = "pit",
 198         .rating = 110,
 199         .read   = pit_read,
 200         .mask   = CLOCKSOURCE_MASK(32),
 201         .mult   = 0,
 202         .shift  = 20,
 203 };
 204
 205 static int __init init_pit_clocksource(void)
 206 {
 207         if (num_possible_cpus() > 1) /* PIT does not scale! */
 208                 return 0;
 209
 210         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
 211         return clocksource_register(&clocksource_pit);
 212 }
 213 arch_initcall(init_pit_clocksource);