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[ALSA] cs4231-lib: replace common delay loop by function
[linux-2.6/verdex.git] / arch / sparc64 / kernel / irq.c
blobf3922e5a89f6c52330b5d6b1cf9ed23353bafba5
1 /* irq.c: UltraSparc IRQ handling/init/registry.
2 *
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
14 #include <linux/mm.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/bootmem.h>
23 #include <linux/irq.h>
24
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/atomic.h>
28 #include <asm/system.h>
29 #include <asm/irq.h>
30 #include <asm/io.h>
31 #include <asm/sbus.h>
32 #include <asm/iommu.h>
33 #include <asm/upa.h>
34 #include <asm/oplib.h>
35 #include <asm/prom.h>
36 #include <asm/timer.h>
37 #include <asm/smp.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
43 #include <asm/head.h>
44 #include <asm/hypervisor.h>
45 #include <asm/cacheflush.h>
46
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
51 *
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 *
56 * If you make changes to ino_bucket, please update hand coded assembler
57 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
58 */
59 struct ino_bucket {
60 /*0x00*/unsigned long __irq_chain_pa;
61
62 /* Virtual interrupt number assigned to this INO. */
63 /*0x08*/unsigned int __virt_irq;
64 /*0x0c*/unsigned int __pad;
65 };
66
67 #define NUM_IVECS (IMAP_INR + 1)
68 struct ino_bucket *ivector_table;
69 unsigned long ivector_table_pa;
70
71 /* On several sun4u processors, it is illegal to mix bypass and
72 * non-bypass accesses. Therefore we access all INO buckets
73 * using bypass accesses only.
74 */
75 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
76 {
77 unsigned long ret;
78
79 __asm__ __volatile__("ldxa [%1] %2, %0"
80 : "=&r" (ret)
81 : "r" (bucket_pa +
82 offsetof(struct ino_bucket,
83 __irq_chain_pa)),
84 "i" (ASI_PHYS_USE_EC));
85
86 return ret;
87 }
88
89 static void bucket_clear_chain_pa(unsigned long bucket_pa)
90 {
91 __asm__ __volatile__("stxa %%g0, [%0] %1"
92 : /* no outputs */
93 : "r" (bucket_pa +
94 offsetof(struct ino_bucket,
95 __irq_chain_pa)),
96 "i" (ASI_PHYS_USE_EC));
97 }
98
99 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
100 {
101 unsigned int ret;
102
103 __asm__ __volatile__("lduwa [%1] %2, %0"
104 : "=&r" (ret)
105 : "r" (bucket_pa +
106 offsetof(struct ino_bucket,
107 __virt_irq)),
108 "i" (ASI_PHYS_USE_EC));
109
110 return ret;
111 }
112
113 static void bucket_set_virt_irq(unsigned long bucket_pa,
114 unsigned int virt_irq)
115 {
116 __asm__ __volatile__("stwa %0, [%1] %2"
117 : /* no outputs */
118 : "r" (virt_irq),
119 "r" (bucket_pa +
120 offsetof(struct ino_bucket,
121 __virt_irq)),
122 "i" (ASI_PHYS_USE_EC));
123 }
124
125 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
126
127 static struct {
128 unsigned int dev_handle;
129 unsigned int dev_ino;
130 unsigned int in_use;
131 } virt_irq_table[NR_IRQS];
132 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
133
134 unsigned char virt_irq_alloc(unsigned int dev_handle,
135 unsigned int dev_ino)
136 {
137 unsigned long flags;
138 unsigned char ent;
139
140 BUILD_BUG_ON(NR_IRQS >= 256);
141
142 spin_lock_irqsave(&virt_irq_alloc_lock, flags);
143
144 for (ent = 1; ent < NR_IRQS; ent++) {
145 if (!virt_irq_table[ent].in_use)
146 break;
147 }
148 if (ent >= NR_IRQS) {
149 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
150 ent = 0;
151 } else {
152 virt_irq_table[ent].dev_handle = dev_handle;
153 virt_irq_table[ent].dev_ino = dev_ino;
154 virt_irq_table[ent].in_use = 1;
155 }
156
157 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
158
159 return ent;
160 }
161
162 #ifdef CONFIG_PCI_MSI
163 void virt_irq_free(unsigned int virt_irq)
164 {
165 unsigned long flags;
166
167 if (virt_irq >= NR_IRQS)
168 return;
169
170 spin_lock_irqsave(&virt_irq_alloc_lock, flags);
171
172 virt_irq_table[virt_irq].in_use = 0;
173
174 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
175 }
176 #endif
177
178 /*
179 * /proc/interrupts printing:
180 */
181
182 int show_interrupts(struct seq_file *p, void *v)
183 {
184 int i = *(loff_t *) v, j;
185 struct irqaction * action;
186 unsigned long flags;
187
188 if (i == 0) {
189 seq_printf(p, " ");
190 for_each_online_cpu(j)
191 seq_printf(p, "CPU%d ",j);
192 seq_putc(p, '\n');
193 }
194
195 if (i < NR_IRQS) {
196 spin_lock_irqsave(&irq_desc[i].lock, flags);
197 action = irq_desc[i].action;
198 if (!action)
199 goto skip;
200 seq_printf(p, "%3d: ",i);
201 #ifndef CONFIG_SMP
202 seq_printf(p, "%10u ", kstat_irqs(i));
203 #else
204 for_each_online_cpu(j)
205 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
206 #endif
207 seq_printf(p, " %9s", irq_desc[i].chip->typename);
208 seq_printf(p, " %s", action->name);
209
210 for (action=action->next; action; action = action->next)
211 seq_printf(p, ", %s", action->name);
212
213 seq_putc(p, '\n');
214 skip:
215 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
216 }
217 return 0;
218 }
219
220 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
221 {
222 unsigned int tid;
223
224 if (this_is_starfire) {
225 tid = starfire_translate(imap, cpuid);
226 tid <<= IMAP_TID_SHIFT;
227 tid &= IMAP_TID_UPA;
228 } else {
229 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
230 unsigned long ver;
231
232 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
233 if ((ver >> 32UL) == __JALAPENO_ID ||
234 (ver >> 32UL) == __SERRANO_ID) {
235 tid = cpuid << IMAP_TID_SHIFT;
236 tid &= IMAP_TID_JBUS;
237 } else {
238 unsigned int a = cpuid & 0x1f;
239 unsigned int n = (cpuid >> 5) & 0x1f;
240
241 tid = ((a << IMAP_AID_SHIFT) |
242 (n << IMAP_NID_SHIFT));
243 tid &= (IMAP_AID_SAFARI |
244 IMAP_NID_SAFARI);;
245 }
246 } else {
247 tid = cpuid << IMAP_TID_SHIFT;
248 tid &= IMAP_TID_UPA;
249 }
250 }
251
252 return tid;
253 }
254
255 struct irq_handler_data {
256 unsigned long iclr;
257 unsigned long imap;
258
259 void (*pre_handler)(unsigned int, void *, void *);
260 void *pre_handler_arg1;
261 void *pre_handler_arg2;
262 };
263
264 #ifdef CONFIG_SMP
265 static int irq_choose_cpu(unsigned int virt_irq)
266 {
267 cpumask_t mask = irq_desc[virt_irq].affinity;
268 int cpuid;
269
270 if (cpus_equal(mask, CPU_MASK_ALL)) {
271 static int irq_rover;
272 static DEFINE_SPINLOCK(irq_rover_lock);
273 unsigned long flags;
274
275 /* Round-robin distribution... */
276 do_round_robin:
277 spin_lock_irqsave(&irq_rover_lock, flags);
278
279 while (!cpu_online(irq_rover)) {
280 if (++irq_rover >= NR_CPUS)
281 irq_rover = 0;
282 }
283 cpuid = irq_rover;
284 do {
285 if (++irq_rover >= NR_CPUS)
286 irq_rover = 0;
287 } while (!cpu_online(irq_rover));
288
289 spin_unlock_irqrestore(&irq_rover_lock, flags);
290 } else {
291 cpumask_t tmp;
292
293 cpus_and(tmp, cpu_online_map, mask);
294
295 if (cpus_empty(tmp))
296 goto do_round_robin;
297
298 cpuid = first_cpu(tmp);
299 }
300
301 return cpuid;
302 }
303 #else
304 static int irq_choose_cpu(unsigned int virt_irq)
305 {
306 return real_hard_smp_processor_id();
307 }
308 #endif
309
310 static void sun4u_irq_enable(unsigned int virt_irq)
311 {
312 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
313
314 if (likely(data)) {
315 unsigned long cpuid, imap, val;
316 unsigned int tid;
317
318 cpuid = irq_choose_cpu(virt_irq);
319 imap = data->imap;
320
321 tid = sun4u_compute_tid(imap, cpuid);
322
323 val = upa_readq(imap);
324 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
325 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
326 val |= tid | IMAP_VALID;
327 upa_writeq(val, imap);
328 }
329 }
330
331 static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
332 {
333 sun4u_irq_enable(virt_irq);
334 }
335
336 static void sun4u_irq_disable(unsigned int virt_irq)
337 {
338 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
339
340 if (likely(data)) {
341 unsigned long imap = data->imap;
342 unsigned long tmp = upa_readq(imap);
343
344 tmp &= ~IMAP_VALID;
345 upa_writeq(tmp, imap);
346 }
347 }
348
349 static void sun4u_irq_end(unsigned int virt_irq)
350 {
351 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
352 struct irq_desc *desc = irq_desc + virt_irq;
353
354 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
355 return;
356
357 if (likely(data))
358 upa_writeq(ICLR_IDLE, data->iclr);
359 }
360
361 static void sun4v_irq_enable(unsigned int virt_irq)
362 {
363 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
364 unsigned long cpuid = irq_choose_cpu(virt_irq);
365 int err;
366
367 err = sun4v_intr_settarget(ino, cpuid);
368 if (err != HV_EOK)
369 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
370 "err(%d)\n", ino, cpuid, err);
371 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
372 if (err != HV_EOK)
373 printk(KERN_ERR "sun4v_intr_setstate(%x): "
374 "err(%d)\n", ino, err);
375 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
376 if (err != HV_EOK)
377 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
378 ino, err);
379 }
380
381 static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
382 {
383 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
384 unsigned long cpuid = irq_choose_cpu(virt_irq);
385 int err;
386
387 err = sun4v_intr_settarget(ino, cpuid);
388 if (err != HV_EOK)
389 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
390 "err(%d)\n", ino, cpuid, err);
391 }
392
393 static void sun4v_irq_disable(unsigned int virt_irq)
394 {
395 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
396 int err;
397
398 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
399 if (err != HV_EOK)
400 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
401 "err(%d)\n", ino, err);
402 }
403
404 static void sun4v_irq_end(unsigned int virt_irq)
405 {
406 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
407 struct irq_desc *desc = irq_desc + virt_irq;
408 int err;
409
410 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
411 return;
412
413 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
414 if (err != HV_EOK)
415 printk(KERN_ERR "sun4v_intr_setstate(%x): "
416 "err(%d)\n", ino, err);
417 }
418
419 static void sun4v_virq_enable(unsigned int virt_irq)
420 {
421 unsigned long cpuid, dev_handle, dev_ino;
422 int err;
423
424 cpuid = irq_choose_cpu(virt_irq);
425
426 dev_handle = virt_irq_table[virt_irq].dev_handle;
427 dev_ino = virt_irq_table[virt_irq].dev_ino;
428
429 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
430 if (err != HV_EOK)
431 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
432 "err(%d)\n",
433 dev_handle, dev_ino, cpuid, err);
434 err = sun4v_vintr_set_state(dev_handle, dev_ino,
435 HV_INTR_STATE_IDLE);
436 if (err != HV_EOK)
437 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
438 "HV_INTR_STATE_IDLE): err(%d)\n",
439 dev_handle, dev_ino, err);
440 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
441 HV_INTR_ENABLED);
442 if (err != HV_EOK)
443 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
444 "HV_INTR_ENABLED): err(%d)\n",
445 dev_handle, dev_ino, err);
446 }
447
448 static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
449 {
450 unsigned long cpuid, dev_handle, dev_ino;
451 int err;
452
453 cpuid = irq_choose_cpu(virt_irq);
454
455 dev_handle = virt_irq_table[virt_irq].dev_handle;
456 dev_ino = virt_irq_table[virt_irq].dev_ino;
457
458 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
459 if (err != HV_EOK)
460 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
461 "err(%d)\n",
462 dev_handle, dev_ino, cpuid, err);
463 }
464
465 static void sun4v_virq_disable(unsigned int virt_irq)
466 {
467 unsigned long dev_handle, dev_ino;
468 int err;
469
470 dev_handle = virt_irq_table[virt_irq].dev_handle;
471 dev_ino = virt_irq_table[virt_irq].dev_ino;
472
473 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
474 HV_INTR_DISABLED);
475 if (err != HV_EOK)
476 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
477 "HV_INTR_DISABLED): err(%d)\n",
478 dev_handle, dev_ino, err);
479 }
480
481 static void sun4v_virq_end(unsigned int virt_irq)
482 {
483 struct irq_desc *desc = irq_desc + virt_irq;
484 unsigned long dev_handle, dev_ino;
485 int err;
486
487 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
488 return;
489
490 dev_handle = virt_irq_table[virt_irq].dev_handle;
491 dev_ino = virt_irq_table[virt_irq].dev_ino;
492
493 err = sun4v_vintr_set_state(dev_handle, dev_ino,
494 HV_INTR_STATE_IDLE);
495 if (err != HV_EOK)
496 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
497 "HV_INTR_STATE_IDLE): err(%d)\n",
498 dev_handle, dev_ino, err);
499 }
500
501 static void run_pre_handler(unsigned int virt_irq)
502 {
503 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
504 unsigned int ino;
505
506 ino = virt_irq_table[virt_irq].dev_ino;
507 if (likely(data->pre_handler)) {
508 data->pre_handler(ino,
509 data->pre_handler_arg1,
510 data->pre_handler_arg2);
511 }
512 }
513
514 static struct irq_chip sun4u_irq = {
515 .typename = "sun4u",
516 .enable = sun4u_irq_enable,
517 .disable = sun4u_irq_disable,
518 .end = sun4u_irq_end,
519 .set_affinity = sun4u_set_affinity,
520 };
521
522 static struct irq_chip sun4u_irq_ack = {
523 .typename = "sun4u+ack",
524 .enable = sun4u_irq_enable,
525 .disable = sun4u_irq_disable,
526 .ack = run_pre_handler,
527 .end = sun4u_irq_end,
528 .set_affinity = sun4u_set_affinity,
529 };
530
531 static struct irq_chip sun4v_irq = {
532 .typename = "sun4v",
533 .enable = sun4v_irq_enable,
534 .disable = sun4v_irq_disable,
535 .end = sun4v_irq_end,
536 .set_affinity = sun4v_set_affinity,
537 };
538
539 static struct irq_chip sun4v_virq = {
540 .typename = "vsun4v",
541 .enable = sun4v_virq_enable,
542 .disable = sun4v_virq_disable,
543 .end = sun4v_virq_end,
544 .set_affinity = sun4v_virt_set_affinity,
545 };
546
547 void irq_install_pre_handler(int virt_irq,
548 void (*func)(unsigned int, void *, void *),
549 void *arg1, void *arg2)
550 {
551 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
552 struct irq_chip *chip = get_irq_chip(virt_irq);
553
554 if (WARN_ON(chip == &sun4v_irq || chip == &sun4v_virq)) {
555 printk(KERN_ERR "IRQ: Trying to install pre-handler on "
556 "sun4v irq %u\n", virt_irq);
557 return;
558 }
559
560 data->pre_handler = func;
561 data->pre_handler_arg1 = arg1;
562 data->pre_handler_arg2 = arg2;
563
564 if (chip == &sun4u_irq_ack)
565 return;
566
567 set_irq_chip(virt_irq, &sun4u_irq_ack);
568 }
569
570 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
571 {
572 struct ino_bucket *bucket;
573 struct irq_handler_data *data;
574 unsigned int virt_irq;
575 int ino;
576
577 BUG_ON(tlb_type == hypervisor);
578
579 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
580 bucket = &ivector_table[ino];
581 virt_irq = bucket_get_virt_irq(__pa(bucket));
582 if (!virt_irq) {
583 virt_irq = virt_irq_alloc(0, ino);
584 bucket_set_virt_irq(__pa(bucket), virt_irq);
585 set_irq_chip(virt_irq, &sun4u_irq);
586 }
587
588 data = get_irq_chip_data(virt_irq);
589 if (unlikely(data))
590 goto out;
591
592 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
593 if (unlikely(!data)) {
594 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
595 prom_halt();
596 }
597 set_irq_chip_data(virt_irq, data);
598
599 data->imap = imap;
600 data->iclr = iclr;
601
602 out:
603 return virt_irq;
604 }
605
606 static unsigned int sun4v_build_common(unsigned long sysino,
607 struct irq_chip *chip)
608 {
609 struct ino_bucket *bucket;
610 struct irq_handler_data *data;
611 unsigned int virt_irq;
612
613 BUG_ON(tlb_type != hypervisor);
614
615 bucket = &ivector_table[sysino];
616 virt_irq = bucket_get_virt_irq(__pa(bucket));
617 if (!virt_irq) {
618 virt_irq = virt_irq_alloc(0, sysino);
619 bucket_set_virt_irq(__pa(bucket), virt_irq);
620 set_irq_chip(virt_irq, chip);
621 }
622
623 data = get_irq_chip_data(virt_irq);
624 if (unlikely(data))
625 goto out;
626
627 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
628 if (unlikely(!data)) {
629 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
630 prom_halt();
631 }
632 set_irq_chip_data(virt_irq, data);
633
634 /* Catch accidental accesses to these things. IMAP/ICLR handling
635 * is done by hypervisor calls on sun4v platforms, not by direct
636 * register accesses.
637 */
638 data->imap = ~0UL;
639 data->iclr = ~0UL;
640
641 out:
642 return virt_irq;
643 }
644
645 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
646 {
647 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
648
649 return sun4v_build_common(sysino, &sun4v_irq);
650 }
651
652 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
653 {
654 struct irq_handler_data *data;
655 struct ino_bucket *bucket;
656 unsigned long hv_err, cookie;
657 unsigned int virt_irq;
658
659 bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
660 if (unlikely(!bucket))
661 return 0;
662 __flush_dcache_range((unsigned long) bucket,
663 ((unsigned long) bucket +
664 sizeof(struct ino_bucket)));
665
666 virt_irq = virt_irq_alloc(devhandle, devino);
667 bucket_set_virt_irq(__pa(bucket), virt_irq);
668 set_irq_chip(virt_irq, &sun4v_virq);
669
670 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
671 if (unlikely(!data))
672 return 0;
673
674 set_irq_chip_data(virt_irq, data);
675
676 /* Catch accidental accesses to these things. IMAP/ICLR handling
677 * is done by hypervisor calls on sun4v platforms, not by direct
678 * register accesses.
679 */
680 data->imap = ~0UL;
681 data->iclr = ~0UL;
682
683 cookie = ~__pa(bucket);
684 hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
685 if (hv_err) {
686 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
687 "err=%lu\n", devhandle, devino, hv_err);
688 prom_halt();
689 }
690
691 return virt_irq;
692 }
693
694 void ack_bad_irq(unsigned int virt_irq)
695 {
696 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
697
698 if (!ino)
699 ino = 0xdeadbeef;
700
701 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
702 ino, virt_irq);
703 }
704
705 void handler_irq(int irq, struct pt_regs *regs)
706 {
707 unsigned long pstate, bucket_pa;
708 struct pt_regs *old_regs;
709
710 clear_softint(1 << irq);
711
712 old_regs = set_irq_regs(regs);
713 irq_enter();
714
715 /* Grab an atomic snapshot of the pending IVECs. */
716 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
717 "wrpr %0, %3, %%pstate\n\t"
718 "ldx [%2], %1\n\t"
719 "stx %%g0, [%2]\n\t"
720 "wrpr %0, 0x0, %%pstate\n\t"
721 : "=&r" (pstate), "=&r" (bucket_pa)
722 : "r" (irq_work_pa(smp_processor_id())),
723 "i" (PSTATE_IE)
724 : "memory");
725
726 while (bucket_pa) {
727 unsigned long next_pa;
728 unsigned int virt_irq;
729
730 next_pa = bucket_get_chain_pa(bucket_pa);
731 virt_irq = bucket_get_virt_irq(bucket_pa);
732 bucket_clear_chain_pa(bucket_pa);
733
734 __do_IRQ(virt_irq);
735
736 bucket_pa = next_pa;
737 }
738
739 irq_exit();
740 set_irq_regs(old_regs);
741 }
742
743 #ifdef CONFIG_HOTPLUG_CPU
744 void fixup_irqs(void)
745 {
746 unsigned int irq;
747
748 for (irq = 0; irq < NR_IRQS; irq++) {
749 unsigned long flags;
750
751 spin_lock_irqsave(&irq_desc[irq].lock, flags);
752 if (irq_desc[irq].action &&
753 !(irq_desc[irq].status & IRQ_PER_CPU)) {
754 if (irq_desc[irq].chip->set_affinity)
755 irq_desc[irq].chip->set_affinity(irq,
756 irq_desc[irq].affinity);
757 }
758 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
759 }
760 }
761 #endif
762
763 struct sun5_timer {
764 u64 count0;
765 u64 limit0;
766 u64 count1;
767 u64 limit1;
768 };
769
770 static struct sun5_timer *prom_timers;
771 static u64 prom_limit0, prom_limit1;
772
773 static void map_prom_timers(void)
774 {
775 struct device_node *dp;
776 const unsigned int *addr;
777
778 /* PROM timer node hangs out in the top level of device siblings... */
779 dp = of_find_node_by_path("/");
780 dp = dp->child;
781 while (dp) {
782 if (!strcmp(dp->name, "counter-timer"))
783 break;
784 dp = dp->sibling;
785 }
786
787 /* Assume if node is not present, PROM uses different tick mechanism
788 * which we should not care about.
789 */
790 if (!dp) {
791 prom_timers = (struct sun5_timer *) 0;
792 return;
793 }
794
795 /* If PROM is really using this, it must be mapped by him. */
796 addr = of_get_property(dp, "address", NULL);
797 if (!addr) {
798 prom_printf("PROM does not have timer mapped, trying to continue.\n");
799 prom_timers = (struct sun5_timer *) 0;
800 return;
801 }
802 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
803 }
804
805 static void kill_prom_timer(void)
806 {
807 if (!prom_timers)
808 return;
809
810 /* Save them away for later. */
811 prom_limit0 = prom_timers->limit0;
812 prom_limit1 = prom_timers->limit1;
813
814 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
815 * We turn both off here just to be paranoid.
816 */
817 prom_timers->limit0 = 0;
818 prom_timers->limit1 = 0;
819
820 /* Wheee, eat the interrupt packet too... */
821 __asm__ __volatile__(
822 " mov 0x40, %%g2\n"
823 " ldxa [%%g0] %0, %%g1\n"
824 " ldxa [%%g2] %1, %%g1\n"
825 " stxa %%g0, [%%g0] %0\n"
826 " membar #Sync\n"
827 : /* no outputs */
828 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
829 : "g1", "g2");
830 }
831
832 void init_irqwork_curcpu(void)
833 {
834 int cpu = hard_smp_processor_id();
835
836 trap_block[cpu].irq_worklist_pa = 0UL;
837 }
838
839 /* Please be very careful with register_one_mondo() and
840 * sun4v_register_mondo_queues().
841 *
842 * On SMP this gets invoked from the CPU trampoline before
843 * the cpu has fully taken over the trap table from OBP,
844 * and it's kernel stack + %g6 thread register state is
845 * not fully cooked yet.
846 *
847 * Therefore you cannot make any OBP calls, not even prom_printf,
848 * from these two routines.
849 */
850 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
851 {
852 unsigned long num_entries = (qmask + 1) / 64;
853 unsigned long status;
854
855 status = sun4v_cpu_qconf(type, paddr, num_entries);
856 if (status != HV_EOK) {
857 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
858 "err %lu\n", type, paddr, num_entries, status);
859 prom_halt();
860 }
861 }
862
863 void __cpuinit sun4v_register_mondo_queues(int this_cpu)
864 {
865 struct trap_per_cpu *tb = &trap_block[this_cpu];
866
867 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
868 tb->cpu_mondo_qmask);
869 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
870 tb->dev_mondo_qmask);
871 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
872 tb->resum_qmask);
873 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
874 tb->nonresum_qmask);
875 }
876
877 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
878 {
879 unsigned long size = PAGE_ALIGN(qmask + 1);
880 void *p = __alloc_bootmem_low(size, size, 0);
881 if (!p) {
882 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
883 prom_halt();
884 }
885
886 *pa_ptr = __pa(p);
887 }
888
889 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
890 {
891 unsigned long size = PAGE_ALIGN(qmask + 1);
892 void *p = __alloc_bootmem_low(size, size, 0);
893
894 if (!p) {
895 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
896 prom_halt();
897 }
898
899 *pa_ptr = __pa(p);
900 }
901
902 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
903 {
904 #ifdef CONFIG_SMP
905 void *page;
906
907 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
908
909 page = alloc_bootmem_low_pages(PAGE_SIZE);
910 if (!page) {
911 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
912 prom_halt();
913 }
914
915 tb->cpu_mondo_block_pa = __pa(page);
916 tb->cpu_list_pa = __pa(page + 64);
917 #endif
918 }
919
920 /* Allocate mondo and error queues for all possible cpus. */
921 static void __init sun4v_init_mondo_queues(void)
922 {
923 int cpu;
924
925 for_each_possible_cpu(cpu) {
926 struct trap_per_cpu *tb = &trap_block[cpu];
927
928 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
929 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
930 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
931 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
932 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
933 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
934 tb->nonresum_qmask);
935
936 init_cpu_send_mondo_info(tb);
937 }
938
939 /* Load up the boot cpu's entries. */
940 sun4v_register_mondo_queues(hard_smp_processor_id());
941 }
942
943 static struct irqaction timer_irq_action = {
944 .name = "timer",
945 };
946
947 /* Only invoked on boot processor. */
948 void __init init_IRQ(void)
949 {
950 unsigned long size;
951
952 map_prom_timers();
953 kill_prom_timer();
954
955 size = sizeof(struct ino_bucket) * NUM_IVECS;
956 ivector_table = alloc_bootmem_low(size);
957 if (!ivector_table) {
958 prom_printf("Fatal error, cannot allocate ivector_table\n");
959 prom_halt();
960 }
961 __flush_dcache_range((unsigned long) ivector_table,
962 ((unsigned long) ivector_table) + size);
963
964 ivector_table_pa = __pa(ivector_table);
965
966 if (tlb_type == hypervisor)
967 sun4v_init_mondo_queues();
968
969 /* We need to clear any IRQ's pending in the soft interrupt
970 * registers, a spurious one could be left around from the
971 * PROM timer which we just disabled.
972 */
973 clear_softint(get_softint());
974
975 /* Now that ivector table is initialized, it is safe
976 * to receive IRQ vector traps. We will normally take
977 * one or two right now, in case some device PROM used
978 * to boot us wants to speak to us. We just ignore them.
979 */
980 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
981 "or %%g1, %0, %%g1\n\t"
982 "wrpr %%g1, 0x0, %%pstate"
983 : /* No outputs */
984 : "i" (PSTATE_IE)
985 : "g1");
986
987 irq_desc[0].action = &timer_irq_action;
988 }
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