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[ALSA] cs4231-lib: replace common delay loop by function
[linux-2.6/verdex.git] / arch / sparc64 / kernel / pci.c
blob9b808640a193d5c941cbb2dd16e4ec5bbffb465a
1 /* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21
22 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
24 #include <asm/irq.h>
25 #include <asm/ebus.h>
26 #include <asm/isa.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29
30 #include "pci_impl.h"
31
32 #ifndef CONFIG_PCI
33 /* A "nop" PCI implementation. */
34 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
35 unsigned long off, unsigned long len,
36 unsigned char *buf)
37 {
38 return 0;
39 }
40 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
41 unsigned long off, unsigned long len,
42 unsigned char *buf)
43 {
44 return 0;
45 }
46 #else
47
48 /* List of all PCI controllers found in the system. */
49 struct pci_pbm_info *pci_pbm_root = NULL;
50
51 /* Each PBM found gets a unique index. */
52 int pci_num_pbms = 0;
53
54 volatile int pci_poke_in_progress;
55 volatile int pci_poke_cpu = -1;
56 volatile int pci_poke_faulted;
57
58 static DEFINE_SPINLOCK(pci_poke_lock);
59
60 void pci_config_read8(u8 *addr, u8 *ret)
61 {
62 unsigned long flags;
63 u8 byte;
64
65 spin_lock_irqsave(&pci_poke_lock, flags);
66 pci_poke_cpu = smp_processor_id();
67 pci_poke_in_progress = 1;
68 pci_poke_faulted = 0;
69 __asm__ __volatile__("membar #Sync\n\t"
70 "lduba [%1] %2, %0\n\t"
71 "membar #Sync"
72 : "=r" (byte)
73 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
74 : "memory");
75 pci_poke_in_progress = 0;
76 pci_poke_cpu = -1;
77 if (!pci_poke_faulted)
78 *ret = byte;
79 spin_unlock_irqrestore(&pci_poke_lock, flags);
80 }
81
82 void pci_config_read16(u16 *addr, u16 *ret)
83 {
84 unsigned long flags;
85 u16 word;
86
87 spin_lock_irqsave(&pci_poke_lock, flags);
88 pci_poke_cpu = smp_processor_id();
89 pci_poke_in_progress = 1;
90 pci_poke_faulted = 0;
91 __asm__ __volatile__("membar #Sync\n\t"
92 "lduha [%1] %2, %0\n\t"
93 "membar #Sync"
94 : "=r" (word)
95 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
96 : "memory");
97 pci_poke_in_progress = 0;
98 pci_poke_cpu = -1;
99 if (!pci_poke_faulted)
100 *ret = word;
101 spin_unlock_irqrestore(&pci_poke_lock, flags);
102 }
103
104 void pci_config_read32(u32 *addr, u32 *ret)
105 {
106 unsigned long flags;
107 u32 dword;
108
109 spin_lock_irqsave(&pci_poke_lock, flags);
110 pci_poke_cpu = smp_processor_id();
111 pci_poke_in_progress = 1;
112 pci_poke_faulted = 0;
113 __asm__ __volatile__("membar #Sync\n\t"
114 "lduwa [%1] %2, %0\n\t"
115 "membar #Sync"
116 : "=r" (dword)
117 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
118 : "memory");
119 pci_poke_in_progress = 0;
120 pci_poke_cpu = -1;
121 if (!pci_poke_faulted)
122 *ret = dword;
123 spin_unlock_irqrestore(&pci_poke_lock, flags);
124 }
125
126 void pci_config_write8(u8 *addr, u8 val)
127 {
128 unsigned long flags;
129
130 spin_lock_irqsave(&pci_poke_lock, flags);
131 pci_poke_cpu = smp_processor_id();
132 pci_poke_in_progress = 1;
133 pci_poke_faulted = 0;
134 __asm__ __volatile__("membar #Sync\n\t"
135 "stba %0, [%1] %2\n\t"
136 "membar #Sync"
137 : /* no outputs */
138 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
139 : "memory");
140 pci_poke_in_progress = 0;
141 pci_poke_cpu = -1;
142 spin_unlock_irqrestore(&pci_poke_lock, flags);
143 }
144
145 void pci_config_write16(u16 *addr, u16 val)
146 {
147 unsigned long flags;
148
149 spin_lock_irqsave(&pci_poke_lock, flags);
150 pci_poke_cpu = smp_processor_id();
151 pci_poke_in_progress = 1;
152 pci_poke_faulted = 0;
153 __asm__ __volatile__("membar #Sync\n\t"
154 "stha %0, [%1] %2\n\t"
155 "membar #Sync"
156 : /* no outputs */
157 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
158 : "memory");
159 pci_poke_in_progress = 0;
160 pci_poke_cpu = -1;
161 spin_unlock_irqrestore(&pci_poke_lock, flags);
162 }
163
164 void pci_config_write32(u32 *addr, u32 val)
165 {
166 unsigned long flags;
167
168 spin_lock_irqsave(&pci_poke_lock, flags);
169 pci_poke_cpu = smp_processor_id();
170 pci_poke_in_progress = 1;
171 pci_poke_faulted = 0;
172 __asm__ __volatile__("membar #Sync\n\t"
173 "stwa %0, [%1] %2\n\t"
174 "membar #Sync"
175 : /* no outputs */
176 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
177 : "memory");
178 pci_poke_in_progress = 0;
179 pci_poke_cpu = -1;
180 spin_unlock_irqrestore(&pci_poke_lock, flags);
181 }
182
183 /* Probe for all PCI controllers in the system. */
184 extern void sabre_init(struct device_node *, const char *);
185 extern void psycho_init(struct device_node *, const char *);
186 extern void schizo_init(struct device_node *, const char *);
187 extern void schizo_plus_init(struct device_node *, const char *);
188 extern void tomatillo_init(struct device_node *, const char *);
189 extern void sun4v_pci_init(struct device_node *, const char *);
190 extern void fire_pci_init(struct device_node *, const char *);
191
192 static struct {
193 char *model_name;
194 void (*init)(struct device_node *, const char *);
195 } pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
207 { "SUNW,sun4v-pci", sun4v_pci_init },
208 { "pciex108e,80f0", fire_pci_init },
209 };
210 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
211 sizeof(pci_controller_table[0]))
212
213 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
214 {
215 int i;
216
217 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
218 if (!strncmp(model_name,
219 pci_controller_table[i].model_name,
220 namelen)) {
221 pci_controller_table[i].init(dp, model_name);
222 return 1;
223 }
224 }
225
226 return 0;
227 }
228
229 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
230 {
231 int i;
232
233 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
234 if (!strncmp(model_name,
235 pci_controller_table[i].model_name,
236 namelen)) {
237 return 1;
238 }
239 }
240 return 0;
241 }
242
243 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
244 {
245 struct device_node *dp;
246 int count = 0;
247
248 for_each_node_by_name(dp, "pci") {
249 struct property *prop;
250 int len;
251
252 prop = of_find_property(dp, "model", &len);
253 if (!prop)
254 prop = of_find_property(dp, "compatible", &len);
255
256 if (prop) {
257 const char *model = prop->value;
258 int item_len = 0;
259
260 /* Our value may be a multi-valued string in the
261 * case of some compatible properties. For sanity,
262 * only try the first one.
263 */
264 while (model[item_len] && len) {
265 len--;
266 item_len++;
267 }
268
269 if (handler(model, item_len, dp))
270 count++;
271 }
272 }
273
274 return count;
275 }
276
277
278 /* Is there some PCI controller in the system? */
279 int __init pcic_present(void)
280 {
281 return pci_controller_scan(pci_is_controller);
282 }
283
284 /* Find each controller in the system, attach and initialize
285 * software state structure for each and link into the
286 * pci_pbm_root. Setup the controller enough such
287 * that bus scanning can be done.
288 */
289 static void __init pci_controller_probe(void)
290 {
291 printk("PCI: Probing for controllers.\n");
292
293 pci_controller_scan(pci_controller_init);
294 }
295
296 static int ofpci_verbose;
297
298 static int __init ofpci_debug(char *str)
299 {
300 int val = 0;
301
302 get_option(&str, &val);
303 if (val)
304 ofpci_verbose = 1;
305 return 1;
306 }
307
308 __setup("ofpci_debug=", ofpci_debug);
309
310 static unsigned long pci_parse_of_flags(u32 addr0)
311 {
312 unsigned long flags = 0;
313
314 if (addr0 & 0x02000000) {
315 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
316 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
317 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
318 if (addr0 & 0x40000000)
319 flags |= IORESOURCE_PREFETCH
320 | PCI_BASE_ADDRESS_MEM_PREFETCH;
321 } else if (addr0 & 0x01000000)
322 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
323 return flags;
324 }
325
326 /* The of_device layer has translated all of the assigned-address properties
327 * into physical address resources, we only have to figure out the register
328 * mapping.
329 */
330 static void pci_parse_of_addrs(struct of_device *op,
331 struct device_node *node,
332 struct pci_dev *dev)
333 {
334 struct resource *op_res;
335 const u32 *addrs;
336 int proplen;
337
338 addrs = of_get_property(node, "assigned-addresses", &proplen);
339 if (!addrs)
340 return;
341 if (ofpci_verbose)
342 printk(" parse addresses (%d bytes) @ %p\n",
343 proplen, addrs);
344 op_res = &op->resource[0];
345 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
346 struct resource *res;
347 unsigned long flags;
348 int i;
349
350 flags = pci_parse_of_flags(addrs[0]);
351 if (!flags)
352 continue;
353 i = addrs[0] & 0xff;
354 if (ofpci_verbose)
355 printk(" start: %lx, end: %lx, i: %x\n",
356 op_res->start, op_res->end, i);
357
358 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
359 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
360 } else if (i == dev->rom_base_reg) {
361 res = &dev->resource[PCI_ROM_RESOURCE];
362 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
363 } else {
364 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
365 continue;
366 }
367 res->start = op_res->start;
368 res->end = op_res->end;
369 res->flags = flags;
370 res->name = pci_name(dev);
371 }
372 }
373
374 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
375 struct device_node *node,
376 struct pci_bus *bus, int devfn,
377 int host_controller)
378 {
379 struct dev_archdata *sd;
380 struct pci_dev *dev;
381 const char *type;
382 u32 class;
383
384 dev = alloc_pci_dev();
385 if (!dev)
386 return NULL;
387
388 sd = &dev->dev.archdata;
389 sd->iommu = pbm->iommu;
390 sd->stc = &pbm->stc;
391 sd->host_controller = pbm;
392 sd->prom_node = node;
393 sd->op = of_find_device_by_node(node);
394
395 sd = &sd->op->dev.archdata;
396 sd->iommu = pbm->iommu;
397 sd->stc = &pbm->stc;
398
399 type = of_get_property(node, "device_type", NULL);
400 if (type == NULL)
401 type = "";
402
403 if (ofpci_verbose)
404 printk(" create device, devfn: %x, type: %s\n",
405 devfn, type);
406
407 dev->bus = bus;
408 dev->sysdata = node;
409 dev->dev.parent = bus->bridge;
410 dev->dev.bus = &pci_bus_type;
411 dev->devfn = devfn;
412 dev->multifunction = 0; /* maybe a lie? */
413
414 if (host_controller) {
415 if (tlb_type != hypervisor) {
416 pci_read_config_word(dev, PCI_VENDOR_ID,
417 &dev->vendor);
418 pci_read_config_word(dev, PCI_DEVICE_ID,
419 &dev->device);
420 } else {
421 dev->vendor = PCI_VENDOR_ID_SUN;
422 dev->device = 0x80f0;
423 }
424 dev->cfg_size = 256;
425 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
426 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
427 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
428 } else {
429 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
430 dev->device = of_getintprop_default(node, "device-id", 0xffff);
431 dev->subsystem_vendor =
432 of_getintprop_default(node, "subsystem-vendor-id", 0);
433 dev->subsystem_device =
434 of_getintprop_default(node, "subsystem-id", 0);
435
436 dev->cfg_size = pci_cfg_space_size(dev);
437
438 /* We can't actually use the firmware value, we have
439 * to read what is in the register right now. One
440 * reason is that in the case of IDE interfaces the
441 * firmware can sample the value before the the IDE
442 * interface is programmed into native mode.
443 */
444 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
445 dev->class = class >> 8;
446 dev->revision = class & 0xff;
447
448 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
449 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
450 }
451 if (ofpci_verbose)
452 printk(" class: 0x%x device name: %s\n",
453 dev->class, pci_name(dev));
454
455 /* I have seen IDE devices which will not respond to
456 * the bmdma simplex check reads if bus mastering is
457 * disabled.
458 */
459 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
460 pci_set_master(dev);
461
462 dev->current_state = 4; /* unknown power state */
463 dev->error_state = pci_channel_io_normal;
464
465 if (host_controller) {
466 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
467 dev->rom_base_reg = PCI_ROM_ADDRESS1;
468 dev->irq = PCI_IRQ_NONE;
469 } else {
470 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
471 /* a PCI-PCI bridge */
472 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
473 dev->rom_base_reg = PCI_ROM_ADDRESS1;
474 } else if (!strcmp(type, "cardbus")) {
475 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
476 } else {
477 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
478 dev->rom_base_reg = PCI_ROM_ADDRESS;
479
480 dev->irq = sd->op->irqs[0];
481 if (dev->irq == 0xffffffff)
482 dev->irq = PCI_IRQ_NONE;
483 }
484 }
485 pci_parse_of_addrs(sd->op, node, dev);
486
487 if (ofpci_verbose)
488 printk(" adding to system ...\n");
489
490 pci_device_add(dev, bus);
491
492 return dev;
493 }
494
495 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
496 {
497 u32 idx, first, last;
498
499 first = 8;
500 last = 0;
501 for (idx = 0; idx < 8; idx++) {
502 if ((map & (1 << idx)) != 0) {
503 if (first > idx)
504 first = idx;
505 if (last < idx)
506 last = idx;
507 }
508 }
509
510 *first_p = first;
511 *last_p = last;
512 }
513
514 static void pci_resource_adjust(struct resource *res,
515 struct resource *root)
516 {
517 res->start += root->start;
518 res->end += root->start;
519 }
520
521 /* For PCI bus devices which lack a 'ranges' property we interrogate
522 * the config space values to set the resources, just like the generic
523 * Linux PCI probing code does.
524 */
525 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
526 struct pci_bus *bus,
527 struct pci_pbm_info *pbm)
528 {
529 struct resource *res;
530 u8 io_base_lo, io_limit_lo;
531 u16 mem_base_lo, mem_limit_lo;
532 unsigned long base, limit;
533
534 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
535 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
536 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
537 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
538
539 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
540 u16 io_base_hi, io_limit_hi;
541
542 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
543 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
544 base |= (io_base_hi << 16);
545 limit |= (io_limit_hi << 16);
546 }
547
548 res = bus->resource[0];
549 if (base <= limit) {
550 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
551 if (!res->start)
552 res->start = base;
553 if (!res->end)
554 res->end = limit + 0xfff;
555 pci_resource_adjust(res, &pbm->io_space);
556 }
557
558 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
559 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
560 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
561 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
562
563 res = bus->resource[1];
564 if (base <= limit) {
565 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
566 IORESOURCE_MEM);
567 res->start = base;
568 res->end = limit + 0xfffff;
569 pci_resource_adjust(res, &pbm->mem_space);
570 }
571
572 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
573 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
574 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
575 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
576
577 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
578 u32 mem_base_hi, mem_limit_hi;
579
580 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
581 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
582
583 /*
584 * Some bridges set the base > limit by default, and some
585 * (broken) BIOSes do not initialize them. If we find
586 * this, just assume they are not being used.
587 */
588 if (mem_base_hi <= mem_limit_hi) {
589 base |= ((long) mem_base_hi) << 32;
590 limit |= ((long) mem_limit_hi) << 32;
591 }
592 }
593
594 res = bus->resource[2];
595 if (base <= limit) {
596 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
597 IORESOURCE_MEM | IORESOURCE_PREFETCH);
598 res->start = base;
599 res->end = limit + 0xfffff;
600 pci_resource_adjust(res, &pbm->mem_space);
601 }
602 }
603
604 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
605 * a proper 'ranges' property.
606 */
607 static void __devinit apb_fake_ranges(struct pci_dev *dev,
608 struct pci_bus *bus,
609 struct pci_pbm_info *pbm)
610 {
611 struct resource *res;
612 u32 first, last;
613 u8 map;
614
615 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
616 apb_calc_first_last(map, &first, &last);
617 res = bus->resource[0];
618 res->start = (first << 21);
619 res->end = (last << 21) + ((1 << 21) - 1);
620 res->flags = IORESOURCE_IO;
621 pci_resource_adjust(res, &pbm->io_space);
622
623 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
624 apb_calc_first_last(map, &first, &last);
625 res = bus->resource[1];
626 res->start = (first << 21);
627 res->end = (last << 21) + ((1 << 21) - 1);
628 res->flags = IORESOURCE_MEM;
629 pci_resource_adjust(res, &pbm->mem_space);
630 }
631
632 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
633 struct device_node *node,
634 struct pci_bus *bus);
635
636 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
637
638 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
639 struct device_node *node,
640 struct pci_dev *dev)
641 {
642 struct pci_bus *bus;
643 const u32 *busrange, *ranges;
644 int len, i, simba;
645 struct resource *res;
646 unsigned int flags;
647 u64 size;
648
649 if (ofpci_verbose)
650 printk("of_scan_pci_bridge(%s)\n", node->full_name);
651
652 /* parse bus-range property */
653 busrange = of_get_property(node, "bus-range", &len);
654 if (busrange == NULL || len != 8) {
655 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
656 node->full_name);
657 return;
658 }
659 ranges = of_get_property(node, "ranges", &len);
660 simba = 0;
661 if (ranges == NULL) {
662 const char *model = of_get_property(node, "model", NULL);
663 if (model && !strcmp(model, "SUNW,simba"))
664 simba = 1;
665 }
666
667 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
668 if (!bus) {
669 printk(KERN_ERR "Failed to create pci bus for %s\n",
670 node->full_name);
671 return;
672 }
673
674 bus->primary = dev->bus->number;
675 bus->subordinate = busrange[1];
676 bus->bridge_ctl = 0;
677
678 /* parse ranges property, or cook one up by hand for Simba */
679 /* PCI #address-cells == 3 and #size-cells == 2 always */
680 res = &dev->resource[PCI_BRIDGE_RESOURCES];
681 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
682 res->flags = 0;
683 bus->resource[i] = res;
684 ++res;
685 }
686 if (simba) {
687 apb_fake_ranges(dev, bus, pbm);
688 goto after_ranges;
689 } else if (ranges == NULL) {
690 pci_cfg_fake_ranges(dev, bus, pbm);
691 goto after_ranges;
692 }
693 i = 1;
694 for (; len >= 32; len -= 32, ranges += 8) {
695 struct resource *root;
696
697 flags = pci_parse_of_flags(ranges[0]);
698 size = GET_64BIT(ranges, 6);
699 if (flags == 0 || size == 0)
700 continue;
701 if (flags & IORESOURCE_IO) {
702 res = bus->resource[0];
703 if (res->flags) {
704 printk(KERN_ERR "PCI: ignoring extra I/O range"
705 " for bridge %s\n", node->full_name);
706 continue;
707 }
708 root = &pbm->io_space;
709 } else {
710 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
711 printk(KERN_ERR "PCI: too many memory ranges"
712 " for bridge %s\n", node->full_name);
713 continue;
714 }
715 res = bus->resource[i];
716 ++i;
717 root = &pbm->mem_space;
718 }
719
720 res->start = GET_64BIT(ranges, 1);
721 res->end = res->start + size - 1;
722 res->flags = flags;
723
724 /* Another way to implement this would be to add an of_device
725 * layer routine that can calculate a resource for a given
726 * range property value in a PCI device.
727 */
728 pci_resource_adjust(res, root);
729 }
730 after_ranges:
731 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
732 bus->number);
733 if (ofpci_verbose)
734 printk(" bus name: %s\n", bus->name);
735
736 pci_of_scan_bus(pbm, node, bus);
737 }
738
739 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
740 struct device_node *node,
741 struct pci_bus *bus)
742 {
743 struct device_node *child;
744 const u32 *reg;
745 int reglen, devfn, prev_devfn;
746 struct pci_dev *dev;
747
748 if (ofpci_verbose)
749 printk("PCI: scan_bus[%s] bus no %d\n",
750 node->full_name, bus->number);
751
752 child = NULL;
753 prev_devfn = -1;
754 while ((child = of_get_next_child(node, child)) != NULL) {
755 if (ofpci_verbose)
756 printk(" * %s\n", child->full_name);
757 reg = of_get_property(child, "reg", &reglen);
758 if (reg == NULL || reglen < 20)
759 continue;
760
761 devfn = (reg[0] >> 8) & 0xff;
762
763 /* This is a workaround for some device trees
764 * which list PCI devices twice. On the V100
765 * for example, device number 3 is listed twice.
766 * Once as "pm" and once again as "lomp".
767 */
768 if (devfn == prev_devfn)
769 continue;
770 prev_devfn = devfn;
771
772 /* create a new pci_dev for this device */
773 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
774 if (!dev)
775 continue;
776 if (ofpci_verbose)
777 printk("PCI: dev header type: %x\n",
778 dev->hdr_type);
779
780 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
781 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
782 of_scan_pci_bridge(pbm, child, dev);
783 }
784 }
785
786 static ssize_t
787 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
788 {
789 struct pci_dev *pdev;
790 struct device_node *dp;
791
792 pdev = to_pci_dev(dev);
793 dp = pdev->dev.archdata.prom_node;
794
795 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
796 }
797
798 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
799
800 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
801 {
802 struct pci_dev *dev;
803 struct pci_bus *child_bus;
804 int err;
805
806 list_for_each_entry(dev, &bus->devices, bus_list) {
807 /* we don't really care if we can create this file or
808 * not, but we need to assign the result of the call
809 * or the world will fall under alien invasion and
810 * everybody will be frozen on a spaceship ready to be
811 * eaten on alpha centauri by some green and jelly
812 * humanoid.
813 */
814 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
815 }
816 list_for_each_entry(child_bus, &bus->children, node)
817 pci_bus_register_of_sysfs(child_bus);
818 }
819
820 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
821 unsigned int devfn,
822 int where, int size,
823 u32 *value)
824 {
825 static u8 fake_pci_config[] = {
826 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
827 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
828 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
829 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
830 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
831 0x00, /* Cacheline: 0x00 */
832 0x40, /* Latency: 0x40 */
833 0x00, /* Header-Type: 0x00 normal */
834 };
835
836 *value = 0;
837 if (where >= 0 && where < sizeof(fake_pci_config) &&
838 (where + size) >= 0 &&
839 (where + size) < sizeof(fake_pci_config) &&
840 size <= sizeof(u32)) {
841 while (size--) {
842 *value <<= 8;
843 *value |= fake_pci_config[where + size];
844 }
845 }
846
847 return PCIBIOS_SUCCESSFUL;
848 }
849
850 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
851 unsigned int devfn,
852 int where, int size,
853 u32 value)
854 {
855 return PCIBIOS_SUCCESSFUL;
856 }
857
858 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
859 {
860 struct device_node *node = pbm->prom_node;
861 struct pci_dev *host_pdev;
862 struct pci_bus *bus;
863
864 printk("PCI: Scanning PBM %s\n", node->full_name);
865
866 /* XXX parent device? XXX */
867 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
868 if (!bus) {
869 printk(KERN_ERR "Failed to create bus for %s\n",
870 node->full_name);
871 return NULL;
872 }
873 bus->secondary = pbm->pci_first_busno;
874 bus->subordinate = pbm->pci_last_busno;
875
876 bus->resource[0] = &pbm->io_space;
877 bus->resource[1] = &pbm->mem_space;
878
879 /* Create the dummy host bridge and link it in. */
880 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
881 bus->self = host_pdev;
882
883 pci_of_scan_bus(pbm, node, bus);
884 pci_bus_add_devices(bus);
885 pci_bus_register_of_sysfs(bus);
886
887 return bus;
888 }
889
890 static void __init pci_scan_each_controller_bus(void)
891 {
892 struct pci_pbm_info *pbm;
893
894 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
895 pbm->scan_bus(pbm);
896 }
897
898 extern void power_init(void);
899
900 static int __init pcibios_init(void)
901 {
902 pci_controller_probe();
903 if (pci_pbm_root == NULL)
904 return 0;
905
906 pci_scan_each_controller_bus();
907
908 isa_init();
909 ebus_init();
910 power_init();
911
912 return 0;
913 }
914
915 subsys_initcall(pcibios_init);
916
917 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
918 {
919 struct pci_pbm_info *pbm = pbus->sysdata;
920
921 /* Generic PCI bus probing sets these to point at
922 * &io{port,mem}_resouce which is wrong for us.
923 */
924 pbus->resource[0] = &pbm->io_space;
925 pbus->resource[1] = &pbm->mem_space;
926 }
927
928 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
929 {
930 struct pci_pbm_info *pbm = pdev->bus->sysdata;
931 struct resource *root = NULL;
932
933 if (r->flags & IORESOURCE_IO)
934 root = &pbm->io_space;
935 if (r->flags & IORESOURCE_MEM)
936 root = &pbm->mem_space;
937
938 return root;
939 }
940
941 void pcibios_update_irq(struct pci_dev *pdev, int irq)
942 {
943 }
944
945 void pcibios_align_resource(void *data, struct resource *res,
946 resource_size_t size, resource_size_t align)
947 {
948 }
949
950 int pcibios_enable_device(struct pci_dev *dev, int mask)
951 {
952 u16 cmd, oldcmd;
953 int i;
954
955 pci_read_config_word(dev, PCI_COMMAND, &cmd);
956 oldcmd = cmd;
957
958 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
959 struct resource *res = &dev->resource[i];
960
961 /* Only set up the requested stuff */
962 if (!(mask & (1<<i)))
963 continue;
964
965 if (res->flags & IORESOURCE_IO)
966 cmd |= PCI_COMMAND_IO;
967 if (res->flags & IORESOURCE_MEM)
968 cmd |= PCI_COMMAND_MEMORY;
969 }
970
971 if (cmd != oldcmd) {
972 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
973 pci_name(dev), cmd);
974 /* Enable the appropriate bits in the PCI command register. */
975 pci_write_config_word(dev, PCI_COMMAND, cmd);
976 }
977 return 0;
978 }
979
980 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
981 struct resource *res)
982 {
983 struct pci_pbm_info *pbm = pdev->bus->sysdata;
984 struct resource zero_res, *root;
985
986 zero_res.start = 0;
987 zero_res.end = 0;
988 zero_res.flags = res->flags;
989
990 if (res->flags & IORESOURCE_IO)
991 root = &pbm->io_space;
992 else
993 root = &pbm->mem_space;
994
995 pci_resource_adjust(&zero_res, root);
996
997 region->start = res->start - zero_res.start;
998 region->end = res->end - zero_res.start;
999 }
1000 EXPORT_SYMBOL(pcibios_resource_to_bus);
1001
1002 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
1003 struct pci_bus_region *region)
1004 {
1005 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1006 struct resource *root;
1007
1008 res->start = region->start;
1009 res->end = region->end;
1010
1011 if (res->flags & IORESOURCE_IO)
1012 root = &pbm->io_space;
1013 else
1014 root = &pbm->mem_space;
1015
1016 pci_resource_adjust(res, root);
1017 }
1018 EXPORT_SYMBOL(pcibios_bus_to_resource);
1019
1020 char * __devinit pcibios_setup(char *str)
1021 {
1022 return str;
1023 }
1024
1025 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1026
1027 /* If the user uses a host-bridge as the PCI device, he may use
1028 * this to perform a raw mmap() of the I/O or MEM space behind
1029 * that controller.
1030 *
1031 * This can be useful for execution of x86 PCI bios initialization code
1032 * on a PCI card, like the xfree86 int10 stuff does.
1033 */
1034 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1035 enum pci_mmap_state mmap_state)
1036 {
1037 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1038 unsigned long space_size, user_offset, user_size;
1039
1040 if (mmap_state == pci_mmap_io) {
1041 space_size = (pbm->io_space.end -
1042 pbm->io_space.start) + 1;
1043 } else {
1044 space_size = (pbm->mem_space.end -
1045 pbm->mem_space.start) + 1;
1046 }
1047
1048 /* Make sure the request is in range. */
1049 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1050 user_size = vma->vm_end - vma->vm_start;
1051
1052 if (user_offset >= space_size ||
1053 (user_offset + user_size) > space_size)
1054 return -EINVAL;
1055
1056 if (mmap_state == pci_mmap_io) {
1057 vma->vm_pgoff = (pbm->io_space.start +
1058 user_offset) >> PAGE_SHIFT;
1059 } else {
1060 vma->vm_pgoff = (pbm->mem_space.start +
1061 user_offset) >> PAGE_SHIFT;
1062 }
1063
1064 return 0;
1065 }
1066
1067 /* Adjust vm_pgoff of VMA such that it is the physical page offset
1068 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1069 *
1070 * Basically, the user finds the base address for his device which he wishes
1071 * to mmap. They read the 32-bit value from the config space base register,
1072 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1073 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1074 *
1075 * Returns negative error code on failure, zero on success.
1076 */
1077 static int __pci_mmap_make_offset(struct pci_dev *pdev,
1078 struct vm_area_struct *vma,
1079 enum pci_mmap_state mmap_state)
1080 {
1081 unsigned long user_paddr, user_size;
1082 int i, err;
1083
1084 /* First compute the physical address in vma->vm_pgoff,
1085 * making sure the user offset is within range in the
1086 * appropriate PCI space.
1087 */
1088 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
1089 if (err)
1090 return err;
1091
1092 /* If this is a mapping on a host bridge, any address
1093 * is OK.
1094 */
1095 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1096 return err;
1097
1098 /* Otherwise make sure it's in the range for one of the
1099 * device's resources.
1100 */
1101 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
1102 user_size = vma->vm_end - vma->vm_start;
1103
1104 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1105 struct resource *rp = &pdev->resource[i];
1106
1107 /* Active? */
1108 if (!rp->flags)
1109 continue;
1110
1111 /* Same type? */
1112 if (i == PCI_ROM_RESOURCE) {
1113 if (mmap_state != pci_mmap_mem)
1114 continue;
1115 } else {
1116 if ((mmap_state == pci_mmap_io &&
1117 (rp->flags & IORESOURCE_IO) == 0) ||
1118 (mmap_state == pci_mmap_mem &&
1119 (rp->flags & IORESOURCE_MEM) == 0))
1120 continue;
1121 }
1122
1123 if ((rp->start <= user_paddr) &&
1124 (user_paddr + user_size) <= (rp->end + 1UL))
1125 break;
1126 }
1127
1128 if (i > PCI_ROM_RESOURCE)
1129 return -EINVAL;
1130
1131 return 0;
1132 }
1133
1134 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1135 * mapping.
1136 */
1137 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1138 enum pci_mmap_state mmap_state)
1139 {
1140 vma->vm_flags |= (VM_IO | VM_RESERVED);
1141 }
1142
1143 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1144 * device mapping.
1145 */
1146 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1147 enum pci_mmap_state mmap_state)
1148 {
1149 /* Our io_remap_pfn_range takes care of this, do nothing. */
1150 }
1151
1152 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1153 * for this architecture. The region in the process to map is described by vm_start
1154 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1155 * The pci device structure is provided so that architectures may make mapping
1156 * decisions on a per-device or per-bus basis.
1157 *
1158 * Returns a negative error code on failure, zero on success.
1159 */
1160 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1161 enum pci_mmap_state mmap_state,
1162 int write_combine)
1163 {
1164 int ret;
1165
1166 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1167 if (ret < 0)
1168 return ret;
1169
1170 __pci_mmap_set_flags(dev, vma, mmap_state);
1171 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1172
1173 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1174 ret = io_remap_pfn_range(vma, vma->vm_start,
1175 vma->vm_pgoff,
1176 vma->vm_end - vma->vm_start,
1177 vma->vm_page_prot);
1178 if (ret)
1179 return ret;
1180
1181 return 0;
1182 }
1183
1184 /* Return the domain nuber for this pci bus */
1185
1186 int pci_domain_nr(struct pci_bus *pbus)
1187 {
1188 struct pci_pbm_info *pbm = pbus->sysdata;
1189 int ret;
1190
1191 if (pbm == NULL || pbm->parent == NULL) {
1192 ret = -ENXIO;
1193 } else {
1194 ret = pbm->index;
1195 }
1196
1197 return ret;
1198 }
1199 EXPORT_SYMBOL(pci_domain_nr);
1200
1201 #ifdef CONFIG_PCI_MSI
1202 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1203 {
1204 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1205 int virt_irq;
1206
1207 if (!pbm->setup_msi_irq)
1208 return -EINVAL;
1209
1210 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1211 }
1212
1213 void arch_teardown_msi_irq(unsigned int virt_irq)
1214 {
1215 struct msi_desc *entry = get_irq_msi(virt_irq);
1216 struct pci_dev *pdev = entry->dev;
1217 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1218
1219 if (!pbm->teardown_msi_irq)
1220 return;
1221
1222 return pbm->teardown_msi_irq(virt_irq, pdev);
1223 }
1224 #endif /* !(CONFIG_PCI_MSI) */
1225
1226 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1227 {
1228 return pdev->dev.archdata.prom_node;
1229 }
1230 EXPORT_SYMBOL(pci_device_to_OF_node);
1231
1232 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1233 {
1234 struct pci_dev *ali_isa_bridge;
1235 u8 val;
1236
1237 /* ALI sound chips generate 31-bits of DMA, a special register
1238 * determines what bit 31 is emitted as.
1239 */
1240 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1241 PCI_DEVICE_ID_AL_M1533,
1242 NULL);
1243
1244 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1245 if (set_bit)
1246 val |= 0x01;
1247 else
1248 val &= ~0x01;
1249 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1250 pci_dev_put(ali_isa_bridge);
1251 }
1252
1253 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1254 {
1255 u64 dma_addr_mask;
1256
1257 if (pdev == NULL) {
1258 dma_addr_mask = 0xffffffff;
1259 } else {
1260 struct iommu *iommu = pdev->dev.archdata.iommu;
1261
1262 dma_addr_mask = iommu->dma_addr_mask;
1263
1264 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1265 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1266 device_mask == 0x7fffffff) {
1267 ali_sound_dma_hack(pdev,
1268 (dma_addr_mask & 0x80000000) != 0);
1269 return 1;
1270 }
1271 }
1272
1273 if (device_mask >= (1UL << 32UL))
1274 return 0;
1275
1276 return (device_mask & dma_addr_mask) == dma_addr_mask;
1277 }
1278
1279 #endif /* !(CONFIG_PCI) */
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