?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ALSA] cs4231-lib: replace common delay loop by function
[linux-2.6/verdex.git] / arch / sparc64 / kernel / pci_sun4v.c
blob95de1444ee674c912a4fc51cf66a2b0b2f64754b
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/log2.h>
16
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/upa.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27
28 #include "pci_sun4v.h"
29
30 static unsigned long vpci_major = 1;
31 static unsigned long vpci_minor = 1;
32
33 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
34
35 struct iommu_batch {
36 struct device *dev; /* Device mapping is for. */
37 unsigned long prot; /* IOMMU page protections */
38 unsigned long entry; /* Index into IOTSB. */
39 u64 *pglist; /* List of physical pages */
40 unsigned long npages; /* Number of pages in list. */
41 };
42
43 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
44
45 /* Interrupts must be disabled. */
46 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
47 {
48 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
49
50 p->dev = dev;
51 p->prot = prot;
52 p->entry = entry;
53 p->npages = 0;
54 }
55
56 /* Interrupts must be disabled. */
57 static long iommu_batch_flush(struct iommu_batch *p)
58 {
59 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
60 unsigned long devhandle = pbm->devhandle;
61 unsigned long prot = p->prot;
62 unsigned long entry = p->entry;
63 u64 *pglist = p->pglist;
64 unsigned long npages = p->npages;
65
66 while (npages != 0) {
67 long num;
68
69 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
70 npages, prot, __pa(pglist));
71 if (unlikely(num < 0)) {
72 if (printk_ratelimit())
73 printk("iommu_batch_flush: IOMMU map of "
74 "[%08lx:%08lx:%lx:%lx:%lx] failed with "
75 "status %ld\n",
76 devhandle, HV_PCI_TSBID(0, entry),
77 npages, prot, __pa(pglist), num);
78 return -1;
79 }
80
81 entry += num;
82 npages -= num;
83 pglist += num;
84 }
85
86 p->entry = entry;
87 p->npages = 0;
88
89 return 0;
90 }
91
92 /* Interrupts must be disabled. */
93 static inline long iommu_batch_add(u64 phys_page)
94 {
95 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
96
97 BUG_ON(p->npages >= PGLIST_NENTS);
98
99 p->pglist[p->npages++] = phys_page;
100 if (p->npages == PGLIST_NENTS)
101 return iommu_batch_flush(p);
102
103 return 0;
104 }
105
106 /* Interrupts must be disabled. */
107 static inline long iommu_batch_end(void)
108 {
109 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
110
111 BUG_ON(p->npages >= PGLIST_NENTS);
112
113 return iommu_batch_flush(p);
114 }
115
116 static long arena_alloc(struct iommu_arena *arena, unsigned long npages)
117 {
118 unsigned long n, i, start, end, limit;
119 int pass;
120
121 limit = arena->limit;
122 start = arena->hint;
123 pass = 0;
124
125 again:
126 n = find_next_zero_bit(arena->map, limit, start);
127 end = n + npages;
128 if (unlikely(end >= limit)) {
129 if (likely(pass < 1)) {
130 limit = start;
131 start = 0;
132 pass++;
133 goto again;
134 } else {
135 /* Scanned the whole thing, give up. */
136 return -1;
137 }
138 }
139
140 for (i = n; i < end; i++) {
141 if (test_bit(i, arena->map)) {
142 start = i + 1;
143 goto again;
144 }
145 }
146
147 for (i = n; i < end; i++)
148 __set_bit(i, arena->map);
149
150 arena->hint = end;
151
152 return n;
153 }
154
155 static void arena_free(struct iommu_arena *arena, unsigned long base,
156 unsigned long npages)
157 {
158 unsigned long i;
159
160 for (i = base; i < (base + npages); i++)
161 __clear_bit(i, arena->map);
162 }
163
164 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
165 dma_addr_t *dma_addrp, gfp_t gfp)
166 {
167 struct iommu *iommu;
168 unsigned long flags, order, first_page, npages, n;
169 void *ret;
170 long entry;
171
172 size = IO_PAGE_ALIGN(size);
173 order = get_order(size);
174 if (unlikely(order >= MAX_ORDER))
175 return NULL;
176
177 npages = size >> IO_PAGE_SHIFT;
178
179 first_page = __get_free_pages(gfp, order);
180 if (unlikely(first_page == 0UL))
181 return NULL;
182
183 memset((char *)first_page, 0, PAGE_SIZE << order);
184
185 iommu = dev->archdata.iommu;
186
187 spin_lock_irqsave(&iommu->lock, flags);
188 entry = arena_alloc(&iommu->arena, npages);
189 spin_unlock_irqrestore(&iommu->lock, flags);
190
191 if (unlikely(entry < 0L))
192 goto arena_alloc_fail;
193
194 *dma_addrp = (iommu->page_table_map_base +
195 (entry << IO_PAGE_SHIFT));
196 ret = (void *) first_page;
197 first_page = __pa(first_page);
198
199 local_irq_save(flags);
200
201 iommu_batch_start(dev,
202 (HV_PCI_MAP_ATTR_READ |
203 HV_PCI_MAP_ATTR_WRITE),
204 entry);
205
206 for (n = 0; n < npages; n++) {
207 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
208 if (unlikely(err < 0L))
209 goto iommu_map_fail;
210 }
211
212 if (unlikely(iommu_batch_end() < 0L))
213 goto iommu_map_fail;
214
215 local_irq_restore(flags);
216
217 return ret;
218
219 iommu_map_fail:
220 /* Interrupts are disabled. */
221 spin_lock(&iommu->lock);
222 arena_free(&iommu->arena, entry, npages);
223 spin_unlock_irqrestore(&iommu->lock, flags);
224
225 arena_alloc_fail:
226 free_pages(first_page, order);
227 return NULL;
228 }
229
230 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
231 dma_addr_t dvma)
232 {
233 struct pci_pbm_info *pbm;
234 struct iommu *iommu;
235 unsigned long flags, order, npages, entry;
236 u32 devhandle;
237
238 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
239 iommu = dev->archdata.iommu;
240 pbm = dev->archdata.host_controller;
241 devhandle = pbm->devhandle;
242 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
243
244 spin_lock_irqsave(&iommu->lock, flags);
245
246 arena_free(&iommu->arena, entry, npages);
247
248 do {
249 unsigned long num;
250
251 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
252 npages);
253 entry += num;
254 npages -= num;
255 } while (npages != 0);
256
257 spin_unlock_irqrestore(&iommu->lock, flags);
258
259 order = get_order(size);
260 if (order < 10)
261 free_pages((unsigned long)cpu, order);
262 }
263
264 static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
265 enum dma_data_direction direction)
266 {
267 struct iommu *iommu;
268 unsigned long flags, npages, oaddr;
269 unsigned long i, base_paddr;
270 u32 bus_addr, ret;
271 unsigned long prot;
272 long entry;
273
274 iommu = dev->archdata.iommu;
275
276 if (unlikely(direction == DMA_NONE))
277 goto bad;
278
279 oaddr = (unsigned long)ptr;
280 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
281 npages >>= IO_PAGE_SHIFT;
282
283 spin_lock_irqsave(&iommu->lock, flags);
284 entry = arena_alloc(&iommu->arena, npages);
285 spin_unlock_irqrestore(&iommu->lock, flags);
286
287 if (unlikely(entry < 0L))
288 goto bad;
289
290 bus_addr = (iommu->page_table_map_base +
291 (entry << IO_PAGE_SHIFT));
292 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
293 base_paddr = __pa(oaddr & IO_PAGE_MASK);
294 prot = HV_PCI_MAP_ATTR_READ;
295 if (direction != DMA_TO_DEVICE)
296 prot |= HV_PCI_MAP_ATTR_WRITE;
297
298 local_irq_save(flags);
299
300 iommu_batch_start(dev, prot, entry);
301
302 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
303 long err = iommu_batch_add(base_paddr);
304 if (unlikely(err < 0L))
305 goto iommu_map_fail;
306 }
307 if (unlikely(iommu_batch_end() < 0L))
308 goto iommu_map_fail;
309
310 local_irq_restore(flags);
311
312 return ret;
313
314 bad:
315 if (printk_ratelimit())
316 WARN_ON(1);
317 return DMA_ERROR_CODE;
318
319 iommu_map_fail:
320 /* Interrupts are disabled. */
321 spin_lock(&iommu->lock);
322 arena_free(&iommu->arena, entry, npages);
323 spin_unlock_irqrestore(&iommu->lock, flags);
324
325 return DMA_ERROR_CODE;
326 }
327
328 static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
329 size_t sz, enum dma_data_direction direction)
330 {
331 struct pci_pbm_info *pbm;
332 struct iommu *iommu;
333 unsigned long flags, npages;
334 long entry;
335 u32 devhandle;
336
337 if (unlikely(direction == DMA_NONE)) {
338 if (printk_ratelimit())
339 WARN_ON(1);
340 return;
341 }
342
343 iommu = dev->archdata.iommu;
344 pbm = dev->archdata.host_controller;
345 devhandle = pbm->devhandle;
346
347 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
348 npages >>= IO_PAGE_SHIFT;
349 bus_addr &= IO_PAGE_MASK;
350
351 spin_lock_irqsave(&iommu->lock, flags);
352
353 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
354 arena_free(&iommu->arena, entry, npages);
355
356 do {
357 unsigned long num;
358
359 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
360 npages);
361 entry += num;
362 npages -= num;
363 } while (npages != 0);
364
365 spin_unlock_irqrestore(&iommu->lock, flags);
366 }
367
368 #define SG_ENT_PHYS_ADDRESS(SG) \
369 (__pa(page_address((SG)->page)) + (SG)->offset)
370
371 static inline long fill_sg(long entry, struct device *dev,
372 struct scatterlist *sg,
373 int nused, int nelems, unsigned long prot)
374 {
375 struct scatterlist *dma_sg = sg;
376 struct scatterlist *sg_end = sg + nelems;
377 unsigned long flags;
378 int i;
379
380 local_irq_save(flags);
381
382 iommu_batch_start(dev, prot, entry);
383
384 for (i = 0; i < nused; i++) {
385 unsigned long pteval = ~0UL;
386 u32 dma_npages;
387
388 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
389 dma_sg->dma_length +
390 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
391 do {
392 unsigned long offset;
393 signed int len;
394
395 /* If we are here, we know we have at least one
396 * more page to map. So walk forward until we
397 * hit a page crossing, and begin creating new
398 * mappings from that spot.
399 */
400 for (;;) {
401 unsigned long tmp;
402
403 tmp = SG_ENT_PHYS_ADDRESS(sg);
404 len = sg->length;
405 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
406 pteval = tmp & IO_PAGE_MASK;
407 offset = tmp & (IO_PAGE_SIZE - 1UL);
408 break;
409 }
410 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
411 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
412 offset = 0UL;
413 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
414 break;
415 }
416 sg++;
417 }
418
419 pteval = (pteval & IOPTE_PAGE);
420 while (len > 0) {
421 long err;
422
423 err = iommu_batch_add(pteval);
424 if (unlikely(err < 0L))
425 goto iommu_map_failed;
426
427 pteval += IO_PAGE_SIZE;
428 len -= (IO_PAGE_SIZE - offset);
429 offset = 0;
430 dma_npages--;
431 }
432
433 pteval = (pteval & IOPTE_PAGE) + len;
434 sg++;
435
436 /* Skip over any tail mappings we've fully mapped,
437 * adjusting pteval along the way. Stop when we
438 * detect a page crossing event.
439 */
440 while (sg < sg_end &&
441 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
442 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
443 ((pteval ^
444 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
445 pteval += sg->length;
446 sg++;
447 }
448 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
449 pteval = ~0UL;
450 } while (dma_npages != 0);
451 dma_sg++;
452 }
453
454 if (unlikely(iommu_batch_end() < 0L))
455 goto iommu_map_failed;
456
457 local_irq_restore(flags);
458 return 0;
459
460 iommu_map_failed:
461 local_irq_restore(flags);
462 return -1L;
463 }
464
465 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
466 int nelems, enum dma_data_direction direction)
467 {
468 struct iommu *iommu;
469 unsigned long flags, npages, prot;
470 u32 dma_base;
471 struct scatterlist *sgtmp;
472 long entry, err;
473 int used;
474
475 /* Fast path single entry scatterlists. */
476 if (nelems == 1) {
477 sglist->dma_address =
478 dma_4v_map_single(dev,
479 (page_address(sglist->page) +
480 sglist->offset),
481 sglist->length, direction);
482 if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
483 return 0;
484 sglist->dma_length = sglist->length;
485 return 1;
486 }
487
488 iommu = dev->archdata.iommu;
489
490 if (unlikely(direction == DMA_NONE))
491 goto bad;
492
493 /* Step 1: Prepare scatter list. */
494 npages = prepare_sg(sglist, nelems);
495
496 /* Step 2: Allocate a cluster and context, if necessary. */
497 spin_lock_irqsave(&iommu->lock, flags);
498 entry = arena_alloc(&iommu->arena, npages);
499 spin_unlock_irqrestore(&iommu->lock, flags);
500
501 if (unlikely(entry < 0L))
502 goto bad;
503
504 dma_base = iommu->page_table_map_base +
505 (entry << IO_PAGE_SHIFT);
506
507 /* Step 3: Normalize DMA addresses. */
508 used = nelems;
509
510 sgtmp = sglist;
511 while (used && sgtmp->dma_length) {
512 sgtmp->dma_address += dma_base;
513 sgtmp++;
514 used--;
515 }
516 used = nelems - used;
517
518 /* Step 4: Create the mappings. */
519 prot = HV_PCI_MAP_ATTR_READ;
520 if (direction != DMA_TO_DEVICE)
521 prot |= HV_PCI_MAP_ATTR_WRITE;
522
523 err = fill_sg(entry, dev, sglist, used, nelems, prot);
524 if (unlikely(err < 0L))
525 goto iommu_map_failed;
526
527 return used;
528
529 bad:
530 if (printk_ratelimit())
531 WARN_ON(1);
532 return 0;
533
534 iommu_map_failed:
535 spin_lock_irqsave(&iommu->lock, flags);
536 arena_free(&iommu->arena, entry, npages);
537 spin_unlock_irqrestore(&iommu->lock, flags);
538
539 return 0;
540 }
541
542 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
543 int nelems, enum dma_data_direction direction)
544 {
545 struct pci_pbm_info *pbm;
546 struct iommu *iommu;
547 unsigned long flags, i, npages;
548 long entry;
549 u32 devhandle, bus_addr;
550
551 if (unlikely(direction == DMA_NONE)) {
552 if (printk_ratelimit())
553 WARN_ON(1);
554 }
555
556 iommu = dev->archdata.iommu;
557 pbm = dev->archdata.host_controller;
558 devhandle = pbm->devhandle;
559
560 bus_addr = sglist->dma_address & IO_PAGE_MASK;
561
562 for (i = 1; i < nelems; i++)
563 if (sglist[i].dma_length == 0)
564 break;
565 i--;
566 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
567 bus_addr) >> IO_PAGE_SHIFT;
568
569 entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
570
571 spin_lock_irqsave(&iommu->lock, flags);
572
573 arena_free(&iommu->arena, entry, npages);
574
575 do {
576 unsigned long num;
577
578 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
579 npages);
580 entry += num;
581 npages -= num;
582 } while (npages != 0);
583
584 spin_unlock_irqrestore(&iommu->lock, flags);
585 }
586
587 static void dma_4v_sync_single_for_cpu(struct device *dev,
588 dma_addr_t bus_addr, size_t sz,
589 enum dma_data_direction direction)
590 {
591 /* Nothing to do... */
592 }
593
594 static void dma_4v_sync_sg_for_cpu(struct device *dev,
595 struct scatterlist *sglist, int nelems,
596 enum dma_data_direction direction)
597 {
598 /* Nothing to do... */
599 }
600
601 const struct dma_ops sun4v_dma_ops = {
602 .alloc_coherent = dma_4v_alloc_coherent,
603 .free_coherent = dma_4v_free_coherent,
604 .map_single = dma_4v_map_single,
605 .unmap_single = dma_4v_unmap_single,
606 .map_sg = dma_4v_map_sg,
607 .unmap_sg = dma_4v_unmap_sg,
608 .sync_single_for_cpu = dma_4v_sync_single_for_cpu,
609 .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu,
610 };
611
612 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
613 {
614 struct property *prop;
615 struct device_node *dp;
616
617 dp = pbm->prom_node;
618 prop = of_find_property(dp, "66mhz-capable", NULL);
619 pbm->is_66mhz_capable = (prop != NULL);
620 pbm->pci_bus = pci_scan_one_pbm(pbm);
621
622 /* XXX register error interrupt handlers XXX */
623 }
624
625 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
626 struct iommu *iommu)
627 {
628 struct iommu_arena *arena = &iommu->arena;
629 unsigned long i, cnt = 0;
630 u32 devhandle;
631
632 devhandle = pbm->devhandle;
633 for (i = 0; i < arena->limit; i++) {
634 unsigned long ret, io_attrs, ra;
635
636 ret = pci_sun4v_iommu_getmap(devhandle,
637 HV_PCI_TSBID(0, i),
638 &io_attrs, &ra);
639 if (ret == HV_EOK) {
640 if (page_in_phys_avail(ra)) {
641 pci_sun4v_iommu_demap(devhandle,
642 HV_PCI_TSBID(0, i), 1);
643 } else {
644 cnt++;
645 __set_bit(i, arena->map);
646 }
647 }
648 }
649
650 return cnt;
651 }
652
653 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
654 {
655 struct iommu *iommu = pbm->iommu;
656 struct property *prop;
657 unsigned long num_tsb_entries, sz, tsbsize;
658 u32 vdma[2], dma_mask, dma_offset;
659
660 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
661 if (prop) {
662 u32 *val = prop->value;
663
664 vdma[0] = val[0];
665 vdma[1] = val[1];
666 } else {
667 /* No property, use default values. */
668 vdma[0] = 0x80000000;
669 vdma[1] = 0x80000000;
670 }
671
672 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
673 prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n",
674 vdma[0], vdma[1]);
675 prom_halt();
676 };
677
678 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
679 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
680 tsbsize = num_tsb_entries * sizeof(iopte_t);
681
682 dma_offset = vdma[0];
683
684 /* Setup initial software IOMMU state. */
685 spin_lock_init(&iommu->lock);
686 iommu->ctx_lowest_free = 1;
687 iommu->page_table_map_base = dma_offset;
688 iommu->dma_addr_mask = dma_mask;
689
690 /* Allocate and initialize the free area map. */
691 sz = (num_tsb_entries + 7) / 8;
692 sz = (sz + 7UL) & ~7UL;
693 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
694 if (!iommu->arena.map) {
695 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
696 prom_halt();
697 }
698 iommu->arena.limit = num_tsb_entries;
699
700 sz = probe_existing_entries(pbm, iommu);
701 if (sz)
702 printk("%s: Imported %lu TSB entries from OBP\n",
703 pbm->name, sz);
704 }
705
706 #ifdef CONFIG_PCI_MSI
707 struct pci_sun4v_msiq_entry {
708 u64 version_type;
709 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
710 #define MSIQ_VERSION_SHIFT 32
711 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
712 #define MSIQ_TYPE_SHIFT 0
713 #define MSIQ_TYPE_NONE 0x00
714 #define MSIQ_TYPE_MSG 0x01
715 #define MSIQ_TYPE_MSI32 0x02
716 #define MSIQ_TYPE_MSI64 0x03
717 #define MSIQ_TYPE_INTX 0x08
718 #define MSIQ_TYPE_NONE2 0xff
719
720 u64 intx_sysino;
721 u64 reserved1;
722 u64 stick;
723 u64 req_id; /* bus/device/func */
724 #define MSIQ_REQID_BUS_MASK 0xff00UL
725 #define MSIQ_REQID_BUS_SHIFT 8
726 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
727 #define MSIQ_REQID_DEVICE_SHIFT 3
728 #define MSIQ_REQID_FUNC_MASK 0x0007UL
729 #define MSIQ_REQID_FUNC_SHIFT 0
730
731 u64 msi_address;
732
733 /* The format of this value is message type dependent.
734 * For MSI bits 15:0 are the data from the MSI packet.
735 * For MSI-X bits 31:0 are the data from the MSI packet.
736 * For MSG, the message code and message routing code where:
737 * bits 39:32 is the bus/device/fn of the msg target-id
738 * bits 18:16 is the message routing code
739 * bits 7:0 is the message code
740 * For INTx the low order 2-bits are:
741 * 00 - INTA
742 * 01 - INTB
743 * 10 - INTC
744 * 11 - INTD
745 */
746 u64 msi_data;
747
748 u64 reserved2;
749 };
750
751 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
752 unsigned long *head)
753 {
754 unsigned long err, limit;
755
756 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
757 if (unlikely(err))
758 return -ENXIO;
759
760 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
761 if (unlikely(*head >= limit))
762 return -EFBIG;
763
764 return 0;
765 }
766
767 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
768 unsigned long msiqid, unsigned long *head,
769 unsigned long *msi)
770 {
771 struct pci_sun4v_msiq_entry *ep;
772 unsigned long err, type;
773
774 /* Note: void pointer arithmetic, 'head' is a byte offset */
775 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
776 (pbm->msiq_ent_count *
777 sizeof(struct pci_sun4v_msiq_entry))) +
778 *head);
779
780 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
781 return 0;
782
783 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
784 if (unlikely(type != MSIQ_TYPE_MSI32 &&
785 type != MSIQ_TYPE_MSI64))
786 return -EINVAL;
787
788 *msi = ep->msi_data;
789
790 err = pci_sun4v_msi_setstate(pbm->devhandle,
791 ep->msi_data /* msi_num */,
792 HV_MSISTATE_IDLE);
793 if (unlikely(err))
794 return -ENXIO;
795
796 /* Clear the entry. */
797 ep->version_type &= ~MSIQ_TYPE_MASK;
798
799 (*head) += sizeof(struct pci_sun4v_msiq_entry);
800 if (*head >=
801 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
802 *head = 0;
803
804 return 1;
805 }
806
807 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
808 unsigned long head)
809 {
810 unsigned long err;
811
812 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
813 if (unlikely(err))
814 return -EINVAL;
815
816 return 0;
817 }
818
819 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
820 unsigned long msi, int is_msi64)
821 {
822 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
823 (is_msi64 ?
824 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
825 return -ENXIO;
826 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
827 return -ENXIO;
828 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
829 return -ENXIO;
830 return 0;
831 }
832
833 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
834 {
835 unsigned long err, msiqid;
836
837 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
838 if (err)
839 return -ENXIO;
840
841 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
842
843 return 0;
844 }
845
846 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
847 {
848 unsigned long q_size, alloc_size, pages, order;
849 int i;
850
851 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
852 alloc_size = (pbm->msiq_num * q_size);
853 order = get_order(alloc_size);
854 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
855 if (pages == 0UL) {
856 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
857 order);
858 return -ENOMEM;
859 }
860 memset((char *)pages, 0, PAGE_SIZE << order);
861 pbm->msi_queues = (void *) pages;
862
863 for (i = 0; i < pbm->msiq_num; i++) {
864 unsigned long err, base = __pa(pages + (i * q_size));
865 unsigned long ret1, ret2;
866
867 err = pci_sun4v_msiq_conf(pbm->devhandle,
868 pbm->msiq_first + i,
869 base, pbm->msiq_ent_count);
870 if (err) {
871 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
872 err);
873 goto h_error;
874 }
875
876 err = pci_sun4v_msiq_info(pbm->devhandle,
877 pbm->msiq_first + i,
878 &ret1, &ret2);
879 if (err) {
880 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
881 err);
882 goto h_error;
883 }
884 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
885 printk(KERN_ERR "MSI: Bogus qconf "
886 "expected[%lx:%x] got[%lx:%lx]\n",
887 base, pbm->msiq_ent_count,
888 ret1, ret2);
889 goto h_error;
890 }
891 }
892
893 return 0;
894
895 h_error:
896 free_pages(pages, order);
897 return -EINVAL;
898 }
899
900 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
901 {
902 unsigned long q_size, alloc_size, pages, order;
903 int i;
904
905 for (i = 0; i < pbm->msiq_num; i++) {
906 unsigned long msiqid = pbm->msiq_first + i;
907
908 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
909 }
910
911 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
912 alloc_size = (pbm->msiq_num * q_size);
913 order = get_order(alloc_size);
914
915 pages = (unsigned long) pbm->msi_queues;
916
917 free_pages(pages, order);
918
919 pbm->msi_queues = NULL;
920 }
921
922 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
923 unsigned long msiqid,
924 unsigned long devino)
925 {
926 unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino);
927
928 if (!virt_irq)
929 return -ENOMEM;
930
931 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
932 return -EINVAL;
933 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
934 return -EINVAL;
935
936 return virt_irq;
937 }
938
939 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
940 .get_head = pci_sun4v_get_head,
941 .dequeue_msi = pci_sun4v_dequeue_msi,
942 .set_head = pci_sun4v_set_head,
943 .msi_setup = pci_sun4v_msi_setup,
944 .msi_teardown = pci_sun4v_msi_teardown,
945 .msiq_alloc = pci_sun4v_msiq_alloc,
946 .msiq_free = pci_sun4v_msiq_free,
947 .msiq_build_irq = pci_sun4v_msiq_build_irq,
948 };
949
950 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
951 {
952 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
953 }
954 #else /* CONFIG_PCI_MSI */
955 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
956 {
957 }
958 #endif /* !(CONFIG_PCI_MSI) */
959
960 static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
961 {
962 struct pci_pbm_info *pbm;
963
964 if (devhandle & 0x40)
965 pbm = &p->pbm_B;
966 else
967 pbm = &p->pbm_A;
968
969 pbm->next = pci_pbm_root;
970 pci_pbm_root = pbm;
971
972 pbm->scan_bus = pci_sun4v_scan_bus;
973 pbm->pci_ops = &sun4v_pci_ops;
974 pbm->config_space_reg_bits = 12;
975
976 pbm->index = pci_num_pbms++;
977
978 pbm->parent = p;
979 pbm->prom_node = dp;
980
981 pbm->devhandle = devhandle;
982
983 pbm->name = dp->full_name;
984
985 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
986
987 pci_determine_mem_io_space(pbm);
988
989 pci_get_pbm_props(pbm);
990 pci_sun4v_iommu_init(pbm);
991 pci_sun4v_msi_init(pbm);
992 }
993
994 void __init sun4v_pci_init(struct device_node *dp, char *model_name)
995 {
996 static int hvapi_negotiated = 0;
997 struct pci_controller_info *p;
998 struct pci_pbm_info *pbm;
999 struct iommu *iommu;
1000 struct property *prop;
1001 struct linux_prom64_registers *regs;
1002 u32 devhandle;
1003 int i;
1004
1005 if (!hvapi_negotiated++) {
1006 int err = sun4v_hvapi_register(HV_GRP_PCI,
1007 vpci_major,
1008 &vpci_minor);
1009
1010 if (err) {
1011 prom_printf("SUN4V_PCI: Could not register hvapi, "
1012 "err=%d\n", err);
1013 prom_halt();
1014 }
1015 printk("SUN4V_PCI: Registered hvapi major[%lu] minor[%lu]\n",
1016 vpci_major, vpci_minor);
1017
1018 dma_ops = &sun4v_dma_ops;
1019 }
1020
1021 prop = of_find_property(dp, "reg", NULL);
1022 regs = prop->value;
1023
1024 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1025
1026 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1027 if (pbm->devhandle == (devhandle ^ 0x40)) {
1028 pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
1029 return;
1030 }
1031 }
1032
1033 for_each_possible_cpu(i) {
1034 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1035
1036 if (!page)
1037 goto fatal_memory_error;
1038
1039 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1040 }
1041
1042 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1043 if (!p)
1044 goto fatal_memory_error;
1045
1046 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1047 if (!iommu)
1048 goto fatal_memory_error;
1049
1050 p->pbm_A.iommu = iommu;
1051
1052 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1053 if (!iommu)
1054 goto fatal_memory_error;
1055
1056 p->pbm_B.iommu = iommu;
1057
1058 pci_sun4v_pbm_init(p, dp, devhandle);
1059 return;
1060
1061 fatal_memory_error:
1062 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1063 prom_halt();
1064 }
Verdex Pro support