1 #include <linux/errno.h>
2 #include <linux/signal.h>
3 #include <linux/sched.h>
4 #include <linux/ioport.h>
5 #include <linux/interrupt.h>
6 #include <linux/slab.h>
7 #include <linux/random.h>
8 #include <linux/init.h>
9 #include <linux/kernel_stat.h>
10 #include <linux/sysdev.h>
11 #include <linux/bitops.h>
13 #include <asm/atomic.h>
14 #include <asm/system.h>
16 #include <asm/timer.h>
17 #include <asm/pgtable.h>
18 #include <asm/delay.h>
21 #include <asm/arch_hooks.h>
22 #include <asm/i8259.h>
27 * This is the 'legacy' 8259A Programmable Interrupt Controller,
28 * present in the majority of PC/AT boxes.
29 * plus some generic x86 specific things if generic specifics makes
31 * this file should become arch/i386/kernel/irq.c when the old irq.c
32 * moves to arch independent land
35 static int i8259A_auto_eoi
;
36 DEFINE_SPINLOCK(i8259A_lock
);
37 static void mask_and_ack_8259A(unsigned int);
39 static struct irq_chip i8259A_chip
= {
41 .mask
= disable_8259A_irq
,
42 .disable
= disable_8259A_irq
,
43 .unmask
= enable_8259A_irq
,
44 .mask_ack
= mask_and_ack_8259A
,
48 * 8259A PIC functions to handle ISA devices:
52 * This contains the irq mask for both 8259A irq controllers,
54 unsigned int cached_irq_mask
= 0xffff;
57 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
58 * boards the timer interrupt is not really connected to any IO-APIC pin,
59 * it's fed to the master 8259A's IR0 line only.
61 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
62 * this 'mixed mode' IRQ handling costs nothing because it's only used
65 unsigned long io_apic_irqs
;
67 void disable_8259A_irq(unsigned int irq
)
69 unsigned int mask
= 1 << irq
;
72 spin_lock_irqsave(&i8259A_lock
, flags
);
73 cached_irq_mask
|= mask
;
75 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
77 outb(cached_master_mask
, PIC_MASTER_IMR
);
78 spin_unlock_irqrestore(&i8259A_lock
, flags
);
81 void enable_8259A_irq(unsigned int irq
)
83 unsigned int mask
= ~(1 << irq
);
86 spin_lock_irqsave(&i8259A_lock
, flags
);
87 cached_irq_mask
&= mask
;
89 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
91 outb(cached_master_mask
, PIC_MASTER_IMR
);
92 spin_unlock_irqrestore(&i8259A_lock
, flags
);
95 int i8259A_irq_pending(unsigned int irq
)
97 unsigned int mask
= 1<<irq
;
101 spin_lock_irqsave(&i8259A_lock
, flags
);
103 ret
= inb(PIC_MASTER_CMD
) & mask
;
105 ret
= inb(PIC_SLAVE_CMD
) & (mask
>> 8);
106 spin_unlock_irqrestore(&i8259A_lock
, flags
);
111 void make_8259A_irq(unsigned int irq
)
113 disable_irq_nosync(irq
);
114 io_apic_irqs
&= ~(1<<irq
);
115 set_irq_chip_and_handler_name(irq
, &i8259A_chip
, handle_level_irq
,
121 * This function assumes to be called rarely. Switching between
122 * 8259A registers is slow.
123 * This has to be protected by the irq controller spinlock
124 * before being called.
126 static inline int i8259A_irq_real(unsigned int irq
)
129 int irqmask
= 1<<irq
;
132 outb(0x0B,PIC_MASTER_CMD
); /* ISR register */
133 value
= inb(PIC_MASTER_CMD
) & irqmask
;
134 outb(0x0A,PIC_MASTER_CMD
); /* back to the IRR register */
137 outb(0x0B,PIC_SLAVE_CMD
); /* ISR register */
138 value
= inb(PIC_SLAVE_CMD
) & (irqmask
>> 8);
139 outb(0x0A,PIC_SLAVE_CMD
); /* back to the IRR register */
144 * Careful! The 8259A is a fragile beast, it pretty
145 * much _has_ to be done exactly like this (mask it
146 * first, _then_ send the EOI, and the order of EOI
147 * to the two 8259s is important!
149 static void mask_and_ack_8259A(unsigned int irq
)
151 unsigned int irqmask
= 1 << irq
;
154 spin_lock_irqsave(&i8259A_lock
, flags
);
156 * Lightweight spurious IRQ detection. We do not want
157 * to overdo spurious IRQ handling - it's usually a sign
158 * of hardware problems, so we only do the checks we can
159 * do without slowing down good hardware unnecessarily.
161 * Note that IRQ7 and IRQ15 (the two spurious IRQs
162 * usually resulting from the 8259A-1|2 PICs) occur
163 * even if the IRQ is masked in the 8259A. Thus we
164 * can check spurious 8259A IRQs without doing the
165 * quite slow i8259A_irq_real() call for every IRQ.
166 * This does not cover 100% of spurious interrupts,
167 * but should be enough to warn the user that there
168 * is something bad going on ...
170 if (cached_irq_mask
& irqmask
)
171 goto spurious_8259A_irq
;
172 cached_irq_mask
|= irqmask
;
176 inb(PIC_SLAVE_IMR
); /* DUMMY - (do we need this?) */
177 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
178 outb(0x60+(irq
&7),PIC_SLAVE_CMD
);/* 'Specific EOI' to slave */
179 outb(0x60+PIC_CASCADE_IR
,PIC_MASTER_CMD
); /* 'Specific EOI' to master-IRQ2 */
181 inb(PIC_MASTER_IMR
); /* DUMMY - (do we need this?) */
182 outb(cached_master_mask
, PIC_MASTER_IMR
);
183 outb(0x60+irq
,PIC_MASTER_CMD
); /* 'Specific EOI to master */
185 spin_unlock_irqrestore(&i8259A_lock
, flags
);
190 * this is the slow path - should happen rarely.
192 if (i8259A_irq_real(irq
))
194 * oops, the IRQ _is_ in service according to the
195 * 8259A - not spurious, go handle it.
197 goto handle_real_irq
;
200 static int spurious_irq_mask
;
202 * At this point we can be sure the IRQ is spurious,
203 * lets ACK and report it. [once per IRQ]
205 if (!(spurious_irq_mask
& irqmask
)) {
206 printk(KERN_DEBUG
"spurious 8259A interrupt: IRQ%d.\n", irq
);
207 spurious_irq_mask
|= irqmask
;
209 atomic_inc(&irq_err_count
);
211 * Theoretically we do not have to handle this IRQ,
212 * but in Linux this does not cause problems and is
215 goto handle_real_irq
;
219 static char irq_trigger
[2];
221 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
223 static void restore_ELCR(char *trigger
)
225 outb(trigger
[0], 0x4d0);
226 outb(trigger
[1], 0x4d1);
229 static void save_ELCR(char *trigger
)
231 /* IRQ 0,1,2,8,13 are marked as reserved */
232 trigger
[0] = inb(0x4d0) & 0xF8;
233 trigger
[1] = inb(0x4d1) & 0xDE;
236 static int i8259A_resume(struct sys_device
*dev
)
238 init_8259A(i8259A_auto_eoi
);
239 restore_ELCR(irq_trigger
);
243 static int i8259A_suspend(struct sys_device
*dev
, pm_message_t state
)
245 save_ELCR(irq_trigger
);
249 static int i8259A_shutdown(struct sys_device
*dev
)
251 /* Put the i8259A into a quiescent state that
252 * the kernel initialization code can get it
255 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
256 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-1 */
260 static struct sysdev_class i8259_sysdev_class
= {
261 set_kset_name("i8259"),
262 .suspend
= i8259A_suspend
,
263 .resume
= i8259A_resume
,
264 .shutdown
= i8259A_shutdown
,
267 static struct sys_device device_i8259A
= {
269 .cls
= &i8259_sysdev_class
,
272 static int __init
i8259A_init_sysfs(void)
274 int error
= sysdev_class_register(&i8259_sysdev_class
);
276 error
= sysdev_register(&device_i8259A
);
280 device_initcall(i8259A_init_sysfs
);
282 void init_8259A(int auto_eoi
)
286 i8259A_auto_eoi
= auto_eoi
;
288 spin_lock_irqsave(&i8259A_lock
, flags
);
290 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
291 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
294 * outb_p - this has to work on a wide range of PC hardware.
296 outb_p(0x11, PIC_MASTER_CMD
); /* ICW1: select 8259A-1 init */
297 outb_p(0x20 + 0, PIC_MASTER_IMR
); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
298 outb_p(1U << PIC_CASCADE_IR
, PIC_MASTER_IMR
); /* 8259A-1 (the master) has a slave on IR2 */
299 if (auto_eoi
) /* master does Auto EOI */
300 outb_p(MASTER_ICW4_DEFAULT
| PIC_ICW4_AEOI
, PIC_MASTER_IMR
);
301 else /* master expects normal EOI */
302 outb_p(MASTER_ICW4_DEFAULT
, PIC_MASTER_IMR
);
304 outb_p(0x11, PIC_SLAVE_CMD
); /* ICW1: select 8259A-2 init */
305 outb_p(0x20 + 8, PIC_SLAVE_IMR
); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
306 outb_p(PIC_CASCADE_IR
, PIC_SLAVE_IMR
); /* 8259A-2 is a slave on master's IR2 */
307 outb_p(SLAVE_ICW4_DEFAULT
, PIC_SLAVE_IMR
); /* (slave's support for AEOI in flat mode is to be investigated) */
310 * In AEOI mode we just have to mask the interrupt
313 i8259A_chip
.mask_ack
= disable_8259A_irq
;
315 i8259A_chip
.mask_ack
= mask_and_ack_8259A
;
317 udelay(100); /* wait for 8259A to initialize */
319 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
320 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
322 spin_unlock_irqrestore(&i8259A_lock
, flags
);
326 * Note that on a 486, we don't want to do a SIGFPE on an irq13
327 * as the irq is unreliable, and exception 16 works correctly
328 * (ie as explained in the intel literature). On a 386, you
329 * can't use exception 16 due to bad IBM design, so we have to
330 * rely on the less exact irq13.
332 * Careful.. Not only is IRQ13 unreliable, but it is also
333 * leads to races. IBM designers who came up with it should
338 static irqreturn_t
math_error_irq(int cpl
, void *dev_id
)
340 extern void math_error(void __user
*);
342 if (ignore_fpu_irq
|| !boot_cpu_data
.hard_math
)
344 math_error((void __user
*)get_irq_regs()->eip
);
349 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
350 * so allow interrupt sharing.
352 static struct irqaction fpu_irq
= { math_error_irq
, 0, CPU_MASK_NONE
, "fpu", NULL
, NULL
};
354 void __init
init_ISA_irqs (void)
358 #ifdef CONFIG_X86_LOCAL_APIC
363 for (i
= 0; i
< NR_IRQS
; i
++) {
364 irq_desc
[i
].status
= IRQ_DISABLED
;
365 irq_desc
[i
].action
= NULL
;
366 irq_desc
[i
].depth
= 1;
370 * 16 old-style INTA-cycle interrupts:
372 set_irq_chip_and_handler_name(i
, &i8259A_chip
,
373 handle_level_irq
, "XT");
376 * 'high' PCI IRQs filled in on demand
378 irq_desc
[i
].chip
= &no_irq_chip
;
383 /* Overridden in paravirt.c */
384 void init_IRQ(void) __attribute__((weak
, alias("native_init_IRQ")));
386 void __init
native_init_IRQ(void)
390 /* all the set up before the call gates are initialised */
391 pre_intr_init_hook();
394 * Cover the whole vector space, no vector can escape
395 * us. (some of these will be overridden and become
396 * 'special' SMP interrupts)
398 for (i
= 0; i
< (NR_VECTORS
- FIRST_EXTERNAL_VECTOR
); i
++) {
399 int vector
= FIRST_EXTERNAL_VECTOR
+ i
;
402 if (vector
!= SYSCALL_VECTOR
)
403 set_intr_gate(vector
, interrupt
[i
]);
406 /* setup after call gates are initialised (usually add in
407 * the architecture specific gates)
412 * External FPU? Set up irq13 if so, for
413 * original braindamaged IBM FERR coupling.
415 if (boot_cpu_data
.hard_math
&& !cpu_has_fpu
)
416 setup_irq(FPU_IRQ
, &fpu_irq
);
418 irq_ctx_init(smp_processor_id());