2 * linux/arch/arm/mm/alignment.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/config.h>
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/proc_fs.h>
21 #include <linux/init.h>
23 #include <asm/uaccess.h>
24 #include <asm/unaligned.h>
29 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
30 * /proc/sys/debug/alignment, modified and integrated into
31 * Linux 2.1 by Russell King
33 * Speed optimisations and better fault handling by Russell King.
36 * This code is not portable to processors with late data abort handling.
38 #define CODING_BITS(i) (i & 0x0e000000)
40 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
41 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
42 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
43 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
44 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
46 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
48 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
49 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
51 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
52 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
53 #define RM_BITS(i) (i & 15) /* Rm */
55 #define REGMASK_BITS(i) (i & 0xffff)
56 #define OFFSET_BITS(i) (i & 0x0fff)
58 #define IS_SHIFT(i) (i & 0x0ff0)
59 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
60 #define SHIFT_TYPE(i) (i & 0x60)
61 #define SHIFT_LSL 0x00
62 #define SHIFT_LSR 0x20
63 #define SHIFT_ASR 0x40
64 #define SHIFT_RORRRX 0x60
66 static unsigned long ai_user
;
67 static unsigned long ai_sys
;
68 static unsigned long ai_skipped
;
69 static unsigned long ai_half
;
70 static unsigned long ai_word
;
71 static unsigned long ai_dword
;
72 static unsigned long ai_multi
;
73 static int ai_usermode
;
76 static const char *usermode_action
[] = {
86 proc_alignment_read(char *page
, char **start
, off_t off
, int count
, int *eof
,
92 p
+= sprintf(p
, "User:\t\t%lu\n", ai_user
);
93 p
+= sprintf(p
, "System:\t\t%lu\n", ai_sys
);
94 p
+= sprintf(p
, "Skipped:\t%lu\n", ai_skipped
);
95 p
+= sprintf(p
, "Half:\t\t%lu\n", ai_half
);
96 p
+= sprintf(p
, "Word:\t\t%lu\n", ai_word
);
97 if (cpu_architecture() >= CPU_ARCH_ARMv5TE
)
98 p
+= sprintf(p
, "DWord:\t\t%lu\n", ai_dword
);
99 p
+= sprintf(p
, "Multi:\t\t%lu\n", ai_multi
);
100 p
+= sprintf(p
, "User faults:\t%i (%s)\n", ai_usermode
,
101 usermode_action
[ai_usermode
]);
103 len
= (p
- page
) - off
;
107 *eof
= (len
<= count
) ? 1 : 0;
113 static int proc_alignment_write(struct file
*file
, const char __user
*buffer
,
114 unsigned long count
, void *data
)
119 if (get_user(mode
, buffer
))
121 if (mode
>= '0' && mode
<= '5')
122 ai_usermode
= mode
- '0';
127 #endif /* CONFIG_PROC_FS */
141 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
142 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
143 #define NEXT_BYTE "ror #24"
146 #define FIRST_BYTE_16
147 #define FIRST_BYTE_32
148 #define NEXT_BYTE "lsr #8"
151 #define __get8_unaligned_check(ins,val,addr,err) \
153 "1: "ins" %1, [%2], #1\n" \
155 " .section .fixup,\"ax\"\n" \
160 " .section __ex_table,\"a\"\n" \
164 : "=r" (err), "=&r" (val), "=r" (addr) \
165 : "0" (err), "2" (addr))
167 #define __get16_unaligned_check(ins,val,addr) \
169 unsigned int err = 0, v, a = addr; \
170 __get8_unaligned_check(ins,v,a,err); \
171 val = v << ((BE) ? 8 : 0); \
172 __get8_unaligned_check(ins,v,a,err); \
173 val |= v << ((BE) ? 0 : 8); \
178 #define get16_unaligned_check(val,addr) \
179 __get16_unaligned_check("ldrb",val,addr)
181 #define get16t_unaligned_check(val,addr) \
182 __get16_unaligned_check("ldrbt",val,addr)
184 #define __get32_unaligned_check(ins,val,addr) \
186 unsigned int err = 0, v, a = addr; \
187 __get8_unaligned_check(ins,v,a,err); \
188 val = v << ((BE) ? 24 : 0); \
189 __get8_unaligned_check(ins,v,a,err); \
190 val |= v << ((BE) ? 16 : 8); \
191 __get8_unaligned_check(ins,v,a,err); \
192 val |= v << ((BE) ? 8 : 16); \
193 __get8_unaligned_check(ins,v,a,err); \
194 val |= v << ((BE) ? 0 : 24); \
199 #define get32_unaligned_check(val,addr) \
200 __get32_unaligned_check("ldrb",val,addr)
202 #define get32t_unaligned_check(val,addr) \
203 __get32_unaligned_check("ldrbt",val,addr)
205 #define __put16_unaligned_check(ins,val,addr) \
207 unsigned int err = 0, v = val, a = addr; \
208 __asm__( FIRST_BYTE_16 \
209 "1: "ins" %1, [%2], #1\n" \
210 " mov %1, %1, "NEXT_BYTE"\n" \
211 "2: "ins" %1, [%2]\n" \
213 " .section .fixup,\"ax\"\n" \
218 " .section __ex_table,\"a\"\n" \
223 : "=r" (err), "=&r" (v), "=&r" (a) \
224 : "0" (err), "1" (v), "2" (a)); \
229 #define put16_unaligned_check(val,addr) \
230 __put16_unaligned_check("strb",val,addr)
232 #define put16t_unaligned_check(val,addr) \
233 __put16_unaligned_check("strbt",val,addr)
235 #define __put32_unaligned_check(ins,val,addr) \
237 unsigned int err = 0, v = val, a = addr; \
238 __asm__( FIRST_BYTE_32 \
239 "1: "ins" %1, [%2], #1\n" \
240 " mov %1, %1, "NEXT_BYTE"\n" \
241 "2: "ins" %1, [%2], #1\n" \
242 " mov %1, %1, "NEXT_BYTE"\n" \
243 "3: "ins" %1, [%2], #1\n" \
244 " mov %1, %1, "NEXT_BYTE"\n" \
245 "4: "ins" %1, [%2]\n" \
247 " .section .fixup,\"ax\"\n" \
252 " .section __ex_table,\"a\"\n" \
259 : "=r" (err), "=&r" (v), "=&r" (a) \
260 : "0" (err), "1" (v), "2" (a)); \
265 #define put32_unaligned_check(val,addr) \
266 __put32_unaligned_check("strb", val, addr)
268 #define put32t_unaligned_check(val,addr) \
269 __put32_unaligned_check("strbt", val, addr)
272 do_alignment_finish_ldst(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
, union offset_union offset
)
274 if (!LDST_U_BIT(instr
))
275 offset
.un
= -offset
.un
;
277 if (!LDST_P_BIT(instr
))
280 if (!LDST_P_BIT(instr
) || LDST_W_BIT(instr
))
281 regs
->uregs
[RN_BITS(instr
)] = addr
;
285 do_alignment_ldrhstrh(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
287 unsigned int rd
= RD_BITS(instr
);
294 if (LDST_L_BIT(instr
)) {
296 get16_unaligned_check(val
, addr
);
298 /* signed half-word? */
300 val
= (signed long)((signed short) val
);
302 regs
->uregs
[rd
] = val
;
304 put16_unaligned_check(regs
->uregs
[rd
], addr
);
309 if (LDST_L_BIT(instr
)) {
311 get16t_unaligned_check(val
, addr
);
313 /* signed half-word? */
315 val
= (signed long)((signed short) val
);
317 regs
->uregs
[rd
] = val
;
319 put16t_unaligned_check(regs
->uregs
[rd
], addr
);
328 do_alignment_ldrdstrd(unsigned long addr
, unsigned long instr
,
329 struct pt_regs
*regs
)
331 unsigned int rd
= RD_BITS(instr
);
338 if ((instr
& 0xf0) == 0xd0) {
340 get32_unaligned_check(val
, addr
);
341 regs
->uregs
[rd
] = val
;
342 get32_unaligned_check(val
, addr
+4);
343 regs
->uregs
[rd
+1] = val
;
345 put32_unaligned_check(regs
->uregs
[rd
], addr
);
346 put32_unaligned_check(regs
->uregs
[rd
+1], addr
+4);
352 if ((instr
& 0xf0) == 0xd0) {
354 get32t_unaligned_check(val
, addr
);
355 regs
->uregs
[rd
] = val
;
356 get32t_unaligned_check(val
, addr
+4);
357 regs
->uregs
[rd
+1] = val
;
359 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
360 put32t_unaligned_check(regs
->uregs
[rd
+1], addr
+4);
370 do_alignment_ldrstr(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
372 unsigned int rd
= RD_BITS(instr
);
376 if ((!LDST_P_BIT(instr
) && LDST_W_BIT(instr
)) || user_mode(regs
))
379 if (LDST_L_BIT(instr
)) {
381 get32_unaligned_check(val
, addr
);
382 regs
->uregs
[rd
] = val
;
384 put32_unaligned_check(regs
->uregs
[rd
], addr
);
388 if (LDST_L_BIT(instr
)) {
390 get32t_unaligned_check(val
, addr
);
391 regs
->uregs
[rd
] = val
;
393 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
401 * LDM/STM alignment handler.
403 * There are 4 variants of this instruction:
405 * B = rn pointer before instruction, A = rn pointer after instruction
406 * ------ increasing address ----->
407 * | | r0 | r1 | ... | rx | |
414 do_alignment_ldmstm(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
416 unsigned int rd
, rn
, correction
, nr_regs
, regbits
;
417 unsigned long eaddr
, newaddr
;
419 if (LDM_S_BIT(instr
))
422 correction
= 4; /* processor implementation defined */
423 regs
->ARM_pc
+= correction
;
427 /* count the number of registers in the mask to be transferred */
428 nr_regs
= hweight16(REGMASK_BITS(instr
)) * 4;
431 newaddr
= eaddr
= regs
->uregs
[rn
];
433 if (!LDST_U_BIT(instr
))
436 if (!LDST_U_BIT(instr
))
439 if (LDST_P_EQ_U(instr
)) /* U = P */
443 * For alignment faults on the ARM922T/ARM920T the MMU makes
444 * the FSR (and hence addr) equal to the updated base address
445 * of the multiple access rather than the restored value.
446 * Switch this message off if we've got a ARM92[02], otherwise
447 * [ls]dm alignment faults are noisy!
449 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
451 * This is a "hint" - we already have eaddr worked out by the
455 printk(KERN_ERR
"LDMSTM: PC = %08lx, instr = %08lx, "
456 "addr = %08lx, eaddr = %08lx\n",
457 instruction_pointer(regs
), instr
, addr
, eaddr
);
462 if (user_mode(regs
)) {
463 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
464 regbits
>>= 1, rd
+= 1)
466 if (LDST_L_BIT(instr
)) {
468 get32t_unaligned_check(val
, eaddr
);
469 regs
->uregs
[rd
] = val
;
471 put32t_unaligned_check(regs
->uregs
[rd
], eaddr
);
475 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
476 regbits
>>= 1, rd
+= 1)
478 if (LDST_L_BIT(instr
)) {
480 get32_unaligned_check(val
, eaddr
);
481 regs
->uregs
[rd
] = val
;
483 put32_unaligned_check(regs
->uregs
[rd
], eaddr
);
488 if (LDST_W_BIT(instr
))
489 regs
->uregs
[rn
] = newaddr
;
490 if (!LDST_L_BIT(instr
) || !(REGMASK_BITS(instr
) & (1 << 15)))
491 regs
->ARM_pc
-= correction
;
495 regs
->ARM_pc
-= correction
;
499 printk(KERN_ERR
"Alignment trap: not handling ldm with s-bit set\n");
504 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
505 * we can reuse ARM userland alignment fault fixups for Thumb.
507 * This implementation was initially based on the algorithm found in
508 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
509 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
512 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
513 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
514 * decode, we return 0xdeadc0de. This should never happen under normal
515 * circumstances but if it does, we've got other problems to deal with
516 * elsewhere and we obviously can't fix those problems here.
520 thumb2arm(u16 tinstr
)
522 u32 L
= (tinstr
& (1<<11)) >> 11;
524 switch ((tinstr
& 0xf800) >> 11) {
525 /* 6.5.1 Format 1: */
526 case 0x6000 >> 11: /* 7.1.52 STR(1) */
527 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
528 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
529 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
531 ((tinstr
& (1<<12)) << (22-12)) | /* fixup */
532 (L
<<20) | /* L==1? */
533 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
534 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
535 ((tinstr
& (31<<6)) >> /* immed_5 */
536 (6 - ((tinstr
& (1<<12)) ? 0 : 2)));
537 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
538 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
540 (L
<<20) | /* L==1? */
541 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
542 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
543 ((tinstr
& (7<<6)) >> (6-1)) | /* immed_5[2:0] */
544 ((tinstr
& (3<<9)) >> (9-8)); /* immed_5[4:3] */
546 /* 6.5.1 Format 2: */
550 static const u32 subset
[8] = {
551 0xe7800000, /* 7.1.53 STR(2) */
552 0xe18000b0, /* 7.1.58 STRH(2) */
553 0xe7c00000, /* 7.1.56 STRB(2) */
554 0xe19000d0, /* 7.1.34 LDRSB */
555 0xe7900000, /* 7.1.27 LDR(2) */
556 0xe19000b0, /* 7.1.33 LDRH(2) */
557 0xe7d00000, /* 7.1.31 LDRB(2) */
558 0xe19000f0 /* 7.1.35 LDRSH */
560 return subset
[(tinstr
& (7<<9)) >> 9] |
561 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
562 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
563 ((tinstr
& (7<<6)) >> (6-0)); /* Rm */
566 /* 6.5.1 Format 3: */
567 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
568 /* NOTE: This case is not technically possible. We're
569 * loading 32-bit memory data via PC relative
570 * addressing mode. So we can and should eliminate
571 * this case. But I'll leave it here for now.
574 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
575 ((tinstr
& 255) << (2-0)); /* immed_8 */
577 /* 6.5.1 Format 4: */
578 case 0x9000 >> 11: /* 7.1.54 STR(3) */
579 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
581 (L
<<20) | /* L==1? */
582 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
583 ((tinstr
& 255) << 2); /* immed_8 */
585 /* 6.6.1 Format 1: */
586 case 0xc000 >> 11: /* 7.1.51 STMIA */
587 case 0xc800 >> 11: /* 7.1.25 LDMIA */
589 u32 Rn
= (tinstr
& (7<<8)) >> 8;
590 u32 W
= ((L
<<Rn
) & (tinstr
&255)) ? 0 : 1<<21;
592 return 0xe8800000 | W
| (L
<<20) | (Rn
<<16) |
596 /* 6.6.1 Format 2: */
597 case 0xb000 >> 11: /* 7.1.48 PUSH */
598 case 0xb800 >> 11: /* 7.1.47 POP */
599 if ((tinstr
& (3 << 9)) == 0x0400) {
600 static const u32 subset
[4] = {
601 0xe92d0000, /* STMDB sp!,{registers} */
602 0xe92d4000, /* STMDB sp!,{registers,lr} */
603 0xe8bd0000, /* LDMIA sp!,{registers} */
604 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
606 return subset
[(L
<<1) | ((tinstr
& (1<<8)) >> 8)] |
607 (tinstr
& 255); /* register_list */
609 /* Else fall through for illegal instruction case */
617 do_alignment(unsigned long addr
, unsigned int fsr
, struct pt_regs
*regs
)
619 union offset_union offset
;
620 unsigned long instr
= 0, instrptr
;
621 int (*handler
)(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
);
627 instrptr
= instruction_pointer(regs
);
631 if thumb_mode(regs
) {
632 fault
= __get_user(tinstr
, (u16
*)(instrptr
& ~1));
634 instr
= thumb2arm(tinstr
);
636 fault
= __get_user(instr
, (u32
*)instrptr
);
651 regs
->ARM_pc
+= thumb_mode(regs
) ? 2 : 4;
653 switch (CODING_BITS(instr
)) {
654 case 0x00000000: /* 3.13.4 load/store instruction extensions */
655 if (LDSTHD_I_BIT(instr
))
656 offset
.un
= (instr
& 0xf00) >> 4 | (instr
& 15);
658 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
660 if ((instr
& 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
661 (instr
& 0x001000f0) == 0x001000f0) /* LDRSH */
662 handler
= do_alignment_ldrhstrh
;
663 else if ((instr
& 0x001000f0) == 0x000000d0 || /* LDRD */
664 (instr
& 0x001000f0) == 0x000000f0) /* STRD */
665 handler
= do_alignment_ldrdstrd
;
670 case 0x04000000: /* ldr or str immediate */
671 offset
.un
= OFFSET_BITS(instr
);
672 handler
= do_alignment_ldrstr
;
675 case 0x06000000: /* ldr or str register */
676 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
678 if (IS_SHIFT(instr
)) {
679 unsigned int shiftval
= SHIFT_BITS(instr
);
681 switch(SHIFT_TYPE(instr
)) {
683 offset
.un
<<= shiftval
;
687 offset
.un
>>= shiftval
;
691 offset
.sn
>>= shiftval
;
697 if (regs
->ARM_cpsr
& PSR_C_BIT
)
698 offset
.un
|= 1 << 31;
700 offset
.un
= offset
.un
>> shiftval
|
701 offset
.un
<< (32 - shiftval
);
705 handler
= do_alignment_ldrstr
;
708 case 0x08000000: /* ldm or stm */
709 handler
= do_alignment_ldmstm
;
716 type
= handler(addr
, instr
, regs
);
718 if (type
== TYPE_ERROR
|| type
== TYPE_FAULT
)
721 if (type
== TYPE_LDST
)
722 do_alignment_finish_ldst(addr
, instr
, regs
, offset
);
727 if (type
== TYPE_ERROR
)
729 regs
->ARM_pc
-= thumb_mode(regs
) ? 2 : 4;
731 * We got a fault - fix it up, or die.
733 do_bad_area(current
, current
->mm
, addr
, fsr
, regs
);
738 * Oops, we didn't handle the instruction.
740 printk(KERN_ERR
"Alignment trap: not handling instruction "
741 "%0*lx at [<%08lx>]\n",
742 thumb_mode(regs
) ? 4 : 8,
743 thumb_mode(regs
) ? tinstr
: instr
, instrptr
);
751 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
752 "Address=0x%08lx FSR 0x%03x\n", current
->comm
,
753 current
->pid
, instrptr
,
754 thumb_mode(regs
) ? 4 : 8,
755 thumb_mode(regs
) ? tinstr
: instr
,
762 force_sig(SIGBUS
, current
);
764 set_cr(cr_no_alignment
);
770 * This needs to be done after sysctl_init, otherwise sys/ will be
771 * overwritten. Actually, this shouldn't be in sys/ at all since
772 * it isn't a sysctl, and it doesn't contain sysctl information.
773 * We now locate it in /proc/cpu/alignment instead.
775 static int __init
alignment_init(void)
777 #ifdef CONFIG_PROC_FS
778 struct proc_dir_entry
*res
;
780 res
= proc_mkdir("cpu", NULL
);
784 res
= create_proc_entry("alignment", S_IWUSR
| S_IRUGO
, res
);
788 res
->read_proc
= proc_alignment_read
;
789 res
->write_proc
= proc_alignment_write
;
792 hook_fault_code(1, do_alignment
, SIGILL
, "alignment exception");
793 hook_fault_code(3, do_alignment
, SIGILL
, "alignment exception");
798 fs_initcall(alignment_init
);