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PCI: make no_pci_devices() use the pci_bus_type list
[linux-2.6/verdex.git] / drivers / pci / probe.c
blob387fbbb97431eef05d3920db995690ce2f201240
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25
26 static int find_anything(struct device *dev, void *data)
27 {
28 return 1;
29 }
30
31 /*
32 * Some device drivers need know if pci is initiated.
33 * Basically, we think pci is not initiated when there
34 * is no device to be found on the pci_bus_type.
35 */
36 int no_pci_devices(void)
37 {
38 struct device *dev;
39 int no_devices;
40
41 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
42 no_devices = (dev == NULL);
43 put_device(dev);
44 return no_devices;
45 }
46 EXPORT_SYMBOL(no_pci_devices);
47
48 #ifdef HAVE_PCI_LEGACY
49 /**
50 * pci_create_legacy_files - create legacy I/O port and memory files
51 * @b: bus to create files under
52 *
53 * Some platforms allow access to legacy I/O port and ISA memory space on
54 * a per-bus basis. This routine creates the files and ties them into
55 * their associated read, write and mmap files from pci-sysfs.c
56 */
57 static void pci_create_legacy_files(struct pci_bus *b)
58 {
59 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
60 GFP_ATOMIC);
61 if (b->legacy_io) {
62 b->legacy_io->attr.name = "legacy_io";
63 b->legacy_io->size = 0xffff;
64 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
65 b->legacy_io->read = pci_read_legacy_io;
66 b->legacy_io->write = pci_write_legacy_io;
67 device_create_bin_file(&b->dev, b->legacy_io);
68
69 /* Allocated above after the legacy_io struct */
70 b->legacy_mem = b->legacy_io + 1;
71 b->legacy_mem->attr.name = "legacy_mem";
72 b->legacy_mem->size = 1024*1024;
73 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
74 b->legacy_mem->mmap = pci_mmap_legacy_mem;
75 device_create_bin_file(&b->dev, b->legacy_mem);
76 }
77 }
78
79 void pci_remove_legacy_files(struct pci_bus *b)
80 {
81 if (b->legacy_io) {
82 device_remove_bin_file(&b->dev, b->legacy_io);
83 device_remove_bin_file(&b->dev, b->legacy_mem);
84 kfree(b->legacy_io); /* both are allocated here */
85 }
86 }
87 #else /* !HAVE_PCI_LEGACY */
88 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
89 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
90 #endif /* HAVE_PCI_LEGACY */
91
92 /*
93 * PCI Bus Class Devices
94 */
95 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
96 struct device_attribute *attr,
97 char *buf)
98 {
99 int ret;
100 cpumask_t cpumask;
101
102 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
103 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
104 if (ret < PAGE_SIZE)
105 buf[ret++] = '\n';
106 return ret;
107 }
108 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
109
110 /*
111 * PCI Bus Class
112 */
113 static void release_pcibus_dev(struct device *dev)
114 {
115 struct pci_bus *pci_bus = to_pci_bus(dev);
116
117 if (pci_bus->bridge)
118 put_device(pci_bus->bridge);
119 kfree(pci_bus);
120 }
121
122 static struct class pcibus_class = {
123 .name = "pci_bus",
124 .dev_release = &release_pcibus_dev,
125 };
126
127 static int __init pcibus_class_init(void)
128 {
129 return class_register(&pcibus_class);
130 }
131 postcore_initcall(pcibus_class_init);
132
133 /*
134 * Translate the low bits of the PCI base
135 * to the resource type
136 */
137 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
138 {
139 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
140 return IORESOURCE_IO;
141
142 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
143 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
144
145 return IORESOURCE_MEM;
146 }
147
148 /*
149 * Find the extent of a PCI decode..
150 */
151 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
152 {
153 u32 size = mask & maxbase; /* Find the significant bits */
154 if (!size)
155 return 0;
156
157 /* Get the lowest of them to find the decode size, and
158 from that the extent. */
159 size = (size & ~(size-1)) - 1;
160
161 /* base == maxbase can be valid only if the BAR has
162 already been programmed with all 1s. */
163 if (base == maxbase && ((base | size) & mask) != mask)
164 return 0;
165
166 return size;
167 }
168
169 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
170 {
171 u64 size = mask & maxbase; /* Find the significant bits */
172 if (!size)
173 return 0;
174
175 /* Get the lowest of them to find the decode size, and
176 from that the extent. */
177 size = (size & ~(size-1)) - 1;
178
179 /* base == maxbase can be valid only if the BAR has
180 already been programmed with all 1s. */
181 if (base == maxbase && ((base | size) & mask) != mask)
182 return 0;
183
184 return size;
185 }
186
187 static inline int is_64bit_memory(u32 mask)
188 {
189 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
190 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
191 return 1;
192 return 0;
193 }
194
195 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
196 {
197 unsigned int pos, reg, next;
198 u32 l, sz;
199 struct resource *res;
200
201 for(pos=0; pos<howmany; pos = next) {
202 u64 l64;
203 u64 sz64;
204 u32 raw_sz;
205
206 next = pos+1;
207 res = &dev->resource[pos];
208 res->name = pci_name(dev);
209 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
210 pci_read_config_dword(dev, reg, &l);
211 pci_write_config_dword(dev, reg, ~0);
212 pci_read_config_dword(dev, reg, &sz);
213 pci_write_config_dword(dev, reg, l);
214 if (!sz || sz == 0xffffffff)
215 continue;
216 if (l == 0xffffffff)
217 l = 0;
218 raw_sz = sz;
219 if ((l & PCI_BASE_ADDRESS_SPACE) ==
220 PCI_BASE_ADDRESS_SPACE_MEMORY) {
221 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
222 /*
223 * For 64bit prefetchable memory sz could be 0, if the
224 * real size is bigger than 4G, so we need to check
225 * szhi for that.
226 */
227 if (!is_64bit_memory(l) && !sz)
228 continue;
229 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
230 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
231 } else {
232 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
233 if (!sz)
234 continue;
235 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
236 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
237 }
238 res->end = res->start + (unsigned long) sz;
239 res->flags |= pci_calc_resource_flags(l);
240 if (is_64bit_memory(l)) {
241 u32 szhi, lhi;
242
243 pci_read_config_dword(dev, reg+4, &lhi);
244 pci_write_config_dword(dev, reg+4, ~0);
245 pci_read_config_dword(dev, reg+4, &szhi);
246 pci_write_config_dword(dev, reg+4, lhi);
247 sz64 = ((u64)szhi << 32) | raw_sz;
248 l64 = ((u64)lhi << 32) | l;
249 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
250 next++;
251 #if BITS_PER_LONG == 64
252 if (!sz64) {
253 res->start = 0;
254 res->end = 0;
255 res->flags = 0;
256 continue;
257 }
258 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
259 res->end = res->start + sz64;
260 #else
261 if (sz64 > 0x100000000ULL) {
262 printk(KERN_ERR "PCI: Unable to handle 64-bit "
263 "BAR for device %s\n", pci_name(dev));
264 res->start = 0;
265 res->flags = 0;
266 } else if (lhi) {
267 /* 64-bit wide address, treat as disabled */
268 pci_write_config_dword(dev, reg,
269 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
270 pci_write_config_dword(dev, reg+4, 0);
271 res->start = 0;
272 res->end = sz;
273 }
274 #endif
275 }
276 }
277 if (rom) {
278 dev->rom_base_reg = rom;
279 res = &dev->resource[PCI_ROM_RESOURCE];
280 res->name = pci_name(dev);
281 pci_read_config_dword(dev, rom, &l);
282 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
283 pci_read_config_dword(dev, rom, &sz);
284 pci_write_config_dword(dev, rom, l);
285 if (l == 0xffffffff)
286 l = 0;
287 if (sz && sz != 0xffffffff) {
288 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
289 if (sz) {
290 res->flags = (l & IORESOURCE_ROM_ENABLE) |
291 IORESOURCE_MEM | IORESOURCE_PREFETCH |
292 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
293 res->start = l & PCI_ROM_ADDRESS_MASK;
294 res->end = res->start + (unsigned long) sz;
295 }
296 }
297 }
298 }
299
300 void __devinit pci_read_bridge_bases(struct pci_bus *child)
301 {
302 struct pci_dev *dev = child->self;
303 u8 io_base_lo, io_limit_lo;
304 u16 mem_base_lo, mem_limit_lo;
305 unsigned long base, limit;
306 struct resource *res;
307 int i;
308
309 if (!dev) /* It's a host bus, nothing to read */
310 return;
311
312 if (dev->transparent) {
313 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
314 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
315 child->resource[i] = child->parent->resource[i - 3];
316 }
317
318 for(i=0; i<3; i++)
319 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
320
321 res = child->resource[0];
322 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
323 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
324 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
325 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
326
327 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
328 u16 io_base_hi, io_limit_hi;
329 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
330 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
331 base |= (io_base_hi << 16);
332 limit |= (io_limit_hi << 16);
333 }
334
335 if (base <= limit) {
336 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
337 if (!res->start)
338 res->start = base;
339 if (!res->end)
340 res->end = limit + 0xfff;
341 }
342
343 res = child->resource[1];
344 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
345 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
346 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
347 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
348 if (base <= limit) {
349 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
350 res->start = base;
351 res->end = limit + 0xfffff;
352 }
353
354 res = child->resource[2];
355 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
356 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
357 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
358 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
359
360 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
361 u32 mem_base_hi, mem_limit_hi;
362 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
363 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
364
365 /*
366 * Some bridges set the base > limit by default, and some
367 * (broken) BIOSes do not initialize them. If we find
368 * this, just assume they are not being used.
369 */
370 if (mem_base_hi <= mem_limit_hi) {
371 #if BITS_PER_LONG == 64
372 base |= ((long) mem_base_hi) << 32;
373 limit |= ((long) mem_limit_hi) << 32;
374 #else
375 if (mem_base_hi || mem_limit_hi) {
376 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
377 return;
378 }
379 #endif
380 }
381 }
382 if (base <= limit) {
383 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
384 res->start = base;
385 res->end = limit + 0xfffff;
386 }
387 }
388
389 static struct pci_bus * pci_alloc_bus(void)
390 {
391 struct pci_bus *b;
392
393 b = kzalloc(sizeof(*b), GFP_KERNEL);
394 if (b) {
395 INIT_LIST_HEAD(&b->node);
396 INIT_LIST_HEAD(&b->children);
397 INIT_LIST_HEAD(&b->devices);
398 }
399 return b;
400 }
401
402 static struct pci_bus * __devinit
403 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
404 {
405 struct pci_bus *child;
406 int i;
407
408 /*
409 * Allocate a new bus, and inherit stuff from the parent..
410 */
411 child = pci_alloc_bus();
412 if (!child)
413 return NULL;
414
415 child->self = bridge;
416 child->parent = parent;
417 child->ops = parent->ops;
418 child->sysdata = parent->sysdata;
419 child->bus_flags = parent->bus_flags;
420 child->bridge = get_device(&bridge->dev);
421
422 /* initialize some portions of the bus device, but don't register it
423 * now as the parent is not properly set up yet. This device will get
424 * registered later in pci_bus_add_devices()
425 */
426 child->dev.class = &pcibus_class;
427 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
428
429 /*
430 * Set up the primary, secondary and subordinate
431 * bus numbers.
432 */
433 child->number = child->secondary = busnr;
434 child->primary = parent->secondary;
435 child->subordinate = 0xff;
436
437 /* Set up default resource pointers and names.. */
438 for (i = 0; i < 4; i++) {
439 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
440 child->resource[i]->name = child->name;
441 }
442 bridge->subordinate = child;
443
444 return child;
445 }
446
447 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
448 {
449 struct pci_bus *child;
450
451 child = pci_alloc_child_bus(parent, dev, busnr);
452 if (child) {
453 down_write(&pci_bus_sem);
454 list_add_tail(&child->node, &parent->children);
455 up_write(&pci_bus_sem);
456 }
457 return child;
458 }
459
460 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
461 {
462 struct pci_bus *parent = child->parent;
463
464 /* Attempts to fix that up are really dangerous unless
465 we're going to re-assign all bus numbers. */
466 if (!pcibios_assign_all_busses())
467 return;
468
469 while (parent->parent && parent->subordinate < max) {
470 parent->subordinate = max;
471 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
472 parent = parent->parent;
473 }
474 }
475
476 /*
477 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will
479 * be handled by the bridge driver itself.
480 *
481 * We need to process bridges in two passes -- first we scan those
482 * already configured by the BIOS and after we are done with all of
483 * them, we proceed to assigning numbers to the remaining buses in
484 * order to avoid overlaps between old and new bus numbers.
485 */
486 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
487 {
488 struct pci_bus *child;
489 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
490 u32 buses, i, j = 0;
491 u16 bctl;
492
493 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
494
495 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
496 pci_name(dev), buses & 0xffffff, pass);
497
498 /* Disable MasterAbortMode during probing to avoid reporting
499 of bus errors (in some architectures) */
500 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
501 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
502 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
503
504 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
505 unsigned int cmax, busnr;
506 /*
507 * Bus already configured by firmware, process it in the first
508 * pass and just note the configuration.
509 */
510 if (pass)
511 goto out;
512 busnr = (buses >> 8) & 0xFF;
513
514 /*
515 * If we already got to this bus through a different bridge,
516 * ignore it. This can happen with the i450NX chipset.
517 */
518 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
519 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
520 pci_domain_nr(bus), busnr);
521 goto out;
522 }
523
524 child = pci_add_new_bus(bus, dev, busnr);
525 if (!child)
526 goto out;
527 child->primary = buses & 0xFF;
528 child->subordinate = (buses >> 16) & 0xFF;
529 child->bridge_ctl = bctl;
530
531 cmax = pci_scan_child_bus(child);
532 if (cmax > max)
533 max = cmax;
534 if (child->subordinate > max)
535 max = child->subordinate;
536 } else {
537 /*
538 * We need to assign a number to this bus which we always
539 * do in the second pass.
540 */
541 if (!pass) {
542 if (pcibios_assign_all_busses())
543 /* Temporarily disable forwarding of the
544 configuration cycles on all bridges in
545 this bus segment to avoid possible
546 conflicts in the second pass between two
547 bridges programmed with overlapping
548 bus ranges. */
549 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
550 buses & ~0xffffff);
551 goto out;
552 }
553
554 /* Clear errors */
555 pci_write_config_word(dev, PCI_STATUS, 0xffff);
556
557 /* Prevent assigning a bus number that already exists.
558 * This can happen when a bridge is hot-plugged */
559 if (pci_find_bus(pci_domain_nr(bus), max+1))
560 goto out;
561 child = pci_add_new_bus(bus, dev, ++max);
562 buses = (buses & 0xff000000)
563 | ((unsigned int)(child->primary) << 0)
564 | ((unsigned int)(child->secondary) << 8)
565 | ((unsigned int)(child->subordinate) << 16);
566
567 /*
568 * yenta.c forces a secondary latency timer of 176.
569 * Copy that behaviour here.
570 */
571 if (is_cardbus) {
572 buses &= ~0xff000000;
573 buses |= CARDBUS_LATENCY_TIMER << 24;
574 }
575
576 /*
577 * We need to blast all three values with a single write.
578 */
579 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
580
581 if (!is_cardbus) {
582 child->bridge_ctl = bctl;
583 /*
584 * Adjust subordinate busnr in parent buses.
585 * We do this before scanning for children because
586 * some devices may not be detected if the bios
587 * was lazy.
588 */
589 pci_fixup_parent_subordinate_busnr(child, max);
590 /* Now we can scan all subordinate buses... */
591 max = pci_scan_child_bus(child);
592 /*
593 * now fix it up again since we have found
594 * the real value of max.
595 */
596 pci_fixup_parent_subordinate_busnr(child, max);
597 } else {
598 /*
599 * For CardBus bridges, we leave 4 bus numbers
600 * as cards with a PCI-to-PCI bridge can be
601 * inserted later.
602 */
603 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
604 struct pci_bus *parent = bus;
605 if (pci_find_bus(pci_domain_nr(bus),
606 max+i+1))
607 break;
608 while (parent->parent) {
609 if ((!pcibios_assign_all_busses()) &&
610 (parent->subordinate > max) &&
611 (parent->subordinate <= max+i)) {
612 j = 1;
613 }
614 parent = parent->parent;
615 }
616 if (j) {
617 /*
618 * Often, there are two cardbus bridges
619 * -- try to leave one valid bus number
620 * for each one.
621 */
622 i /= 2;
623 break;
624 }
625 }
626 max += i;
627 pci_fixup_parent_subordinate_busnr(child, max);
628 }
629 /*
630 * Set the subordinate bus number to its real value.
631 */
632 child->subordinate = max;
633 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
634 }
635
636 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
637
638 /* Has only triggered on CardBus, fixup is in yenta_socket */
639 while (bus->parent) {
640 if ((child->subordinate > bus->subordinate) ||
641 (child->number > bus->subordinate) ||
642 (child->number < bus->number) ||
643 (child->subordinate < bus->number)) {
644 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
645 "hidden behind%s bridge #%02x (-#%02x)\n",
646 child->number, child->subordinate,
647 (bus->number > child->subordinate &&
648 bus->subordinate < child->number) ?
649 "wholly" : "partially",
650 bus->self->transparent ? " transparent" : "",
651 bus->number, bus->subordinate);
652 }
653 bus = bus->parent;
654 }
655
656 out:
657 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
658
659 return max;
660 }
661
662 /*
663 * Read interrupt line and base address registers.
664 * The architecture-dependent code can tweak these, of course.
665 */
666 static void pci_read_irq(struct pci_dev *dev)
667 {
668 unsigned char irq;
669
670 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
671 dev->pin = irq;
672 if (irq)
673 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
674 dev->irq = irq;
675 }
676
677 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
678
679 /**
680 * pci_setup_device - fill in class and map information of a device
681 * @dev: the device structure to fill
682 *
683 * Initialize the device structure with information about the device's
684 * vendor,class,memory and IO-space addresses,IRQ lines etc.
685 * Called at initialisation of the PCI subsystem and by CardBus services.
686 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
687 * or CardBus).
688 */
689 static int pci_setup_device(struct pci_dev * dev)
690 {
691 u32 class;
692
693 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
694 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
695
696 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
697 dev->revision = class & 0xff;
698 class >>= 8; /* upper 3 bytes */
699 dev->class = class;
700 class >>= 8;
701
702 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
703 dev->vendor, dev->device, class, dev->hdr_type);
704
705 /* "Unknown power state" */
706 dev->current_state = PCI_UNKNOWN;
707
708 /* Early fixups, before probing the BARs */
709 pci_fixup_device(pci_fixup_early, dev);
710 class = dev->class >> 8;
711
712 switch (dev->hdr_type) { /* header type */
713 case PCI_HEADER_TYPE_NORMAL: /* standard header */
714 if (class == PCI_CLASS_BRIDGE_PCI)
715 goto bad;
716 pci_read_irq(dev);
717 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
718 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
719 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
720
721 /*
722 * Do the ugly legacy mode stuff here rather than broken chip
723 * quirk code. Legacy mode ATA controllers have fixed
724 * addresses. These are not always echoed in BAR0-3, and
725 * BAR0-3 in a few cases contain junk!
726 */
727 if (class == PCI_CLASS_STORAGE_IDE) {
728 u8 progif;
729 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
730 if ((progif & 1) == 0) {
731 dev->resource[0].start = 0x1F0;
732 dev->resource[0].end = 0x1F7;
733 dev->resource[0].flags = LEGACY_IO_RESOURCE;
734 dev->resource[1].start = 0x3F6;
735 dev->resource[1].end = 0x3F6;
736 dev->resource[1].flags = LEGACY_IO_RESOURCE;
737 }
738 if ((progif & 4) == 0) {
739 dev->resource[2].start = 0x170;
740 dev->resource[2].end = 0x177;
741 dev->resource[2].flags = LEGACY_IO_RESOURCE;
742 dev->resource[3].start = 0x376;
743 dev->resource[3].end = 0x376;
744 dev->resource[3].flags = LEGACY_IO_RESOURCE;
745 }
746 }
747 break;
748
749 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
750 if (class != PCI_CLASS_BRIDGE_PCI)
751 goto bad;
752 /* The PCI-to-PCI bridge spec requires that subtractive
753 decoding (i.e. transparent) bridge must have programming
754 interface code of 0x01. */
755 pci_read_irq(dev);
756 dev->transparent = ((dev->class & 0xff) == 1);
757 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
758 break;
759
760 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
761 if (class != PCI_CLASS_BRIDGE_CARDBUS)
762 goto bad;
763 pci_read_irq(dev);
764 pci_read_bases(dev, 1, 0);
765 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
766 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
767 break;
768
769 default: /* unknown header */
770 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
771 pci_name(dev), dev->hdr_type);
772 return -1;
773
774 bad:
775 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
776 pci_name(dev), class, dev->hdr_type);
777 dev->class = PCI_CLASS_NOT_DEFINED;
778 }
779
780 /* We found a fine healthy device, go go go... */
781 return 0;
782 }
783
784 /**
785 * pci_release_dev - free a pci device structure when all users of it are finished.
786 * @dev: device that's been disconnected
787 *
788 * Will be called only by the device core when all users of this pci device are
789 * done.
790 */
791 static void pci_release_dev(struct device *dev)
792 {
793 struct pci_dev *pci_dev;
794
795 pci_dev = to_pci_dev(dev);
796 kfree(pci_dev);
797 }
798
799 static void set_pcie_port_type(struct pci_dev *pdev)
800 {
801 int pos;
802 u16 reg16;
803
804 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
805 if (!pos)
806 return;
807 pdev->is_pcie = 1;
808 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
809 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
810 }
811
812 /**
813 * pci_cfg_space_size - get the configuration space size of the PCI device.
814 * @dev: PCI device
815 *
816 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
817 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
818 * access it. Maybe we don't have a way to generate extended config space
819 * accesses, or the device is behind a reverse Express bridge. So we try
820 * reading the dword at 0x100 which must either be 0 or a valid extended
821 * capability header.
822 */
823 int pci_cfg_space_size(struct pci_dev *dev)
824 {
825 int pos;
826 u32 status;
827
828 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
829 if (!pos) {
830 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
831 if (!pos)
832 goto fail;
833
834 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
835 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
836 goto fail;
837 }
838
839 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
840 goto fail;
841 if (status == 0xffffffff)
842 goto fail;
843
844 return PCI_CFG_SPACE_EXP_SIZE;
845
846 fail:
847 return PCI_CFG_SPACE_SIZE;
848 }
849
850 static void pci_release_bus_bridge_dev(struct device *dev)
851 {
852 kfree(dev);
853 }
854
855 struct pci_dev *alloc_pci_dev(void)
856 {
857 struct pci_dev *dev;
858
859 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
860 if (!dev)
861 return NULL;
862
863 INIT_LIST_HEAD(&dev->global_list);
864 INIT_LIST_HEAD(&dev->bus_list);
865
866 pci_msi_init_pci_dev(dev);
867
868 return dev;
869 }
870 EXPORT_SYMBOL(alloc_pci_dev);
871
872 /*
873 * Read the config data for a PCI device, sanity-check it
874 * and fill in the dev structure...
875 */
876 static struct pci_dev * __devinit
877 pci_scan_device(struct pci_bus *bus, int devfn)
878 {
879 struct pci_dev *dev;
880 u32 l;
881 u8 hdr_type;
882 int delay = 1;
883
884 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
885 return NULL;
886
887 /* some broken boards return 0 or ~0 if a slot is empty: */
888 if (l == 0xffffffff || l == 0x00000000 ||
889 l == 0x0000ffff || l == 0xffff0000)
890 return NULL;
891
892 /* Configuration request Retry Status */
893 while (l == 0xffff0001) {
894 msleep(delay);
895 delay *= 2;
896 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
897 return NULL;
898 /* Card hasn't responded in 60 seconds? Must be stuck. */
899 if (delay > 60 * 1000) {
900 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
901 "responding\n", pci_domain_nr(bus),
902 bus->number, PCI_SLOT(devfn),
903 PCI_FUNC(devfn));
904 return NULL;
905 }
906 }
907
908 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
909 return NULL;
910
911 dev = alloc_pci_dev();
912 if (!dev)
913 return NULL;
914
915 dev->bus = bus;
916 dev->sysdata = bus->sysdata;
917 dev->dev.parent = bus->bridge;
918 dev->dev.bus = &pci_bus_type;
919 dev->devfn = devfn;
920 dev->hdr_type = hdr_type & 0x7f;
921 dev->multifunction = !!(hdr_type & 0x80);
922 dev->vendor = l & 0xffff;
923 dev->device = (l >> 16) & 0xffff;
924 dev->cfg_size = pci_cfg_space_size(dev);
925 dev->error_state = pci_channel_io_normal;
926 set_pcie_port_type(dev);
927
928 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
929 set this higher, assuming the system even supports it. */
930 dev->dma_mask = 0xffffffff;
931 if (pci_setup_device(dev) < 0) {
932 kfree(dev);
933 return NULL;
934 }
935
936 return dev;
937 }
938
939 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
940 {
941 device_initialize(&dev->dev);
942 dev->dev.release = pci_release_dev;
943 pci_dev_get(dev);
944
945 set_dev_node(&dev->dev, pcibus_to_node(bus));
946 dev->dev.dma_mask = &dev->dma_mask;
947 dev->dev.dma_parms = &dev->dma_parms;
948 dev->dev.coherent_dma_mask = 0xffffffffull;
949
950 pci_set_dma_max_seg_size(dev, 65536);
951 pci_set_dma_seg_boundary(dev, 0xffffffff);
952
953 /* Fix up broken headers */
954 pci_fixup_device(pci_fixup_header, dev);
955
956 /*
957 * Add the device to our list of discovered devices
958 * and the bus list for fixup functions, etc.
959 */
960 INIT_LIST_HEAD(&dev->global_list);
961 down_write(&pci_bus_sem);
962 list_add_tail(&dev->bus_list, &bus->devices);
963 up_write(&pci_bus_sem);
964 }
965
966 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
967 {
968 struct pci_dev *dev;
969
970 dev = pci_scan_device(bus, devfn);
971 if (!dev)
972 return NULL;
973
974 pci_device_add(dev, bus);
975
976 return dev;
977 }
978 EXPORT_SYMBOL(pci_scan_single_device);
979
980 /**
981 * pci_scan_slot - scan a PCI slot on a bus for devices.
982 * @bus: PCI bus to scan
983 * @devfn: slot number to scan (must have zero function.)
984 *
985 * Scan a PCI slot on the specified PCI bus for devices, adding
986 * discovered devices to the @bus->devices list. New devices
987 * will have an empty dev->global_list head.
988 */
989 int pci_scan_slot(struct pci_bus *bus, int devfn)
990 {
991 int func, nr = 0;
992 int scan_all_fns;
993
994 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
995
996 for (func = 0; func < 8; func++, devfn++) {
997 struct pci_dev *dev;
998
999 dev = pci_scan_single_device(bus, devfn);
1000 if (dev) {
1001 nr++;
1002
1003 /*
1004 * If this is a single function device,
1005 * don't scan past the first function.
1006 */
1007 if (!dev->multifunction) {
1008 if (func > 0) {
1009 dev->multifunction = 1;
1010 } else {
1011 break;
1012 }
1013 }
1014 } else {
1015 if (func == 0 && !scan_all_fns)
1016 break;
1017 }
1018 }
1019 return nr;
1020 }
1021
1022 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1023 {
1024 unsigned int devfn, pass, max = bus->secondary;
1025 struct pci_dev *dev;
1026
1027 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1028
1029 /* Go find them, Rover! */
1030 for (devfn = 0; devfn < 0x100; devfn += 8)
1031 pci_scan_slot(bus, devfn);
1032
1033 /*
1034 * After performing arch-dependent fixup of the bus, look behind
1035 * all PCI-to-PCI bridges on this bus.
1036 */
1037 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1038 pcibios_fixup_bus(bus);
1039 for (pass=0; pass < 2; pass++)
1040 list_for_each_entry(dev, &bus->devices, bus_list) {
1041 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1042 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1043 max = pci_scan_bridge(bus, dev, max, pass);
1044 }
1045
1046 /*
1047 * We've scanned the bus and so we know all about what's on
1048 * the other side of any bridges that may be on this bus plus
1049 * any devices.
1050 *
1051 * Return how far we've got finding sub-buses.
1052 */
1053 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1054 pci_domain_nr(bus), bus->number, max);
1055 return max;
1056 }
1057
1058 struct pci_bus * pci_create_bus(struct device *parent,
1059 int bus, struct pci_ops *ops, void *sysdata)
1060 {
1061 int error;
1062 struct pci_bus *b;
1063 struct device *dev;
1064
1065 b = pci_alloc_bus();
1066 if (!b)
1067 return NULL;
1068
1069 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1070 if (!dev){
1071 kfree(b);
1072 return NULL;
1073 }
1074
1075 b->sysdata = sysdata;
1076 b->ops = ops;
1077
1078 if (pci_find_bus(pci_domain_nr(b), bus)) {
1079 /* If we already got to this bus through a different bridge, ignore it */
1080 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1081 goto err_out;
1082 }
1083
1084 down_write(&pci_bus_sem);
1085 list_add_tail(&b->node, &pci_root_buses);
1086 up_write(&pci_bus_sem);
1087
1088 memset(dev, 0, sizeof(*dev));
1089 dev->parent = parent;
1090 dev->release = pci_release_bus_bridge_dev;
1091 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1092 error = device_register(dev);
1093 if (error)
1094 goto dev_reg_err;
1095 b->bridge = get_device(dev);
1096
1097 b->dev.class = &pcibus_class;
1098 b->dev.parent = b->bridge;
1099 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1100 error = device_register(&b->dev);
1101 if (error)
1102 goto class_dev_reg_err;
1103 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1104 if (error)
1105 goto dev_create_file_err;
1106
1107 /* Create legacy_io and legacy_mem files for this bus */
1108 pci_create_legacy_files(b);
1109
1110 b->number = b->secondary = bus;
1111 b->resource[0] = &ioport_resource;
1112 b->resource[1] = &iomem_resource;
1113
1114 return b;
1115
1116 dev_create_file_err:
1117 device_unregister(&b->dev);
1118 class_dev_reg_err:
1119 device_unregister(dev);
1120 dev_reg_err:
1121 down_write(&pci_bus_sem);
1122 list_del(&b->node);
1123 up_write(&pci_bus_sem);
1124 err_out:
1125 kfree(dev);
1126 kfree(b);
1127 return NULL;
1128 }
1129
1130 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1131 int bus, struct pci_ops *ops, void *sysdata)
1132 {
1133 struct pci_bus *b;
1134
1135 b = pci_create_bus(parent, bus, ops, sysdata);
1136 if (b)
1137 b->subordinate = pci_scan_child_bus(b);
1138 return b;
1139 }
1140 EXPORT_SYMBOL(pci_scan_bus_parented);
1141
1142 #ifdef CONFIG_HOTPLUG
1143 EXPORT_SYMBOL(pci_add_new_bus);
1144 EXPORT_SYMBOL(pci_scan_slot);
1145 EXPORT_SYMBOL(pci_scan_bridge);
1146 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1147 #endif
1148
1149 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1150 {
1151 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1152 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1153
1154 if (a->bus->number < b->bus->number) return -1;
1155 else if (a->bus->number > b->bus->number) return 1;
1156
1157 if (a->devfn < b->devfn) return -1;
1158 else if (a->devfn > b->devfn) return 1;
1159
1160 return 0;
1161 }
1162
1163 /*
1164 * Yes, this forcably breaks the klist abstraction temporarily. It
1165 * just wants to sort the klist, not change reference counts and
1166 * take/drop locks rapidly in the process. It does all this while
1167 * holding the lock for the list, so objects can't otherwise be
1168 * added/removed while we're swizzling.
1169 */
1170 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1171 {
1172 struct list_head *pos;
1173 struct klist_node *n;
1174 struct device *dev;
1175 struct pci_dev *b;
1176
1177 list_for_each(pos, list) {
1178 n = container_of(pos, struct klist_node, n_node);
1179 dev = container_of(n, struct device, knode_bus);
1180 b = to_pci_dev(dev);
1181 if (pci_sort_bf_cmp(a, b) <= 0) {
1182 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1183 return;
1184 }
1185 }
1186 list_move_tail(&a->dev.knode_bus.n_node, list);
1187 }
1188
1189 static void __init pci_sort_breadthfirst_klist(void)
1190 {
1191 LIST_HEAD(sorted_devices);
1192 struct list_head *pos, *tmp;
1193 struct klist_node *n;
1194 struct device *dev;
1195 struct pci_dev *pdev;
1196 struct klist *device_klist;
1197
1198 device_klist = bus_get_device_klist(&pci_bus_type);
1199
1200 spin_lock(&device_klist->k_lock);
1201 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1202 n = container_of(pos, struct klist_node, n_node);
1203 dev = container_of(n, struct device, knode_bus);
1204 pdev = to_pci_dev(dev);
1205 pci_insertion_sort_klist(pdev, &sorted_devices);
1206 }
1207 list_splice(&sorted_devices, &device_klist->k_list);
1208 spin_unlock(&device_klist->k_lock);
1209 }
1210
1211 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1212 {
1213 struct pci_dev *b;
1214
1215 list_for_each_entry(b, list, global_list) {
1216 if (pci_sort_bf_cmp(a, b) <= 0) {
1217 list_move_tail(&a->global_list, &b->global_list);
1218 return;
1219 }
1220 }
1221 list_move_tail(&a->global_list, list);
1222 }
1223
1224 static void __init pci_sort_breadthfirst_devices(void)
1225 {
1226 LIST_HEAD(sorted_devices);
1227 struct pci_dev *dev, *tmp;
1228
1229 down_write(&pci_bus_sem);
1230 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1231 pci_insertion_sort_devices(dev, &sorted_devices);
1232 }
1233 list_splice(&sorted_devices, &pci_devices);
1234 up_write(&pci_bus_sem);
1235 }
1236
1237 void __init pci_sort_breadthfirst(void)
1238 {
1239 pci_sort_breadthfirst_devices();
1240 pci_sort_breadthfirst_klist();
1241 }
1242
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