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[PATCH] W1: possible cleanups
[linux-2.6/verdex.git] / drivers / scsi / megaraid / megaraid_sas.h
blob927d6ffef05f14c53367106e15fdbf9e21079c6c
1 /*
2 *
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
5 * Copyright (c) 2003-2005 LSI Logic Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * FILE : megaraid_sas.h
13 */
14
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
17
18 /**
19 * MegaRAID SAS Driver meta data
20 */
21 #define MEGASAS_VERSION "00.00.02.04"
22 #define MEGASAS_RELDATE "Feb 03, 2006"
23 #define MEGASAS_EXT_VERSION "Fri Feb 03 14:31:44 PST 2006"
24 /*
25 * =====================================
26 * MegaRAID SAS MFI firmware definitions
27 * =====================================
28 */
29
30 /*
31 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
32 * protocol between the software and firmware. Commands are issued using
33 * "message frames"
34 */
35
36 /**
37 * FW posts its state in upper 4 bits of outbound_msg_0 register
38 */
39 #define MFI_STATE_MASK 0xF0000000
40 #define MFI_STATE_UNDEFINED 0x00000000
41 #define MFI_STATE_BB_INIT 0x10000000
42 #define MFI_STATE_FW_INIT 0x40000000
43 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
44 #define MFI_STATE_FW_INIT_2 0x70000000
45 #define MFI_STATE_DEVICE_SCAN 0x80000000
46 #define MFI_STATE_FLUSH_CACHE 0xA0000000
47 #define MFI_STATE_READY 0xB0000000
48 #define MFI_STATE_OPERATIONAL 0xC0000000
49 #define MFI_STATE_FAULT 0xF0000000
50
51 #define MEGAMFI_FRAME_SIZE 64
52
53 /**
54 * During FW init, clear pending cmds & reset state using inbound_msg_0
55 *
56 * ABORT : Abort all pending cmds
57 * READY : Move from OPERATIONAL to READY state; discard queue info
58 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
59 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
60 */
61 #define MFI_INIT_ABORT 0x00000000
62 #define MFI_INIT_READY 0x00000002
63 #define MFI_INIT_MFIMODE 0x00000004
64 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
65 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE
66
67 /**
68 * MFI frame flags
69 */
70 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
71 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
72 #define MFI_FRAME_SGL32 0x0000
73 #define MFI_FRAME_SGL64 0x0002
74 #define MFI_FRAME_SENSE32 0x0000
75 #define MFI_FRAME_SENSE64 0x0004
76 #define MFI_FRAME_DIR_NONE 0x0000
77 #define MFI_FRAME_DIR_WRITE 0x0008
78 #define MFI_FRAME_DIR_READ 0x0010
79 #define MFI_FRAME_DIR_BOTH 0x0018
80
81 /**
82 * Definition for cmd_status
83 */
84 #define MFI_CMD_STATUS_POLL_MODE 0xFF
85
86 /**
87 * MFI command opcodes
88 */
89 #define MFI_CMD_INIT 0x00
90 #define MFI_CMD_LD_READ 0x01
91 #define MFI_CMD_LD_WRITE 0x02
92 #define MFI_CMD_LD_SCSI_IO 0x03
93 #define MFI_CMD_PD_SCSI_IO 0x04
94 #define MFI_CMD_DCMD 0x05
95 #define MFI_CMD_ABORT 0x06
96 #define MFI_CMD_SMP 0x07
97 #define MFI_CMD_STP 0x08
98
99 #define MR_DCMD_CTRL_GET_INFO 0x01010000
100
101 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
102 #define MR_FLUSH_CTRL_CACHE 0x01
103 #define MR_FLUSH_DISK_CACHE 0x02
104
105 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
106 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
107
108 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
109 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
110 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
111 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
112
113 #define MR_DCMD_CLUSTER 0x08000000
114 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
115 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
116
117 /**
118 * MFI command completion codes
119 */
120 enum MFI_STAT {
121 MFI_STAT_OK = 0x00,
122 MFI_STAT_INVALID_CMD = 0x01,
123 MFI_STAT_INVALID_DCMD = 0x02,
124 MFI_STAT_INVALID_PARAMETER = 0x03,
125 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
126 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
127 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
128 MFI_STAT_APP_IN_USE = 0x07,
129 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
130 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
131 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
132 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
133 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
134 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
135 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
136 MFI_STAT_FLASH_BUSY = 0x0f,
137 MFI_STAT_FLASH_ERROR = 0x10,
138 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
139 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
140 MFI_STAT_FLASH_NOT_OPEN = 0x13,
141 MFI_STAT_FLASH_NOT_STARTED = 0x14,
142 MFI_STAT_FLUSH_FAILED = 0x15,
143 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
144 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
145 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
146 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
147 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
148 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
149 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
150 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
151 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
152 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
153 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
154 MFI_STAT_MFC_HW_ERROR = 0x21,
155 MFI_STAT_NO_HW_PRESENT = 0x22,
156 MFI_STAT_NOT_FOUND = 0x23,
157 MFI_STAT_NOT_IN_ENCL = 0x24,
158 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
159 MFI_STAT_PD_TYPE_WRONG = 0x26,
160 MFI_STAT_PR_DISABLED = 0x27,
161 MFI_STAT_ROW_INDEX_INVALID = 0x28,
162 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
163 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
164 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
165 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
166 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
167 MFI_STAT_SCSI_IO_FAILED = 0x2e,
168 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
169 MFI_STAT_SHUTDOWN_FAILED = 0x30,
170 MFI_STAT_TIME_NOT_SET = 0x31,
171 MFI_STAT_WRONG_STATE = 0x32,
172 MFI_STAT_LD_OFFLINE = 0x33,
173 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
174 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
175 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
176 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
177 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
178
179 MFI_STAT_INVALID_STATUS = 0xFF
180 };
181
182 /*
183 * Number of mailbox bytes in DCMD message frame
184 */
185 #define MFI_MBOX_SIZE 12
186
187 enum MR_EVT_CLASS {
188
189 MR_EVT_CLASS_DEBUG = -2,
190 MR_EVT_CLASS_PROGRESS = -1,
191 MR_EVT_CLASS_INFO = 0,
192 MR_EVT_CLASS_WARNING = 1,
193 MR_EVT_CLASS_CRITICAL = 2,
194 MR_EVT_CLASS_FATAL = 3,
195 MR_EVT_CLASS_DEAD = 4,
196
197 };
198
199 enum MR_EVT_LOCALE {
200
201 MR_EVT_LOCALE_LD = 0x0001,
202 MR_EVT_LOCALE_PD = 0x0002,
203 MR_EVT_LOCALE_ENCL = 0x0004,
204 MR_EVT_LOCALE_BBU = 0x0008,
205 MR_EVT_LOCALE_SAS = 0x0010,
206 MR_EVT_LOCALE_CTRL = 0x0020,
207 MR_EVT_LOCALE_CONFIG = 0x0040,
208 MR_EVT_LOCALE_CLUSTER = 0x0080,
209 MR_EVT_LOCALE_ALL = 0xffff,
210
211 };
212
213 enum MR_EVT_ARGS {
214
215 MR_EVT_ARGS_NONE,
216 MR_EVT_ARGS_CDB_SENSE,
217 MR_EVT_ARGS_LD,
218 MR_EVT_ARGS_LD_COUNT,
219 MR_EVT_ARGS_LD_LBA,
220 MR_EVT_ARGS_LD_OWNER,
221 MR_EVT_ARGS_LD_LBA_PD_LBA,
222 MR_EVT_ARGS_LD_PROG,
223 MR_EVT_ARGS_LD_STATE,
224 MR_EVT_ARGS_LD_STRIP,
225 MR_EVT_ARGS_PD,
226 MR_EVT_ARGS_PD_ERR,
227 MR_EVT_ARGS_PD_LBA,
228 MR_EVT_ARGS_PD_LBA_LD,
229 MR_EVT_ARGS_PD_PROG,
230 MR_EVT_ARGS_PD_STATE,
231 MR_EVT_ARGS_PCI,
232 MR_EVT_ARGS_RATE,
233 MR_EVT_ARGS_STR,
234 MR_EVT_ARGS_TIME,
235 MR_EVT_ARGS_ECC,
236
237 };
238
239 /*
240 * SAS controller properties
241 */
242 struct megasas_ctrl_prop {
243
244 u16 seq_num;
245 u16 pred_fail_poll_interval;
246 u16 intr_throttle_count;
247 u16 intr_throttle_timeouts;
248 u8 rebuild_rate;
249 u8 patrol_read_rate;
250 u8 bgi_rate;
251 u8 cc_rate;
252 u8 recon_rate;
253 u8 cache_flush_interval;
254 u8 spinup_drv_count;
255 u8 spinup_delay;
256 u8 cluster_enable;
257 u8 coercion_mode;
258 u8 alarm_enable;
259 u8 disable_auto_rebuild;
260 u8 disable_battery_warn;
261 u8 ecc_bucket_size;
262 u16 ecc_bucket_leak_rate;
263 u8 restore_hotspare_on_insertion;
264 u8 expose_encl_devices;
265 u8 reserved[38];
266
267 } __attribute__ ((packed));
268
269 /*
270 * SAS controller information
271 */
272 struct megasas_ctrl_info {
273
274 /*
275 * PCI device information
276 */
277 struct {
278
279 u16 vendor_id;
280 u16 device_id;
281 u16 sub_vendor_id;
282 u16 sub_device_id;
283 u8 reserved[24];
284
285 } __attribute__ ((packed)) pci;
286
287 /*
288 * Host interface information
289 */
290 struct {
291
292 u8 PCIX:1;
293 u8 PCIE:1;
294 u8 iSCSI:1;
295 u8 SAS_3G:1;
296 u8 reserved_0:4;
297 u8 reserved_1[6];
298 u8 port_count;
299 u64 port_addr[8];
300
301 } __attribute__ ((packed)) host_interface;
302
303 /*
304 * Device (backend) interface information
305 */
306 struct {
307
308 u8 SPI:1;
309 u8 SAS_3G:1;
310 u8 SATA_1_5G:1;
311 u8 SATA_3G:1;
312 u8 reserved_0:4;
313 u8 reserved_1[6];
314 u8 port_count;
315 u64 port_addr[8];
316
317 } __attribute__ ((packed)) device_interface;
318
319 /*
320 * List of components residing in flash. All str are null terminated
321 */
322 u32 image_check_word;
323 u32 image_component_count;
324
325 struct {
326
327 char name[8];
328 char version[32];
329 char build_date[16];
330 char built_time[16];
331
332 } __attribute__ ((packed)) image_component[8];
333
334 /*
335 * List of flash components that have been flashed on the card, but
336 * are not in use, pending reset of the adapter. This list will be
337 * empty if a flash operation has not occurred. All stings are null
338 * terminated
339 */
340 u32 pending_image_component_count;
341
342 struct {
343
344 char name[8];
345 char version[32];
346 char build_date[16];
347 char build_time[16];
348
349 } __attribute__ ((packed)) pending_image_component[8];
350
351 u8 max_arms;
352 u8 max_spans;
353 u8 max_arrays;
354 u8 max_lds;
355
356 char product_name[80];
357 char serial_no[32];
358
359 /*
360 * Other physical/controller/operation information. Indicates the
361 * presence of the hardware
362 */
363 struct {
364
365 u32 bbu:1;
366 u32 alarm:1;
367 u32 nvram:1;
368 u32 uart:1;
369 u32 reserved:28;
370
371 } __attribute__ ((packed)) hw_present;
372
373 u32 current_fw_time;
374
375 /*
376 * Maximum data transfer sizes
377 */
378 u16 max_concurrent_cmds;
379 u16 max_sge_count;
380 u32 max_request_size;
381
382 /*
383 * Logical and physical device counts
384 */
385 u16 ld_present_count;
386 u16 ld_degraded_count;
387 u16 ld_offline_count;
388
389 u16 pd_present_count;
390 u16 pd_disk_present_count;
391 u16 pd_disk_pred_failure_count;
392 u16 pd_disk_failed_count;
393
394 /*
395 * Memory size information
396 */
397 u16 nvram_size;
398 u16 memory_size;
399 u16 flash_size;
400
401 /*
402 * Error counters
403 */
404 u16 mem_correctable_error_count;
405 u16 mem_uncorrectable_error_count;
406
407 /*
408 * Cluster information
409 */
410 u8 cluster_permitted;
411 u8 cluster_active;
412
413 /*
414 * Additional max data transfer sizes
415 */
416 u16 max_strips_per_io;
417
418 /*
419 * Controller capabilities structures
420 */
421 struct {
422
423 u32 raid_level_0:1;
424 u32 raid_level_1:1;
425 u32 raid_level_5:1;
426 u32 raid_level_1E:1;
427 u32 raid_level_6:1;
428 u32 reserved:27;
429
430 } __attribute__ ((packed)) raid_levels;
431
432 struct {
433
434 u32 rbld_rate:1;
435 u32 cc_rate:1;
436 u32 bgi_rate:1;
437 u32 recon_rate:1;
438 u32 patrol_rate:1;
439 u32 alarm_control:1;
440 u32 cluster_supported:1;
441 u32 bbu:1;
442 u32 spanning_allowed:1;
443 u32 dedicated_hotspares:1;
444 u32 revertible_hotspares:1;
445 u32 foreign_config_import:1;
446 u32 self_diagnostic:1;
447 u32 mixed_redundancy_arr:1;
448 u32 global_hot_spares:1;
449 u32 reserved:17;
450
451 } __attribute__ ((packed)) adapter_operations;
452
453 struct {
454
455 u32 read_policy:1;
456 u32 write_policy:1;
457 u32 io_policy:1;
458 u32 access_policy:1;
459 u32 disk_cache_policy:1;
460 u32 reserved:27;
461
462 } __attribute__ ((packed)) ld_operations;
463
464 struct {
465
466 u8 min;
467 u8 max;
468 u8 reserved[2];
469
470 } __attribute__ ((packed)) stripe_sz_ops;
471
472 struct {
473
474 u32 force_online:1;
475 u32 force_offline:1;
476 u32 force_rebuild:1;
477 u32 reserved:29;
478
479 } __attribute__ ((packed)) pd_operations;
480
481 struct {
482
483 u32 ctrl_supports_sas:1;
484 u32 ctrl_supports_sata:1;
485 u32 allow_mix_in_encl:1;
486 u32 allow_mix_in_ld:1;
487 u32 allow_sata_in_cluster:1;
488 u32 reserved:27;
489
490 } __attribute__ ((packed)) pd_mix_support;
491
492 /*
493 * Define ECC single-bit-error bucket information
494 */
495 u8 ecc_bucket_count;
496 u8 reserved_2[11];
497
498 /*
499 * Include the controller properties (changeable items)
500 */
501 struct megasas_ctrl_prop properties;
502
503 /*
504 * Define FW pkg version (set in envt v'bles on OEM basis)
505 */
506 char package_version[0x60];
507
508 u8 pad[0x800 - 0x6a0];
509
510 } __attribute__ ((packed));
511
512 /*
513 * ===============================
514 * MegaRAID SAS driver definitions
515 * ===============================
516 */
517 #define MEGASAS_MAX_PD_CHANNELS 2
518 #define MEGASAS_MAX_LD_CHANNELS 2
519 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
520 MEGASAS_MAX_LD_CHANNELS)
521 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
522 #define MEGASAS_DEFAULT_INIT_ID -1
523 #define MEGASAS_MAX_LUN 8
524 #define MEGASAS_MAX_LD 64
525
526 /*
527 * When SCSI mid-layer calls driver's reset routine, driver waits for
528 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
529 * that the driver cannot _actually_ abort or reset pending commands. While
530 * it is waiting for the commands to complete, it prints a diagnostic message
531 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
532 */
533 #define MEGASAS_RESET_WAIT_TIME 180
534 #define MEGASAS_RESET_NOTICE_INTERVAL 5
535
536 #define MEGASAS_IOCTL_CMD 0
537
538 /*
539 * FW reports the maximum of number of commands that it can accept (maximum
540 * commands that can be outstanding) at any time. The driver must report a
541 * lower number to the mid layer because it can issue a few internal commands
542 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
543 * is shown below
544 */
545 #define MEGASAS_INT_CMDS 32
546
547 /*
548 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
549 * SGLs based on the size of dma_addr_t
550 */
551 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
552
553 #define MFI_OB_INTR_STATUS_MASK 0x00000002
554 #define MFI_POLL_TIMEOUT_SECS 10
555
556 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
557 #define PCI_DEVICE_ID_LSI_SAS1078R 0x00000060
558
559 struct megasas_register_set {
560 u32 reserved_0[4]; /*0000h*/
561
562 u32 inbound_msg_0; /*0010h*/
563 u32 inbound_msg_1; /*0014h*/
564 u32 outbound_msg_0; /*0018h*/
565 u32 outbound_msg_1; /*001Ch*/
566
567 u32 inbound_doorbell; /*0020h*/
568 u32 inbound_intr_status; /*0024h*/
569 u32 inbound_intr_mask; /*0028h*/
570
571 u32 outbound_doorbell; /*002Ch*/
572 u32 outbound_intr_status; /*0030h*/
573 u32 outbound_intr_mask; /*0034h*/
574
575 u32 reserved_1[2]; /*0038h*/
576
577 u32 inbound_queue_port; /*0040h*/
578 u32 outbound_queue_port; /*0044h*/
579
580 u32 reserved_2[22]; /*0048h*/
581
582 u32 outbound_doorbell_clear; /*00A0h*/
583
584 u32 reserved_3[3]; /*00A4h*/
585
586 u32 outbound_scratch_pad ; /*00B0h*/
587
588 u32 reserved_4[3]; /*00B4h*/
589
590 u32 inbound_low_queue_port ; /*00C0h*/
591
592 u32 inbound_high_queue_port ; /*00C4h*/
593
594 u32 reserved_5; /*00C8h*/
595 u32 index_registers[820]; /*00CCh*/
596
597 } __attribute__ ((packed));
598
599 struct megasas_sge32 {
600
601 u32 phys_addr;
602 u32 length;
603
604 } __attribute__ ((packed));
605
606 struct megasas_sge64 {
607
608 u64 phys_addr;
609 u32 length;
610
611 } __attribute__ ((packed));
612
613 union megasas_sgl {
614
615 struct megasas_sge32 sge32[1];
616 struct megasas_sge64 sge64[1];
617
618 } __attribute__ ((packed));
619
620 struct megasas_header {
621
622 u8 cmd; /*00h */
623 u8 sense_len; /*01h */
624 u8 cmd_status; /*02h */
625 u8 scsi_status; /*03h */
626
627 u8 target_id; /*04h */
628 u8 lun; /*05h */
629 u8 cdb_len; /*06h */
630 u8 sge_count; /*07h */
631
632 u32 context; /*08h */
633 u32 pad_0; /*0Ch */
634
635 u16 flags; /*10h */
636 u16 timeout; /*12h */
637 u32 data_xferlen; /*14h */
638
639 } __attribute__ ((packed));
640
641 union megasas_sgl_frame {
642
643 struct megasas_sge32 sge32[8];
644 struct megasas_sge64 sge64[5];
645
646 } __attribute__ ((packed));
647
648 struct megasas_init_frame {
649
650 u8 cmd; /*00h */
651 u8 reserved_0; /*01h */
652 u8 cmd_status; /*02h */
653
654 u8 reserved_1; /*03h */
655 u32 reserved_2; /*04h */
656
657 u32 context; /*08h */
658 u32 pad_0; /*0Ch */
659
660 u16 flags; /*10h */
661 u16 reserved_3; /*12h */
662 u32 data_xfer_len; /*14h */
663
664 u32 queue_info_new_phys_addr_lo; /*18h */
665 u32 queue_info_new_phys_addr_hi; /*1Ch */
666 u32 queue_info_old_phys_addr_lo; /*20h */
667 u32 queue_info_old_phys_addr_hi; /*24h */
668
669 u32 reserved_4[6]; /*28h */
670
671 } __attribute__ ((packed));
672
673 struct megasas_init_queue_info {
674
675 u32 init_flags; /*00h */
676 u32 reply_queue_entries; /*04h */
677
678 u32 reply_queue_start_phys_addr_lo; /*08h */
679 u32 reply_queue_start_phys_addr_hi; /*0Ch */
680 u32 producer_index_phys_addr_lo; /*10h */
681 u32 producer_index_phys_addr_hi; /*14h */
682 u32 consumer_index_phys_addr_lo; /*18h */
683 u32 consumer_index_phys_addr_hi; /*1Ch */
684
685 } __attribute__ ((packed));
686
687 struct megasas_io_frame {
688
689 u8 cmd; /*00h */
690 u8 sense_len; /*01h */
691 u8 cmd_status; /*02h */
692 u8 scsi_status; /*03h */
693
694 u8 target_id; /*04h */
695 u8 access_byte; /*05h */
696 u8 reserved_0; /*06h */
697 u8 sge_count; /*07h */
698
699 u32 context; /*08h */
700 u32 pad_0; /*0Ch */
701
702 u16 flags; /*10h */
703 u16 timeout; /*12h */
704 u32 lba_count; /*14h */
705
706 u32 sense_buf_phys_addr_lo; /*18h */
707 u32 sense_buf_phys_addr_hi; /*1Ch */
708
709 u32 start_lba_lo; /*20h */
710 u32 start_lba_hi; /*24h */
711
712 union megasas_sgl sgl; /*28h */
713
714 } __attribute__ ((packed));
715
716 struct megasas_pthru_frame {
717
718 u8 cmd; /*00h */
719 u8 sense_len; /*01h */
720 u8 cmd_status; /*02h */
721 u8 scsi_status; /*03h */
722
723 u8 target_id; /*04h */
724 u8 lun; /*05h */
725 u8 cdb_len; /*06h */
726 u8 sge_count; /*07h */
727
728 u32 context; /*08h */
729 u32 pad_0; /*0Ch */
730
731 u16 flags; /*10h */
732 u16 timeout; /*12h */
733 u32 data_xfer_len; /*14h */
734
735 u32 sense_buf_phys_addr_lo; /*18h */
736 u32 sense_buf_phys_addr_hi; /*1Ch */
737
738 u8 cdb[16]; /*20h */
739 union megasas_sgl sgl; /*30h */
740
741 } __attribute__ ((packed));
742
743 struct megasas_dcmd_frame {
744
745 u8 cmd; /*00h */
746 u8 reserved_0; /*01h */
747 u8 cmd_status; /*02h */
748 u8 reserved_1[4]; /*03h */
749 u8 sge_count; /*07h */
750
751 u32 context; /*08h */
752 u32 pad_0; /*0Ch */
753
754 u16 flags; /*10h */
755 u16 timeout; /*12h */
756
757 u32 data_xfer_len; /*14h */
758 u32 opcode; /*18h */
759
760 union { /*1Ch */
761 u8 b[12];
762 u16 s[6];
763 u32 w[3];
764 } mbox;
765
766 union megasas_sgl sgl; /*28h */
767
768 } __attribute__ ((packed));
769
770 struct megasas_abort_frame {
771
772 u8 cmd; /*00h */
773 u8 reserved_0; /*01h */
774 u8 cmd_status; /*02h */
775
776 u8 reserved_1; /*03h */
777 u32 reserved_2; /*04h */
778
779 u32 context; /*08h */
780 u32 pad_0; /*0Ch */
781
782 u16 flags; /*10h */
783 u16 reserved_3; /*12h */
784 u32 reserved_4; /*14h */
785
786 u32 abort_context; /*18h */
787 u32 pad_1; /*1Ch */
788
789 u32 abort_mfi_phys_addr_lo; /*20h */
790 u32 abort_mfi_phys_addr_hi; /*24h */
791
792 u32 reserved_5[6]; /*28h */
793
794 } __attribute__ ((packed));
795
796 struct megasas_smp_frame {
797
798 u8 cmd; /*00h */
799 u8 reserved_1; /*01h */
800 u8 cmd_status; /*02h */
801 u8 connection_status; /*03h */
802
803 u8 reserved_2[3]; /*04h */
804 u8 sge_count; /*07h */
805
806 u32 context; /*08h */
807 u32 pad_0; /*0Ch */
808
809 u16 flags; /*10h */
810 u16 timeout; /*12h */
811
812 u32 data_xfer_len; /*14h */
813 u64 sas_addr; /*18h */
814
815 union {
816 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
817 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
818 } sgl;
819
820 } __attribute__ ((packed));
821
822 struct megasas_stp_frame {
823
824 u8 cmd; /*00h */
825 u8 reserved_1; /*01h */
826 u8 cmd_status; /*02h */
827 u8 reserved_2; /*03h */
828
829 u8 target_id; /*04h */
830 u8 reserved_3[2]; /*05h */
831 u8 sge_count; /*07h */
832
833 u32 context; /*08h */
834 u32 pad_0; /*0Ch */
835
836 u16 flags; /*10h */
837 u16 timeout; /*12h */
838
839 u32 data_xfer_len; /*14h */
840
841 u16 fis[10]; /*18h */
842 u32 stp_flags;
843
844 union {
845 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
846 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
847 } sgl;
848
849 } __attribute__ ((packed));
850
851 union megasas_frame {
852
853 struct megasas_header hdr;
854 struct megasas_init_frame init;
855 struct megasas_io_frame io;
856 struct megasas_pthru_frame pthru;
857 struct megasas_dcmd_frame dcmd;
858 struct megasas_abort_frame abort;
859 struct megasas_smp_frame smp;
860 struct megasas_stp_frame stp;
861
862 u8 raw_bytes[64];
863 };
864
865 struct megasas_cmd;
866
867 union megasas_evt_class_locale {
868
869 struct {
870 u16 locale;
871 u8 reserved;
872 s8 class;
873 } __attribute__ ((packed)) members;
874
875 u32 word;
876
877 } __attribute__ ((packed));
878
879 struct megasas_evt_log_info {
880 u32 newest_seq_num;
881 u32 oldest_seq_num;
882 u32 clear_seq_num;
883 u32 shutdown_seq_num;
884 u32 boot_seq_num;
885
886 } __attribute__ ((packed));
887
888 struct megasas_progress {
889
890 u16 progress;
891 u16 elapsed_seconds;
892
893 } __attribute__ ((packed));
894
895 struct megasas_evtarg_ld {
896
897 u16 target_id;
898 u8 ld_index;
899 u8 reserved;
900
901 } __attribute__ ((packed));
902
903 struct megasas_evtarg_pd {
904 u16 device_id;
905 u8 encl_index;
906 u8 slot_number;
907
908 } __attribute__ ((packed));
909
910 struct megasas_evt_detail {
911
912 u32 seq_num;
913 u32 time_stamp;
914 u32 code;
915 union megasas_evt_class_locale cl;
916 u8 arg_type;
917 u8 reserved1[15];
918
919 union {
920 struct {
921 struct megasas_evtarg_pd pd;
922 u8 cdb_length;
923 u8 sense_length;
924 u8 reserved[2];
925 u8 cdb[16];
926 u8 sense[64];
927 } __attribute__ ((packed)) cdbSense;
928
929 struct megasas_evtarg_ld ld;
930
931 struct {
932 struct megasas_evtarg_ld ld;
933 u64 count;
934 } __attribute__ ((packed)) ld_count;
935
936 struct {
937 u64 lba;
938 struct megasas_evtarg_ld ld;
939 } __attribute__ ((packed)) ld_lba;
940
941 struct {
942 struct megasas_evtarg_ld ld;
943 u32 prevOwner;
944 u32 newOwner;
945 } __attribute__ ((packed)) ld_owner;
946
947 struct {
948 u64 ld_lba;
949 u64 pd_lba;
950 struct megasas_evtarg_ld ld;
951 struct megasas_evtarg_pd pd;
952 } __attribute__ ((packed)) ld_lba_pd_lba;
953
954 struct {
955 struct megasas_evtarg_ld ld;
956 struct megasas_progress prog;
957 } __attribute__ ((packed)) ld_prog;
958
959 struct {
960 struct megasas_evtarg_ld ld;
961 u32 prev_state;
962 u32 new_state;
963 } __attribute__ ((packed)) ld_state;
964
965 struct {
966 u64 strip;
967 struct megasas_evtarg_ld ld;
968 } __attribute__ ((packed)) ld_strip;
969
970 struct megasas_evtarg_pd pd;
971
972 struct {
973 struct megasas_evtarg_pd pd;
974 u32 err;
975 } __attribute__ ((packed)) pd_err;
976
977 struct {
978 u64 lba;
979 struct megasas_evtarg_pd pd;
980 } __attribute__ ((packed)) pd_lba;
981
982 struct {
983 u64 lba;
984 struct megasas_evtarg_pd pd;
985 struct megasas_evtarg_ld ld;
986 } __attribute__ ((packed)) pd_lba_ld;
987
988 struct {
989 struct megasas_evtarg_pd pd;
990 struct megasas_progress prog;
991 } __attribute__ ((packed)) pd_prog;
992
993 struct {
994 struct megasas_evtarg_pd pd;
995 u32 prevState;
996 u32 newState;
997 } __attribute__ ((packed)) pd_state;
998
999 struct {
1000 u16 vendorId;
1001 u16 deviceId;
1002 u16 subVendorId;
1003 u16 subDeviceId;
1004 } __attribute__ ((packed)) pci;
1005
1006 u32 rate;
1007 char str[96];
1008
1009 struct {
1010 u32 rtc;
1011 u32 elapsedSeconds;
1012 } __attribute__ ((packed)) time;
1013
1014 struct {
1015 u32 ecar;
1016 u32 elog;
1017 char str[64];
1018 } __attribute__ ((packed)) ecc;
1019
1020 u8 b[96];
1021 u16 s[48];
1022 u32 w[24];
1023 u64 d[12];
1024 } args;
1025
1026 char description[128];
1027
1028 } __attribute__ ((packed));
1029
1030 struct megasas_instance_template {
1031 void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1032
1033 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1034
1035 int (*clear_intr)(struct megasas_register_set __iomem *);
1036
1037 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1038 };
1039
1040 struct megasas_instance {
1041
1042 u32 *producer;
1043 dma_addr_t producer_h;
1044 u32 *consumer;
1045 dma_addr_t consumer_h;
1046
1047 u32 *reply_queue;
1048 dma_addr_t reply_queue_h;
1049
1050 unsigned long base_addr;
1051 struct megasas_register_set __iomem *reg_set;
1052
1053 s8 init_id;
1054 u8 reserved[3];
1055
1056 u16 max_num_sge;
1057 u16 max_fw_cmds;
1058 u32 max_sectors_per_req;
1059
1060 struct megasas_cmd **cmd_list;
1061 struct list_head cmd_pool;
1062 spinlock_t cmd_pool_lock;
1063 struct dma_pool *frame_dma_pool;
1064 struct dma_pool *sense_dma_pool;
1065
1066 struct megasas_evt_detail *evt_detail;
1067 dma_addr_t evt_detail_h;
1068 struct megasas_cmd *aen_cmd;
1069 struct semaphore aen_mutex;
1070 struct semaphore ioctl_sem;
1071
1072 struct Scsi_Host *host;
1073
1074 wait_queue_head_t int_cmd_wait_q;
1075 wait_queue_head_t abort_cmd_wait_q;
1076
1077 struct pci_dev *pdev;
1078 u32 unique_id;
1079
1080 atomic_t fw_outstanding;
1081 u32 hw_crit_error;
1082
1083 struct megasas_instance_template *instancet;
1084 };
1085
1086 #define MEGASAS_IS_LOGICAL(scp) \
1087 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1088
1089 #define MEGASAS_DEV_INDEX(inst, scp) \
1090 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1091 scp->device->id
1092
1093 struct megasas_cmd {
1094
1095 union megasas_frame *frame;
1096 dma_addr_t frame_phys_addr;
1097 u8 *sense;
1098 dma_addr_t sense_phys_addr;
1099
1100 u32 index;
1101 u8 sync_cmd;
1102 u8 cmd_status;
1103 u16 abort_aen;
1104
1105 struct list_head list;
1106 struct scsi_cmnd *scmd;
1107 struct megasas_instance *instance;
1108 u32 frame_count;
1109 };
1110
1111 #define MAX_MGMT_ADAPTERS 1024
1112 #define MAX_IOCTL_SGE 16
1113
1114 struct megasas_iocpacket {
1115
1116 u16 host_no;
1117 u16 __pad1;
1118 u32 sgl_off;
1119 u32 sge_count;
1120 u32 sense_off;
1121 u32 sense_len;
1122 union {
1123 u8 raw[128];
1124 struct megasas_header hdr;
1125 } frame;
1126
1127 struct iovec sgl[MAX_IOCTL_SGE];
1128
1129 } __attribute__ ((packed));
1130
1131 struct megasas_aen {
1132 u16 host_no;
1133 u16 __pad1;
1134 u32 seq_num;
1135 u32 class_locale_word;
1136 } __attribute__ ((packed));
1137
1138 #ifdef CONFIG_COMPAT
1139 struct compat_megasas_iocpacket {
1140 u16 host_no;
1141 u16 __pad1;
1142 u32 sgl_off;
1143 u32 sge_count;
1144 u32 sense_off;
1145 u32 sense_len;
1146 union {
1147 u8 raw[128];
1148 struct megasas_header hdr;
1149 } frame;
1150 struct compat_iovec sgl[MAX_IOCTL_SGE];
1151 } __attribute__ ((packed));
1152
1153 #endif
1154
1155 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1156 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1157 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1158
1159 struct megasas_mgmt_info {
1160
1161 u16 count;
1162 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1163 int max_index;
1164 };
1165
1166 #endif /*LSI_MEGARAID_SAS_H */
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