2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu
21 * Technically, updating td->status here is a race, but it's not really a
22 * problem. The worst that can happen is that we set the IOC bit again
23 * generating a spurious interrupt. We could fix this by creating another
24 * QH and leaving the IOC bit always set, but then we would have to play
25 * games with the FSBR code to make sure we get the correct order in all
26 * the cases. I don't think it's worth the effort
28 static void uhci_set_next_interrupt(struct uhci_hcd
*uhci
)
31 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
32 uhci
->term_td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
35 static inline void uhci_clear_next_interrupt(struct uhci_hcd
*uhci
)
37 uhci
->term_td
->status
&= ~cpu_to_le32(TD_CTRL_IOC
);
42 * Full-Speed Bandwidth Reclamation (FSBR).
43 * We turn on FSBR whenever a queue that wants it is advancing,
44 * and leave it on for a short time thereafter.
46 static void uhci_fsbr_on(struct uhci_hcd
*uhci
)
49 uhci
->skel_term_qh
->link
= cpu_to_le32(
50 uhci
->skel_fs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
53 static void uhci_fsbr_off(struct uhci_hcd
*uhci
)
56 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;
59 static void uhci_add_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
61 struct urb_priv
*urbp
= urb
->hcpriv
;
63 if (!(urb
->transfer_flags
& URB_NO_FSBR
))
67 static void uhci_urbp_wants_fsbr(struct uhci_hcd
*uhci
, struct urb_priv
*urbp
)
70 uhci
->fsbr_is_wanted
= 1;
71 if (!uhci
->fsbr_is_on
)
73 else if (uhci
->fsbr_expiring
) {
74 uhci
->fsbr_expiring
= 0;
75 del_timer(&uhci
->fsbr_timer
);
80 static void uhci_fsbr_timeout(unsigned long _uhci
)
82 struct uhci_hcd
*uhci
= (struct uhci_hcd
*) _uhci
;
85 spin_lock_irqsave(&uhci
->lock
, flags
);
86 if (uhci
->fsbr_expiring
) {
87 uhci
->fsbr_expiring
= 0;
90 spin_unlock_irqrestore(&uhci
->lock
, flags
);
94 static struct uhci_td
*uhci_alloc_td(struct uhci_hcd
*uhci
)
96 dma_addr_t dma_handle
;
99 td
= dma_pool_alloc(uhci
->td_pool
, GFP_ATOMIC
, &dma_handle
);
103 td
->dma_handle
= dma_handle
;
106 INIT_LIST_HEAD(&td
->list
);
107 INIT_LIST_HEAD(&td
->fl_list
);
112 static void uhci_free_td(struct uhci_hcd
*uhci
, struct uhci_td
*td
)
114 if (!list_empty(&td
->list
))
115 dev_warn(uhci_dev(uhci
), "td %p still in list!\n", td
);
116 if (!list_empty(&td
->fl_list
))
117 dev_warn(uhci_dev(uhci
), "td %p still in fl_list!\n", td
);
119 dma_pool_free(uhci
->td_pool
, td
, td
->dma_handle
);
122 static inline void uhci_fill_td(struct uhci_td
*td
, u32 status
,
123 u32 token
, u32 buffer
)
125 td
->status
= cpu_to_le32(status
);
126 td
->token
= cpu_to_le32(token
);
127 td
->buffer
= cpu_to_le32(buffer
);
130 static void uhci_add_td_to_urbp(struct uhci_td
*td
, struct urb_priv
*urbp
)
132 list_add_tail(&td
->list
, &urbp
->td_list
);
135 static void uhci_remove_td_from_urbp(struct uhci_td
*td
)
137 list_del_init(&td
->list
);
141 * We insert Isochronous URBs directly into the frame list at the beginning
143 static inline void uhci_insert_td_in_frame_list(struct uhci_hcd
*uhci
,
144 struct uhci_td
*td
, unsigned framenum
)
146 framenum
&= (UHCI_NUMFRAMES
- 1);
148 td
->frame
= framenum
;
150 /* Is there a TD already mapped there? */
151 if (uhci
->frame_cpu
[framenum
]) {
152 struct uhci_td
*ftd
, *ltd
;
154 ftd
= uhci
->frame_cpu
[framenum
];
155 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
157 list_add_tail(&td
->fl_list
, &ftd
->fl_list
);
159 td
->link
= ltd
->link
;
161 ltd
->link
= cpu_to_le32(td
->dma_handle
);
163 td
->link
= uhci
->frame
[framenum
];
165 uhci
->frame
[framenum
] = cpu_to_le32(td
->dma_handle
);
166 uhci
->frame_cpu
[framenum
] = td
;
170 static inline void uhci_remove_td_from_frame_list(struct uhci_hcd
*uhci
,
173 /* If it's not inserted, don't remove it */
174 if (td
->frame
== -1) {
175 WARN_ON(!list_empty(&td
->fl_list
));
179 if (uhci
->frame_cpu
[td
->frame
] == td
) {
180 if (list_empty(&td
->fl_list
)) {
181 uhci
->frame
[td
->frame
] = td
->link
;
182 uhci
->frame_cpu
[td
->frame
] = NULL
;
186 ntd
= list_entry(td
->fl_list
.next
, struct uhci_td
, fl_list
);
187 uhci
->frame
[td
->frame
] = cpu_to_le32(ntd
->dma_handle
);
188 uhci
->frame_cpu
[td
->frame
] = ntd
;
193 ptd
= list_entry(td
->fl_list
.prev
, struct uhci_td
, fl_list
);
194 ptd
->link
= td
->link
;
197 list_del_init(&td
->fl_list
);
201 static inline void uhci_remove_tds_from_frame(struct uhci_hcd
*uhci
,
202 unsigned int framenum
)
204 struct uhci_td
*ftd
, *ltd
;
206 framenum
&= (UHCI_NUMFRAMES
- 1);
208 ftd
= uhci
->frame_cpu
[framenum
];
210 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
211 uhci
->frame
[framenum
] = ltd
->link
;
212 uhci
->frame_cpu
[framenum
] = NULL
;
214 while (!list_empty(&ftd
->fl_list
))
215 list_del_init(ftd
->fl_list
.prev
);
220 * Remove all the TDs for an Isochronous URB from the frame list
222 static void uhci_unlink_isochronous_tds(struct uhci_hcd
*uhci
, struct urb
*urb
)
224 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
227 list_for_each_entry(td
, &urbp
->td_list
, list
)
228 uhci_remove_td_from_frame_list(uhci
, td
);
231 static struct uhci_qh
*uhci_alloc_qh(struct uhci_hcd
*uhci
,
232 struct usb_device
*udev
, struct usb_host_endpoint
*hep
)
234 dma_addr_t dma_handle
;
237 qh
= dma_pool_alloc(uhci
->qh_pool
, GFP_ATOMIC
, &dma_handle
);
241 memset(qh
, 0, sizeof(*qh
));
242 qh
->dma_handle
= dma_handle
;
244 qh
->element
= UHCI_PTR_TERM
;
245 qh
->link
= UHCI_PTR_TERM
;
247 INIT_LIST_HEAD(&qh
->queue
);
248 INIT_LIST_HEAD(&qh
->node
);
250 if (udev
) { /* Normal QH */
251 qh
->dummy_td
= uhci_alloc_td(uhci
);
253 dma_pool_free(uhci
->qh_pool
, qh
, dma_handle
);
256 qh
->state
= QH_STATE_IDLE
;
260 qh
->type
= hep
->desc
.bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
;
262 } else { /* Skeleton QH */
263 qh
->state
= QH_STATE_ACTIVE
;
269 static void uhci_free_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
271 WARN_ON(qh
->state
!= QH_STATE_IDLE
&& qh
->udev
);
272 if (!list_empty(&qh
->queue
))
273 dev_warn(uhci_dev(uhci
), "qh %p list not empty!\n", qh
);
277 qh
->hep
->hcpriv
= NULL
;
278 uhci_free_td(uhci
, qh
->dummy_td
);
280 dma_pool_free(uhci
->qh_pool
, qh
, qh
->dma_handle
);
284 * When a queue is stopped and a dequeued URB is given back, adjust
285 * the previous TD link (if the URB isn't first on the queue) or
286 * save its toggle value (if it is first and is currently executing).
288 * Returns 0 if the URB should not yet be given back, 1 otherwise.
290 static int uhci_cleanup_queue(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
293 struct urb_priv
*urbp
= urb
->hcpriv
;
297 /* Isochronous pipes don't use toggles and their TD link pointers
298 * get adjusted during uhci_urb_dequeue(). But since their queues
299 * cannot truly be stopped, we have to watch out for dequeues
300 * occurring after the nominal unlink frame. */
301 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
) {
302 ret
= (uhci
->frame_number
+ uhci
->is_stopped
!=
307 /* If the URB isn't first on its queue, adjust the link pointer
308 * of the last TD in the previous URB. The toggle doesn't need
309 * to be saved since this URB can't be executing yet. */
310 if (qh
->queue
.next
!= &urbp
->node
) {
311 struct urb_priv
*purbp
;
314 purbp
= list_entry(urbp
->node
.prev
, struct urb_priv
, node
);
315 WARN_ON(list_empty(&purbp
->td_list
));
316 ptd
= list_entry(purbp
->td_list
.prev
, struct uhci_td
,
318 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
,
320 ptd
->link
= td
->link
;
324 /* If the QH element pointer is UHCI_PTR_TERM then then currently
325 * executing URB has already been unlinked, so this one isn't it. */
326 if (qh_element(qh
) == UHCI_PTR_TERM
)
328 qh
->element
= UHCI_PTR_TERM
;
330 /* Control pipes have to worry about toggles */
331 if (qh
->type
== USB_ENDPOINT_XFER_CONTROL
)
334 /* Save the next toggle value */
335 WARN_ON(list_empty(&urbp
->td_list
));
336 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
338 qh
->initial_toggle
= uhci_toggle(td_token(td
));
345 * Fix up the data toggles for URBs in a queue, when one of them
346 * terminates early (short transfer, error, or dequeued).
348 static void uhci_fixup_toggles(struct uhci_qh
*qh
, int skip_first
)
350 struct urb_priv
*urbp
= NULL
;
352 unsigned int toggle
= qh
->initial_toggle
;
355 /* Fixups for a short transfer start with the second URB in the
356 * queue (the short URB is the first). */
358 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
360 /* When starting with the first URB, if the QH element pointer is
361 * still valid then we know the URB's toggles are okay. */
362 else if (qh_element(qh
) != UHCI_PTR_TERM
)
365 /* Fix up the toggle for the URBs in the queue. Normally this
366 * loop won't run more than once: When an error or short transfer
367 * occurs, the queue usually gets emptied. */
368 urbp
= list_prepare_entry(urbp
, &qh
->queue
, node
);
369 list_for_each_entry_continue(urbp
, &qh
->queue
, node
) {
371 /* If the first TD has the right toggle value, we don't
372 * need to change any toggles in this URB */
373 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
374 if (toggle
> 1 || uhci_toggle(td_token(td
)) == toggle
) {
375 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
,
377 toggle
= uhci_toggle(td_token(td
)) ^ 1;
379 /* Otherwise all the toggles in the URB have to be switched */
381 list_for_each_entry(td
, &urbp
->td_list
, list
) {
382 td
->token
^= __constant_cpu_to_le32(
390 pipe
= list_entry(qh
->queue
.next
, struct urb_priv
, node
)->urb
->pipe
;
391 usb_settoggle(qh
->udev
, usb_pipeendpoint(pipe
),
392 usb_pipeout(pipe
), toggle
);
397 * Put a QH on the schedule in both hardware and software
399 static void uhci_activate_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
403 WARN_ON(list_empty(&qh
->queue
));
405 /* Set the element pointer if it isn't set already.
406 * This isn't needed for Isochronous queues, but it doesn't hurt. */
407 if (qh_element(qh
) == UHCI_PTR_TERM
) {
408 struct urb_priv
*urbp
= list_entry(qh
->queue
.next
,
409 struct urb_priv
, node
);
410 struct uhci_td
*td
= list_entry(urbp
->td_list
.next
,
411 struct uhci_td
, list
);
413 qh
->element
= cpu_to_le32(td
->dma_handle
);
416 /* Treat the queue as if it has just advanced */
417 qh
->wait_expired
= 0;
418 qh
->advance_jiffies
= jiffies
;
420 if (qh
->state
== QH_STATE_ACTIVE
)
422 qh
->state
= QH_STATE_ACTIVE
;
424 /* Move the QH from its old list to the end of the appropriate
426 if (qh
== uhci
->next_qh
)
427 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
429 list_move_tail(&qh
->node
, &qh
->skel
->node
);
431 /* Link it into the schedule */
432 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
433 qh
->link
= pqh
->link
;
435 pqh
->link
= UHCI_PTR_QH
| cpu_to_le32(qh
->dma_handle
);
439 * Take a QH off the hardware schedule
441 static void uhci_unlink_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
445 if (qh
->state
== QH_STATE_UNLINKING
)
447 WARN_ON(qh
->state
!= QH_STATE_ACTIVE
|| !qh
->udev
);
448 qh
->state
= QH_STATE_UNLINKING
;
450 /* Unlink the QH from the schedule and record when we did it */
451 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
452 pqh
->link
= qh
->link
;
455 uhci_get_current_frame_number(uhci
);
456 qh
->unlink_frame
= uhci
->frame_number
;
458 /* Force an interrupt so we know when the QH is fully unlinked */
459 if (list_empty(&uhci
->skel_unlink_qh
->node
))
460 uhci_set_next_interrupt(uhci
);
462 /* Move the QH from its old list to the end of the unlinking list */
463 if (qh
== uhci
->next_qh
)
464 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
466 list_move_tail(&qh
->node
, &uhci
->skel_unlink_qh
->node
);
470 * When we and the controller are through with a QH, it becomes IDLE.
471 * This happens when a QH has been off the schedule (on the unlinking
472 * list) for more than one frame, or when an error occurs while adding
473 * the first URB onto a new QH.
475 static void uhci_make_qh_idle(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
477 WARN_ON(qh
->state
== QH_STATE_ACTIVE
);
479 if (qh
== uhci
->next_qh
)
480 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
482 list_move(&qh
->node
, &uhci
->idle_qh_list
);
483 qh
->state
= QH_STATE_IDLE
;
485 /* Now that the QH is idle, its post_td isn't being used */
487 uhci_free_td(uhci
, qh
->post_td
);
491 /* If anyone is waiting for a QH to become idle, wake them up */
492 if (uhci
->num_waiting
)
493 wake_up_all(&uhci
->waitqh
);
496 static inline struct urb_priv
*uhci_alloc_urb_priv(struct uhci_hcd
*uhci
,
499 struct urb_priv
*urbp
;
501 urbp
= kmem_cache_alloc(uhci_up_cachep
, SLAB_ATOMIC
);
505 memset((void *)urbp
, 0, sizeof(*urbp
));
510 INIT_LIST_HEAD(&urbp
->node
);
511 INIT_LIST_HEAD(&urbp
->td_list
);
516 static void uhci_free_urb_priv(struct uhci_hcd
*uhci
,
517 struct urb_priv
*urbp
)
519 struct uhci_td
*td
, *tmp
;
521 if (!list_empty(&urbp
->node
))
522 dev_warn(uhci_dev(uhci
), "urb %p still on QH's list!\n",
525 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
526 uhci_remove_td_from_urbp(td
);
527 uhci_free_td(uhci
, td
);
530 urbp
->urb
->hcpriv
= NULL
;
531 kmem_cache_free(uhci_up_cachep
, urbp
);
535 * Map status to standard result codes
537 * <status> is (td_status(td) & 0xF60000), a.k.a.
538 * uhci_status_bits(td_status(td)).
539 * Note: <status> does not include the TD_CTRL_NAK bit.
540 * <dir_out> is True for output TDs and False for input TDs.
542 static int uhci_map_status(int status
, int dir_out
)
546 if (status
& TD_CTRL_BITSTUFF
) /* Bitstuff error */
548 if (status
& TD_CTRL_CRCTIMEO
) { /* CRC/Timeout */
554 if (status
& TD_CTRL_BABBLE
) /* Babble */
556 if (status
& TD_CTRL_DBUFERR
) /* Buffer error */
558 if (status
& TD_CTRL_STALLED
) /* Stalled */
566 static int uhci_submit_control(struct uhci_hcd
*uhci
, struct urb
*urb
,
570 unsigned long destination
, status
;
571 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
572 int len
= urb
->transfer_buffer_length
;
573 dma_addr_t data
= urb
->transfer_dma
;
575 struct urb_priv
*urbp
= urb
->hcpriv
;
577 /* The "pipe" thing contains the destination in bits 8--18 */
578 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | USB_PID_SETUP
;
580 /* 3 errors, dummy TD remains inactive */
581 status
= uhci_maxerr(3);
582 if (urb
->dev
->speed
== USB_SPEED_LOW
)
583 status
|= TD_CTRL_LS
;
586 * Build the TD for the control request setup packet
589 uhci_add_td_to_urbp(td
, urbp
);
590 uhci_fill_td(td
, status
, destination
| uhci_explen(8),
593 status
|= TD_CTRL_ACTIVE
;
596 * If direction is "send", change the packet ID from SETUP (0x2D)
597 * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
598 * set Short Packet Detect (SPD) for all data packets.
600 if (usb_pipeout(urb
->pipe
))
601 destination
^= (USB_PID_SETUP
^ USB_PID_OUT
);
603 destination
^= (USB_PID_SETUP
^ USB_PID_IN
);
604 status
|= TD_CTRL_SPD
;
611 int pktsze
= min(len
, maxsze
);
613 td
= uhci_alloc_td(uhci
);
616 *plink
= cpu_to_le32(td
->dma_handle
);
618 /* Alternate Data0/1 (start with Data1) */
619 destination
^= TD_TOKEN_TOGGLE
;
621 uhci_add_td_to_urbp(td
, urbp
);
622 uhci_fill_td(td
, status
, destination
| uhci_explen(pktsze
),
631 * Build the final TD for control status
633 td
= uhci_alloc_td(uhci
);
636 *plink
= cpu_to_le32(td
->dma_handle
);
639 * It's IN if the pipe is an output pipe or we're not expecting
642 destination
&= ~TD_TOKEN_PID_MASK
;
643 if (usb_pipeout(urb
->pipe
) || !urb
->transfer_buffer_length
)
644 destination
|= USB_PID_IN
;
646 destination
|= USB_PID_OUT
;
648 destination
|= TD_TOKEN_TOGGLE
; /* End in Data1 */
650 status
&= ~TD_CTRL_SPD
;
652 uhci_add_td_to_urbp(td
, urbp
);
653 uhci_fill_td(td
, status
| TD_CTRL_IOC
,
654 destination
| uhci_explen(0), 0);
658 * Build the new dummy TD and activate the old one
660 td
= uhci_alloc_td(uhci
);
663 *plink
= cpu_to_le32(td
->dma_handle
);
665 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
667 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
670 /* Low-speed transfers get a different queue, and won't hog the bus.
671 * Also, some devices enumerate better without FSBR; the easiest way
672 * to do that is to put URBs on the low-speed queue while the device
673 * isn't in the CONFIGURED state. */
674 if (urb
->dev
->speed
== USB_SPEED_LOW
||
675 urb
->dev
->state
!= USB_STATE_CONFIGURED
)
676 qh
->skel
= uhci
->skel_ls_control_qh
;
678 qh
->skel
= uhci
->skel_fs_control_qh
;
679 uhci_add_fsbr(uhci
, urb
);
682 urb
->actual_length
= -8; /* Account for the SETUP packet */
686 /* Remove the dummy TD from the td_list so it doesn't get freed */
687 uhci_remove_td_from_urbp(qh
->dummy_td
);
692 * Common submit for bulk and interrupt
694 static int uhci_submit_common(struct uhci_hcd
*uhci
, struct urb
*urb
,
698 unsigned long destination
, status
;
699 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
700 int len
= urb
->transfer_buffer_length
;
701 dma_addr_t data
= urb
->transfer_dma
;
703 struct urb_priv
*urbp
= urb
->hcpriv
;
709 /* The "pipe" thing contains the destination in bits 8--18 */
710 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
711 toggle
= usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
712 usb_pipeout(urb
->pipe
));
714 /* 3 errors, dummy TD remains inactive */
715 status
= uhci_maxerr(3);
716 if (urb
->dev
->speed
== USB_SPEED_LOW
)
717 status
|= TD_CTRL_LS
;
718 if (usb_pipein(urb
->pipe
))
719 status
|= TD_CTRL_SPD
;
726 do { /* Allow zero length packets */
729 if (len
<= pktsze
) { /* The last packet */
731 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
732 status
&= ~TD_CTRL_SPD
;
736 td
= uhci_alloc_td(uhci
);
739 *plink
= cpu_to_le32(td
->dma_handle
);
741 uhci_add_td_to_urbp(td
, urbp
);
742 uhci_fill_td(td
, status
,
743 destination
| uhci_explen(pktsze
) |
744 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
747 status
|= TD_CTRL_ACTIVE
;
755 * URB_ZERO_PACKET means adding a 0-length packet, if direction
756 * is OUT and the transfer_length was an exact multiple of maxsze,
757 * hence (len = transfer_length - N * maxsze) == 0
758 * however, if transfer_length == 0, the zero packet was already
761 if ((urb
->transfer_flags
& URB_ZERO_PACKET
) &&
762 usb_pipeout(urb
->pipe
) && len
== 0 &&
763 urb
->transfer_buffer_length
> 0) {
764 td
= uhci_alloc_td(uhci
);
767 *plink
= cpu_to_le32(td
->dma_handle
);
769 uhci_add_td_to_urbp(td
, urbp
);
770 uhci_fill_td(td
, status
,
771 destination
| uhci_explen(0) |
772 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
779 /* Set the interrupt-on-completion flag on the last packet.
780 * A more-or-less typical 4 KB URB (= size of one memory page)
781 * will require about 3 ms to transfer; that's a little on the
782 * fast side but not enough to justify delaying an interrupt
783 * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
785 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
788 * Build the new dummy TD and activate the old one
790 td
= uhci_alloc_td(uhci
);
793 *plink
= cpu_to_le32(td
->dma_handle
);
795 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
797 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
799 qh
->period
= urb
->interval
;
801 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
802 usb_pipeout(urb
->pipe
), toggle
);
806 /* Remove the dummy TD from the td_list so it doesn't get freed */
807 uhci_remove_td_from_urbp(qh
->dummy_td
);
811 static inline int uhci_submit_bulk(struct uhci_hcd
*uhci
, struct urb
*urb
,
816 /* Can't have low-speed bulk transfers */
817 if (urb
->dev
->speed
== USB_SPEED_LOW
)
820 qh
->skel
= uhci
->skel_bulk_qh
;
821 ret
= uhci_submit_common(uhci
, urb
, qh
);
823 uhci_add_fsbr(uhci
, urb
);
827 static int uhci_submit_interrupt(struct uhci_hcd
*uhci
, struct urb
*urb
,
832 /* USB 1.1 interrupt transfers only involve one packet per interval.
833 * Drivers can submit URBs of any length, but longer ones will need
834 * multiple intervals to complete.
837 /* Figure out which power-of-two queue to use */
838 for (exponent
= 7; exponent
>= 0; --exponent
) {
839 if ((1 << exponent
) <= urb
->interval
)
844 urb
->interval
= 1 << exponent
;
847 qh
->skel
= uhci
->skelqh
[UHCI_SKEL_INDEX(exponent
)];
848 else if (qh
->period
!= urb
->interval
)
849 return -EINVAL
; /* Can't change the period */
851 return uhci_submit_common(uhci
, urb
, qh
);
855 * Fix up the data structures following a short transfer
857 static int uhci_fixup_short_transfer(struct uhci_hcd
*uhci
,
858 struct uhci_qh
*qh
, struct urb_priv
*urbp
)
861 struct list_head
*tmp
;
864 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
, list
);
865 if (qh
->type
== USB_ENDPOINT_XFER_CONTROL
) {
867 /* When a control transfer is short, we have to restart
868 * the queue at the status stage transaction, which is
870 WARN_ON(list_empty(&urbp
->td_list
));
871 qh
->element
= cpu_to_le32(td
->dma_handle
);
877 /* When a bulk/interrupt transfer is short, we have to
878 * fix up the toggles of the following URBs on the queue
879 * before restarting the queue at the next URB. */
880 qh
->initial_toggle
= uhci_toggle(td_token(qh
->post_td
)) ^ 1;
881 uhci_fixup_toggles(qh
, 1);
883 if (list_empty(&urbp
->td_list
))
885 qh
->element
= td
->link
;
886 tmp
= urbp
->td_list
.prev
;
890 /* Remove all the TDs we skipped over, from tmp back to the start */
891 while (tmp
!= &urbp
->td_list
) {
892 td
= list_entry(tmp
, struct uhci_td
, list
);
895 uhci_remove_td_from_urbp(td
);
896 uhci_free_td(uhci
, td
);
902 * Common result for control, bulk, and interrupt
904 static int uhci_result_common(struct uhci_hcd
*uhci
, struct urb
*urb
)
906 struct urb_priv
*urbp
= urb
->hcpriv
;
907 struct uhci_qh
*qh
= urbp
->qh
;
908 struct uhci_td
*td
, *tmp
;
912 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
913 unsigned int ctrlstat
;
916 ctrlstat
= td_status(td
);
917 status
= uhci_status_bits(ctrlstat
);
918 if (status
& TD_CTRL_ACTIVE
)
921 len
= uhci_actual_length(ctrlstat
);
922 urb
->actual_length
+= len
;
925 ret
= uhci_map_status(status
,
926 uhci_packetout(td_token(td
)));
927 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
928 /* Some debugging code */
929 dev_dbg(&urb
->dev
->dev
,
930 "%s: failed with status %x\n",
931 __FUNCTION__
, status
);
933 if (debug
> 1 && errbuf
) {
934 /* Print the chain for debugging */
935 uhci_show_qh(urbp
->qh
, errbuf
,
941 } else if (len
< uhci_expected_length(td_token(td
))) {
943 /* We received a short packet */
944 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
)
946 else if (ctrlstat
& TD_CTRL_SPD
)
950 uhci_remove_td_from_urbp(td
);
952 uhci_free_td(uhci
, qh
->post_td
);
962 /* In case a control transfer gets an error
963 * during the setup stage */
964 urb
->actual_length
= max(urb
->actual_length
, 0);
966 /* Note that the queue has stopped and save
967 * the next toggle value */
968 qh
->element
= UHCI_PTR_TERM
;
970 qh
->needs_fixup
= (qh
->type
!= USB_ENDPOINT_XFER_CONTROL
);
971 qh
->initial_toggle
= uhci_toggle(td_token(td
)) ^
974 } else /* Short packet received */
975 ret
= uhci_fixup_short_transfer(uhci
, qh
, urbp
);
980 * Isochronous transfers
982 static int uhci_submit_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
,
985 struct uhci_td
*td
= NULL
; /* Since urb->number_of_packets > 0 */
987 unsigned long destination
, status
;
988 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
990 /* Values must not be too big (could overflow below) */
991 if (urb
->interval
>= UHCI_NUMFRAMES
||
992 urb
->number_of_packets
>= UHCI_NUMFRAMES
)
995 /* Check the period and figure out the starting frame number */
996 if (qh
->period
== 0) {
997 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
998 uhci_get_current_frame_number(uhci
);
999 urb
->start_frame
= uhci
->frame_number
+ 10;
1001 i
= urb
->start_frame
- uhci
->last_iso_frame
;
1002 if (i
<= 0 || i
>= UHCI_NUMFRAMES
)
1005 } else if (qh
->period
!= urb
->interval
) {
1006 return -EINVAL
; /* Can't change the period */
1008 } else { /* Pick up where the last URB leaves off */
1009 if (list_empty(&qh
->queue
)) {
1010 frame
= qh
->iso_frame
;
1014 lurb
= list_entry(qh
->queue
.prev
,
1015 struct urb_priv
, node
)->urb
;
1016 frame
= lurb
->start_frame
+
1017 lurb
->number_of_packets
*
1020 if (urb
->transfer_flags
& URB_ISO_ASAP
)
1021 urb
->start_frame
= frame
;
1022 else if (urb
->start_frame
!= frame
)
1026 /* Make sure we won't have to go too far into the future */
1027 if (uhci_frame_before_eq(uhci
->last_iso_frame
+ UHCI_NUMFRAMES
,
1028 urb
->start_frame
+ urb
->number_of_packets
*
1032 status
= TD_CTRL_ACTIVE
| TD_CTRL_IOS
;
1033 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
1035 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1036 td
= uhci_alloc_td(uhci
);
1040 uhci_add_td_to_urbp(td
, urbp
);
1041 uhci_fill_td(td
, status
, destination
|
1042 uhci_explen(urb
->iso_frame_desc
[i
].length
),
1044 urb
->iso_frame_desc
[i
].offset
);
1047 /* Set the interrupt-on-completion flag on the last packet. */
1048 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
1050 qh
->skel
= uhci
->skel_iso_qh
;
1051 qh
->period
= urb
->interval
;
1053 /* Add the TDs to the frame list */
1054 frame
= urb
->start_frame
;
1055 list_for_each_entry(td
, &urbp
->td_list
, list
) {
1056 uhci_insert_td_in_frame_list(uhci
, td
, frame
);
1057 frame
+= qh
->period
;
1060 if (list_empty(&qh
->queue
)) {
1061 qh
->iso_packet_desc
= &urb
->iso_frame_desc
[0];
1062 qh
->iso_frame
= urb
->start_frame
;
1069 static int uhci_result_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
)
1071 struct uhci_td
*td
, *tmp
;
1072 struct urb_priv
*urbp
= urb
->hcpriv
;
1073 struct uhci_qh
*qh
= urbp
->qh
;
1075 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
1076 unsigned int ctrlstat
;
1080 if (uhci_frame_before_eq(uhci
->cur_iso_frame
, qh
->iso_frame
))
1081 return -EINPROGRESS
;
1083 uhci_remove_tds_from_frame(uhci
, qh
->iso_frame
);
1085 ctrlstat
= td_status(td
);
1086 if (ctrlstat
& TD_CTRL_ACTIVE
) {
1087 status
= -EXDEV
; /* TD was added too late? */
1089 status
= uhci_map_status(uhci_status_bits(ctrlstat
),
1090 usb_pipeout(urb
->pipe
));
1091 actlength
= uhci_actual_length(ctrlstat
);
1093 urb
->actual_length
+= actlength
;
1094 qh
->iso_packet_desc
->actual_length
= actlength
;
1095 qh
->iso_packet_desc
->status
= status
;
1100 qh
->iso_status
= status
;
1103 uhci_remove_td_from_urbp(td
);
1104 uhci_free_td(uhci
, td
);
1105 qh
->iso_frame
+= qh
->period
;
1106 ++qh
->iso_packet_desc
;
1108 return qh
->iso_status
;
1111 static int uhci_urb_enqueue(struct usb_hcd
*hcd
,
1112 struct usb_host_endpoint
*hep
,
1113 struct urb
*urb
, gfp_t mem_flags
)
1116 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1117 unsigned long flags
;
1118 struct urb_priv
*urbp
;
1122 spin_lock_irqsave(&uhci
->lock
, flags
);
1125 if (ret
!= -EINPROGRESS
) /* URB already unlinked! */
1129 urbp
= uhci_alloc_urb_priv(uhci
, urb
);
1134 qh
= (struct uhci_qh
*) hep
->hcpriv
;
1136 qh
= uhci_alloc_qh(uhci
, urb
->dev
, hep
);
1143 case USB_ENDPOINT_XFER_CONTROL
:
1144 ret
= uhci_submit_control(uhci
, urb
, qh
);
1146 case USB_ENDPOINT_XFER_BULK
:
1147 ret
= uhci_submit_bulk(uhci
, urb
, qh
);
1149 case USB_ENDPOINT_XFER_INT
:
1150 if (list_empty(&qh
->queue
)) {
1151 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1155 ret
= uhci_submit_interrupt(uhci
, urb
, qh
);
1157 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 0);
1159 } else { /* inherit from parent */
1160 struct urb_priv
*eurbp
;
1162 eurbp
= list_entry(qh
->queue
.prev
, struct urb_priv
,
1164 urb
->bandwidth
= eurbp
->urb
->bandwidth
;
1165 ret
= uhci_submit_interrupt(uhci
, urb
, qh
);
1168 case USB_ENDPOINT_XFER_ISOC
:
1169 urb
->error_count
= 0;
1170 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1176 ret
= uhci_submit_isochronous(uhci
, urb
, qh
);
1178 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 1);
1182 goto err_submit_failed
;
1184 /* Add this URB to the QH */
1186 list_add_tail(&urbp
->node
, &qh
->queue
);
1188 /* If the new URB is the first and only one on this QH then either
1189 * the QH is new and idle or else it's unlinked and waiting to
1190 * become idle, so we can activate it right away. But only if the
1191 * queue isn't stopped. */
1192 if (qh
->queue
.next
== &urbp
->node
&& !qh
->is_stopped
) {
1193 uhci_activate_qh(uhci
, qh
);
1194 uhci_urbp_wants_fsbr(uhci
, urbp
);
1199 if (qh
->state
== QH_STATE_IDLE
)
1200 uhci_make_qh_idle(uhci
, qh
); /* Reclaim unused QH */
1203 uhci_free_urb_priv(uhci
, urbp
);
1206 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1210 static int uhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
)
1212 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1213 unsigned long flags
;
1214 struct urb_priv
*urbp
;
1217 spin_lock_irqsave(&uhci
->lock
, flags
);
1219 if (!urbp
) /* URB was never linked! */
1223 /* Remove Isochronous TDs from the frame list ASAP */
1224 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
) {
1225 uhci_unlink_isochronous_tds(uhci
, urb
);
1228 /* If the URB has already started, update the QH unlink time */
1229 uhci_get_current_frame_number(uhci
);
1230 if (uhci_frame_before_eq(urb
->start_frame
, uhci
->frame_number
))
1231 qh
->unlink_frame
= uhci
->frame_number
;
1234 uhci_unlink_qh(uhci
, qh
);
1237 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1242 * Finish unlinking an URB and give it back
1244 static void uhci_giveback_urb(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
1245 struct urb
*urb
, struct pt_regs
*regs
)
1246 __releases(uhci
->lock
)
1247 __acquires(uhci
->lock
)
1249 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
1251 /* When giving back the first URB in an Isochronous queue,
1252 * reinitialize the QH's iso-related members for the next URB. */
1253 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
&&
1254 urbp
->node
.prev
== &qh
->queue
&&
1255 urbp
->node
.next
!= &qh
->queue
) {
1256 struct urb
*nurb
= list_entry(urbp
->node
.next
,
1257 struct urb_priv
, node
)->urb
;
1259 qh
->iso_packet_desc
= &nurb
->iso_frame_desc
[0];
1260 qh
->iso_frame
= nurb
->start_frame
;
1264 /* Take the URB off the QH's queue. If the queue is now empty,
1265 * this is a perfect time for a toggle fixup. */
1266 list_del_init(&urbp
->node
);
1267 if (list_empty(&qh
->queue
) && qh
->needs_fixup
) {
1268 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1269 usb_pipeout(urb
->pipe
), qh
->initial_toggle
);
1270 qh
->needs_fixup
= 0;
1273 uhci_free_urb_priv(uhci
, urbp
);
1276 case USB_ENDPOINT_XFER_ISOC
:
1277 /* Release bandwidth for Interrupt or Isoc. transfers */
1279 usb_release_bandwidth(urb
->dev
, urb
, 1);
1281 case USB_ENDPOINT_XFER_INT
:
1282 /* Release bandwidth for Interrupt or Isoc. transfers */
1283 /* Make sure we don't release if we have a queued URB */
1284 if (list_empty(&qh
->queue
) && urb
->bandwidth
)
1285 usb_release_bandwidth(urb
->dev
, urb
, 0);
1287 /* bandwidth was passed on to queued URB, */
1288 /* so don't let usb_unlink_urb() release it */
1293 spin_unlock(&uhci
->lock
);
1294 usb_hcd_giveback_urb(uhci_to_hcd(uhci
), urb
, regs
);
1295 spin_lock(&uhci
->lock
);
1297 /* If the queue is now empty, we can unlink the QH and give up its
1298 * reserved bandwidth. */
1299 if (list_empty(&qh
->queue
)) {
1300 uhci_unlink_qh(uhci
, qh
);
1302 /* Bandwidth stuff not yet implemented */
1308 * Scan the URBs in a QH's queue
1310 #define QH_FINISHED_UNLINKING(qh) \
1311 (qh->state == QH_STATE_UNLINKING && \
1312 uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
1314 static void uhci_scan_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
1315 struct pt_regs
*regs
)
1317 struct urb_priv
*urbp
;
1321 while (!list_empty(&qh
->queue
)) {
1322 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1325 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
)
1326 status
= uhci_result_isochronous(uhci
, urb
);
1328 status
= uhci_result_common(uhci
, urb
);
1329 if (status
== -EINPROGRESS
)
1332 spin_lock(&urb
->lock
);
1333 if (urb
->status
== -EINPROGRESS
) /* Not dequeued */
1334 urb
->status
= status
;
1336 status
= ECONNRESET
; /* Not -ECONNRESET */
1337 spin_unlock(&urb
->lock
);
1339 /* Dequeued but completed URBs can't be given back unless
1340 * the QH is stopped or has finished unlinking. */
1341 if (status
== ECONNRESET
) {
1342 if (QH_FINISHED_UNLINKING(qh
))
1344 else if (!qh
->is_stopped
)
1348 uhci_giveback_urb(uhci
, qh
, urb
, regs
);
1353 /* If the QH is neither stopped nor finished unlinking (normal case),
1354 * our work here is done. */
1355 if (QH_FINISHED_UNLINKING(qh
))
1357 else if (!qh
->is_stopped
)
1360 /* Otherwise give back each of the dequeued URBs */
1362 list_for_each_entry(urbp
, &qh
->queue
, node
) {
1364 if (urb
->status
!= -EINPROGRESS
) {
1366 /* Fix up the TD links and save the toggles for
1367 * non-Isochronous queues. For Isochronous queues,
1368 * test for too-recent dequeues. */
1369 if (!uhci_cleanup_queue(uhci
, qh
, urb
)) {
1373 uhci_giveback_urb(uhci
, qh
, urb
, regs
);
1379 /* There are no more dequeued URBs. If there are still URBs on the
1380 * queue, the QH can now be re-activated. */
1381 if (!list_empty(&qh
->queue
)) {
1382 if (qh
->needs_fixup
)
1383 uhci_fixup_toggles(qh
, 0);
1385 /* If the first URB on the queue wants FSBR but its time
1386 * limit has expired, set the next TD to interrupt on
1387 * completion before reactivating the QH. */
1388 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1389 if (urbp
->fsbr
&& qh
->wait_expired
) {
1390 struct uhci_td
*td
= list_entry(urbp
->td_list
.next
,
1391 struct uhci_td
, list
);
1393 td
->status
|= __cpu_to_le32(TD_CTRL_IOC
);
1396 uhci_activate_qh(uhci
, qh
);
1399 /* The queue is empty. The QH can become idle if it is fully
1401 else if (QH_FINISHED_UNLINKING(qh
))
1402 uhci_make_qh_idle(uhci
, qh
);
1406 * Check for queues that have made some forward progress.
1407 * Returns 0 if the queue is not Isochronous, is ACTIVE, and
1408 * has not advanced since last examined; 1 otherwise.
1410 * Early Intel controllers have a bug which causes qh->element sometimes
1411 * not to advance when a TD completes successfully. The queue remains
1412 * stuck on the inactive completed TD. We detect such cases and advance
1413 * the element pointer by hand.
1415 static int uhci_advance_check(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
1417 struct urb_priv
*urbp
= NULL
;
1422 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
)
1425 /* Treat an UNLINKING queue as though it hasn't advanced.
1426 * This is okay because reactivation will treat it as though
1427 * it has advanced, and if it is going to become IDLE then
1428 * this doesn't matter anyway. Furthermore it's possible
1429 * for an UNLINKING queue not to have any URBs at all, or
1430 * for its first URB not to have any TDs (if it was dequeued
1431 * just as it completed). So it's not easy in any case to
1432 * test whether such queues have advanced. */
1433 if (qh
->state
!= QH_STATE_ACTIVE
) {
1438 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1439 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
1440 status
= td_status(td
);
1441 if (!(status
& TD_CTRL_ACTIVE
)) {
1443 /* We're okay, the queue has advanced */
1444 qh
->wait_expired
= 0;
1445 qh
->advance_jiffies
= jiffies
;
1451 /* The queue hasn't advanced; check for timeout */
1452 if (qh
->wait_expired
)
1455 if (time_after(jiffies
, qh
->advance_jiffies
+ QH_WAIT_TIMEOUT
)) {
1457 /* Detect the Intel bug and work around it */
1458 if (qh
->post_td
&& qh_element(qh
) ==
1459 cpu_to_le32(qh
->post_td
->dma_handle
)) {
1460 qh
->element
= qh
->post_td
->link
;
1461 qh
->advance_jiffies
= jiffies
;
1466 qh
->wait_expired
= 1;
1468 /* If the current URB wants FSBR, unlink it temporarily
1469 * so that we can safely set the next TD to interrupt on
1470 * completion. That way we'll know as soon as the queue
1471 * starts moving again. */
1472 if (urbp
&& urbp
->fsbr
&& !(status
& TD_CTRL_IOC
))
1473 uhci_unlink_qh(uhci
, qh
);
1476 /* Unmoving but not-yet-expired queues keep FSBR alive */
1478 uhci_urbp_wants_fsbr(uhci
, urbp
);
1486 * Process events in the schedule, but only in one thread at a time
1488 static void uhci_scan_schedule(struct uhci_hcd
*uhci
, struct pt_regs
*regs
)
1493 /* Don't allow re-entrant calls */
1494 if (uhci
->scan_in_progress
) {
1495 uhci
->need_rescan
= 1;
1498 uhci
->scan_in_progress
= 1;
1500 uhci
->need_rescan
= 0;
1501 uhci
->fsbr_is_wanted
= 0;
1503 uhci_clear_next_interrupt(uhci
);
1504 uhci_get_current_frame_number(uhci
);
1505 uhci
->cur_iso_frame
= uhci
->frame_number
;
1507 /* Go through all the QH queues and process the URBs in each one */
1508 for (i
= 0; i
< UHCI_NUM_SKELQH
- 1; ++i
) {
1509 uhci
->next_qh
= list_entry(uhci
->skelqh
[i
]->node
.next
,
1510 struct uhci_qh
, node
);
1511 while ((qh
= uhci
->next_qh
) != uhci
->skelqh
[i
]) {
1512 uhci
->next_qh
= list_entry(qh
->node
.next
,
1513 struct uhci_qh
, node
);
1515 if (uhci_advance_check(uhci
, qh
)) {
1516 uhci_scan_qh(uhci
, qh
, regs
);
1517 if (qh
->state
== QH_STATE_ACTIVE
) {
1518 uhci_urbp_wants_fsbr(uhci
,
1519 list_entry(qh
->queue
.next
, struct urb_priv
, node
));
1525 uhci
->last_iso_frame
= uhci
->cur_iso_frame
;
1526 if (uhci
->need_rescan
)
1528 uhci
->scan_in_progress
= 0;
1530 if (uhci
->fsbr_is_on
&& !uhci
->fsbr_is_wanted
&&
1531 !uhci
->fsbr_expiring
) {
1532 uhci
->fsbr_expiring
= 1;
1533 mod_timer(&uhci
->fsbr_timer
, jiffies
+ FSBR_OFF_DELAY
);
1536 if (list_empty(&uhci
->skel_unlink_qh
->node
))
1537 uhci_clear_next_interrupt(uhci
);
1539 uhci_set_next_interrupt(uhci
);