include/asm-ppc/io.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_IO_H
   3 #define _PPC_IO_H
   4
   5 #include <linux/string.h>
   6 #include <linux/types.h>
   7
   8 #include <asm/page.h>
   9 #include <asm/byteorder.h>
  10 #include <asm/synch.h>
  11 #include <asm/mmu.h>
  12
  13 #define SIO_CONFIG_RA   0x398
  14 #define SIO_CONFIG_RD   0x399
  15
  16 #define SLOW_DOWN_IO
  17
  18 #define PMAC_ISA_MEM_BASE       0
  19 #define PMAC_PCI_DRAM_OFFSET    0
  20 #define CHRP_ISA_IO_BASE        0xf8000000
  21 #define CHRP_ISA_MEM_BASE       0xf7000000
  22 #define CHRP_PCI_DRAM_OFFSET    0
  23 #define PREP_ISA_IO_BASE        0x80000000
  24 #define PREP_ISA_MEM_BASE       0xc0000000
  25 #define PREP_PCI_DRAM_OFFSET    0x80000000
  26
  27 #if defined(CONFIG_4xx)
  28 #include <asm/ibm4xx.h>
  29 #elif defined(CONFIG_PPC_MPC52xx)
  30 #include <asm/mpc52xx.h>
  31 #elif defined(CONFIG_8xx)
  32 #include <asm/mpc8xx.h>
  33 #elif defined(CONFIG_8260)
  34 #include <asm/mpc8260.h>
  35 #elif defined(CONFIG_83xx)
  36 #include <asm/mpc83xx.h>
  37 #elif defined(CONFIG_85xx)
  38 #include <asm/mpc85xx.h>
  39 #elif defined(CONFIG_APUS)
  40 #define _IO_BASE        0
  41 #define _ISA_MEM_BASE   0
  42 #define PCI_DRAM_OFFSET 0
  43 #else /* Everyone else */
  44 #define _IO_BASE        isa_io_base
  45 #define _ISA_MEM_BASE   isa_mem_base
  46 #define PCI_DRAM_OFFSET pci_dram_offset
  47 #endif /* Platform-dependent I/O */
  48
  49 #define ___IO_BASE ((void __iomem *)_IO_BASE)
  50 extern unsigned long isa_io_base;
  51 extern unsigned long isa_mem_base;
  52 extern unsigned long pci_dram_offset;
  53
  54 /*
  55  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  56  *
  57  * Read operations have additional twi & isync to make sure the read
  58  * is actually performed (i.e. the data has come back) before we start
  59  * executing any following instructions.
  60  */
  61 extern inline int in_8(const volatile unsigned char __iomem *addr)
  62 {
  63         int ret;
  64
  65         __asm__ __volatile__(
  66                 "lbz%U1%X1 %0,%1;\n"
  67                 "twi 0,%0,0;\n"
  68                 "isync" : "=r" (ret) : "m" (*addr));
  69         return ret;
  70 }
  71
  72 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
  73 {
  74         __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
  75 }
  76
  77 extern inline int in_le16(const volatile unsigned short __iomem *addr)
  78 {
  79         int ret;
  80
  81         __asm__ __volatile__("lhbrx %0,0,%1;\n"
  82                              "twi 0,%0,0;\n"
  83                              "isync" : "=r" (ret) :
  84                               "r" (addr), "m" (*addr));
  85         return ret;
  86 }
  87
  88 extern inline int in_be16(const volatile unsigned short __iomem *addr)
  89 {
  90         int ret;
  91
  92         __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
  93                              "twi 0,%0,0;\n"
  94                              "isync" : "=r" (ret) : "m" (*addr));
  95         return ret;
  96 }
  97
  98 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
  99 {
 100         __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
 101                               "r" (val), "r" (addr));
 102 }
 103
 104 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
 105 {
 106         __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 107 }
 108
 109 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
 110 {
 111         unsigned ret;
 112
 113         __asm__ __volatile__("lwbrx %0,0,%1;\n"
 114                              "twi 0,%0,0;\n"
 115                              "isync" : "=r" (ret) :
 116                              "r" (addr), "m" (*addr));
 117         return ret;
 118 }
 119
 120 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
 121 {
 122         unsigned ret;
 123
 124         __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
 125                              "twi 0,%0,0;\n"
 126                              "isync" : "=r" (ret) : "m" (*addr));
 127         return ret;
 128 }
 129
 130 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
 131 {
 132         __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
 133                              "r" (val), "r" (addr));
 134 }
 135
 136 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 137 {
 138         __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 139 }
 140 #if defined (CONFIG_8260_PCI9)
 141 #define readb(addr) in_8((volatile u8 *)(addr))
 142 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
 143 #else
 144 static inline __u8 readb(const volatile void __iomem *addr)
 145 {
 146         return in_8(addr);
 147 }
 148 static inline void writeb(__u8 b, volatile void __iomem *addr)
 149 {
 150         out_8(addr, b);
 151 }
 152 #endif
 153
 154 #if defined(CONFIG_APUS)
 155 static inline __u16 readw(const volatile void __iomem *addr)
 156 {
 157         return *(__force volatile __u16 *)(addr);
 158 }
 159 static inline __u32 readl(const volatile void __iomem *addr)
 160 {
 161         return *(__force volatile __u32 *)(addr);
 162 }
 163 static inline void writew(__u16 b, volatile void __iomem *addr)
 164 {
 165         *(__force volatile __u16 *)(addr) = b;
 166 }
 167 static inline void writel(__u32 b, volatile void __iomem *addr)
 168 {
 169         *(__force volatile __u32 *)(addr) = b;
 170 }
 171 #elif defined (CONFIG_8260_PCI9)
 172 /* Use macros if PCI9 workaround enabled */
 173 #define readw(addr) in_le16((volatile u16 *)(addr))
 174 #define readl(addr) in_le32((volatile u32 *)(addr))
 175 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
 176 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
 177 #else
 178 static inline __u16 readw(const volatile void __iomem *addr)
 179 {
 180         return in_le16(addr);
 181 }
 182 static inline __u32 readl(const volatile void __iomem *addr)
 183 {
 184         return in_le32(addr);
 185 }
 186 static inline void writew(__u16 b, volatile void __iomem *addr)
 187 {
 188         out_le16(addr, b);
 189 }
 190 static inline void writel(__u32 b, volatile void __iomem *addr)
 191 {
 192         out_le32(addr, b);
 193 }
 194 #endif /* CONFIG_APUS */
 195
 196 #define readb_relaxed(addr) readb(addr)
 197 #define readw_relaxed(addr) readw(addr)
 198 #define readl_relaxed(addr) readl(addr)
 199
 200 static inline __u8 __raw_readb(const volatile void __iomem *addr)
 201 {
 202         return *(__force volatile __u8 *)(addr);
 203 }
 204 static inline __u16 __raw_readw(const volatile void __iomem *addr)
 205 {
 206         return *(__force volatile __u16 *)(addr);
 207 }
 208 static inline __u32 __raw_readl(const volatile void __iomem *addr)
 209 {
 210         return *(__force volatile __u32 *)(addr);
 211 }
 212 static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
 213 {
 214         *(__force volatile __u8 *)(addr) = b;
 215 }
 216 static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
 217 {
 218         *(__force volatile __u16 *)(addr) = b;
 219 }
 220 static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
 221 {
 222         *(__force volatile __u32 *)(addr) = b;
 223 }
 224
 225 #define mmiowb()
 226
 227 /*
 228  * The insw/outsw/insl/outsl macros don't do byte-swapping.
 229  * They are only used in practice for transferring buffers which
 230  * are arrays of bytes, and byte-swapping is not appropriate in
 231  * that case.  - paulus
 232  */
 233 #define insb(port, buf, ns)     _insb((port)+___IO_BASE, (buf), (ns))
 234 #define outsb(port, buf, ns)    _outsb((port)+___IO_BASE, (buf), (ns))
 235 #define insw(port, buf, ns)     _insw_ns((port)+___IO_BASE, (buf), (ns))
 236 #define outsw(port, buf, ns)    _outsw_ns((port)+___IO_BASE, (buf), (ns))
 237 #define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
 238 #define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
 239
 240 /*
 241  * On powermacs and 8xx we will get a machine check exception
 242  * if we try to read data from a non-existent I/O port. Because
 243  * the machine check is an asynchronous exception, it isn't
 244  * well-defined which instruction SRR0 will point to when the
 245  * exception occurs.
 246  * With the sequence below (twi; isync; nop), we have found that
 247  * the machine check occurs on one of the three instructions on
 248  * all PPC implementations tested so far.  The twi and isync are
 249  * needed on the 601 (in fact twi; sync works too), the isync and
 250  * nop are needed on 604[e|r], and any of twi, sync or isync will
 251  * work on 603[e], 750, 74xx.
 252  * The twi creates an explicit data dependency on the returned
 253  * value which seems to be needed to make the 601 wait for the
 254  * load to finish.
 255  */
 256
 257 #define __do_in_asm(name, op)                           \
 258 extern __inline__ unsigned int name(unsigned int port)  \
 259 {                                                       \
 260         unsigned int x;                                 \
 261         __asm__ __volatile__(                           \
 262                 "0:"    op "    %0,0,%1\n"              \
 263                 "1:     twi     0,%0,0\n"               \
 264                 "2:     isync\n"                        \
 265                 "3:     nop\n"                          \
 266                 "4:\n"                                  \
 267                 ".section .fixup,\"ax\"\n"              \
 268                 "5:     li      %0,-1\n"                \
 269                 "       b       4b\n"                   \
 270                 ".previous\n"                           \
 271                 ".section __ex_table,\"a\"\n"           \
 272                 "       .align  2\n"                    \
 273                 "       .long   0b,5b\n"                \
 274                 "       .long   1b,5b\n"                \
 275                 "       .long   2b,5b\n"                \
 276                 "       .long   3b,5b\n"                \
 277                 ".previous"                             \
 278                 : "=&r" (x)                             \
 279                 : "r" (port + ___IO_BASE));             \
 280         return x;                                       \
 281 }
 282
 283 #define __do_out_asm(name, op)                          \
 284 extern __inline__ void name(unsigned int val, unsigned int port) \
 285 {                                                       \
 286         __asm__ __volatile__(                           \
 287                 "0:" op " %0,0,%1\n"                    \
 288                 "1:     sync\n"                         \
 289                 "2:\n"                                  \
 290                 ".section __ex_table,\"a\"\n"           \
 291                 "       .align  2\n"                    \
 292                 "       .long   0b,2b\n"                \
 293                 "       .long   1b,2b\n"                \
 294                 ".previous"                             \
 295                 : : "r" (val), "r" (port + ___IO_BASE));        \
 296 }
 297
 298 __do_out_asm(outb, "stbx")
 299 #ifdef CONFIG_APUS
 300 __do_in_asm(inb, "lbzx")
 301 __do_in_asm(inw, "lhz%U1%X1")
 302 __do_in_asm(inl, "lwz%U1%X1")
 303 __do_out_asm(outl,"stw%U0%X0")
 304 __do_out_asm(outw, "sth%U0%X0")
 305 #elif defined (CONFIG_8260_PCI9)
 306 /* in asm cannot be defined if PCI9 workaround is used */
 307 #define inb(port)               in_8((port)+___IO_BASE)
 308 #define inw(port)               in_le16((port)+___IO_BASE)
 309 #define inl(port)               in_le32((port)+___IO_BASE)
 310 __do_out_asm(outw, "sthbrx")
 311 __do_out_asm(outl, "stwbrx")
 312 #else
 313 __do_in_asm(inb, "lbzx")
 314 __do_in_asm(inw, "lhbrx")
 315 __do_in_asm(inl, "lwbrx")
 316 __do_out_asm(outw, "sthbrx")
 317 __do_out_asm(outl, "stwbrx")
 318
 319 #endif
 320
 321 #define inb_p(port)             inb((port))
 322 #define outb_p(val, port)       outb((val), (port))
 323 #define inw_p(port)             inw((port))
 324 #define outw_p(val, port)       outw((val), (port))
 325 #define inl_p(port)             inl((port))
 326 #define outl_p(val, port)       outl((val), (port))
 327
 328 extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
 329 extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
 330 extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
 331 extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
 332 extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
 333 extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
 334 extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
 335 extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
 336 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
 337 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
 338
 339 /*
 340  * The *_ns versions below don't do byte-swapping.
 341  * Neither do the standard versions now, these are just here
 342  * for older code.
 343  */
 344 #define insw_ns(port, buf, ns)  _insw_ns((port)+___IO_BASE, (buf), (ns))
 345 #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
 346 #define insl_ns(port, buf, nl)  _insl_ns((port)+___IO_BASE, (buf), (nl))
 347 #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
 348
 349
 350 #define IO_SPACE_LIMIT ~0
 351
 352 #if defined (CONFIG_8260_PCI9)
 353 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
 354 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
 355 #define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
 356 #else
 357 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 358 {
 359         memset((void __force *)addr, val, count);
 360 }
 361 static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
 362 {
 363         memcpy(dst, (void __force *) src, count);
 364 }
 365 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 366 {
 367         memcpy((void __force *) dst, src, count);
 368 }
 369 #endif
 370
 371 #define eth_io_copy_and_sum(a,b,c,d)            eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
 372
 373 /*
 374  * Map in an area of physical address space, for accessing
 375  * I/O devices etc.
 376  */
 377 extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 378                        unsigned long flags);
 379 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 380 #ifdef CONFIG_44x
 381 extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
 382 #endif
 383 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 384 extern void iounmap(volatile void __iomem *addr);
 385 extern unsigned long iopa(unsigned long addr);
 386 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 387 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
 388                              unsigned int size, int flags);
 389
 390 /*
 391  * The PCI bus is inherently Little-Endian.  The PowerPC is being
 392  * run Big-Endian.  Thus all values which cross the [PCI] barrier
 393  * must be endian-adjusted.  Also, the local DRAM has a different
 394  * address from the PCI point of view, thus buffer addresses also
 395  * have to be modified [mapped] appropriately.
 396  */
 397 extern inline unsigned long virt_to_bus(volatile void * address)
 398 {
 399 #ifndef CONFIG_APUS
 400         if (address == (void *)0)
 401                 return 0;
 402         return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
 403 #else
 404         return iopa ((unsigned long) address);
 405 #endif
 406 }
 407
 408 extern inline void * bus_to_virt(unsigned long address)
 409 {
 410 #ifndef CONFIG_APUS
 411         if (address == 0)
 412                 return NULL;
 413         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 414 #else
 415         return (void*) mm_ptov (address);
 416 #endif
 417 }
 418
 419 /*
 420  * Change virtual addresses to physical addresses and vv, for
 421  * addresses in the area where the kernel has the RAM mapped.
 422  */
 423 extern inline unsigned long virt_to_phys(volatile void * address)
 424 {
 425 #ifndef CONFIG_APUS
 426         return (unsigned long) address - KERNELBASE;
 427 #else
 428         return iopa ((unsigned long) address);
 429 #endif
 430 }
 431
 432 extern inline void * phys_to_virt(unsigned long address)
 433 {
 434 #ifndef CONFIG_APUS
 435         return (void *) (address + KERNELBASE);
 436 #else
 437         return (void*) mm_ptov (address);
 438 #endif
 439 }
 440
 441 /*
 442  * Change "struct page" to physical address.
 443  */
 444 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 445 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 446
 447 /* Enforce in-order execution of data I/O.
 448  * No distinction between read/write on PPC; use eieio for all three.
 449  */
 450 #define iobarrier_rw() eieio()
 451 #define iobarrier_r()  eieio()
 452 #define iobarrier_w()  eieio()
 453
 454 static inline int check_signature(volatile void __iomem * io_addr,
 455         const unsigned char *signature, int length)
 456 {
 457         int retval = 0;
 458         do {
 459                 if (readb(io_addr) != *signature)
 460                         goto out;
 461                 io_addr++;
 462                 signature++;
 463                 length--;
 464         } while (length);
 465         retval = 1;
 466 out:
 467         return retval;
 468 }
 469
 470 /*
 471  * Here comes the ppc implementation of the IOMAP
 472  * interfaces.
 473  */
 474 static inline unsigned int ioread8(void __iomem *addr)
 475 {
 476         return readb(addr);
 477 }
 478
 479 static inline unsigned int ioread16(void __iomem *addr)
 480 {
 481         return readw(addr);
 482 }
 483
 484 static inline unsigned int ioread32(void __iomem *addr)
 485 {
 486         return readl(addr);
 487 }
 488
 489 static inline void iowrite8(u8 val, void __iomem *addr)
 490 {
 491         writeb(val, addr);
 492 }
 493
 494 static inline void iowrite16(u16 val, void __iomem *addr)
 495 {
 496         writew(val, addr);
 497 }
 498
 499 static inline void iowrite32(u32 val, void __iomem *addr)
 500 {
 501         writel(val, addr);
 502 }
 503
 504 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
 505 {
 506         _insb(addr, dst, count);
 507 }
 508
 509 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
 510 {
 511         _insw_ns(addr, dst, count);
 512 }
 513
 514 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
 515 {
 516         _insl_ns(addr, dst, count);
 517 }
 518
 519 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
 520 {
 521         _outsb(addr, src, count);
 522 }
 523
 524 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
 525 {
 526         _outsw_ns(addr, src, count);
 527 }
 528
 529 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
 530 {
 531         _outsl_ns(addr, src, count);
 532 }
 533
 534 /* Create a virtual mapping cookie for an IO port range */
 535 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 536 extern void ioport_unmap(void __iomem *);
 537
 538 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 539 struct pci_dev;
 540 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 541 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 542
 543 #endif /* _PPC_IO_H */
 544
 545 #ifdef CONFIG_8260_PCI9
 546 #include <asm/mpc8260_pci9.h>
 547 #endif
 548
 549 #ifdef CONFIG_NOT_COHERENT_CACHE
 550
 551 #define dma_cache_inv(_start,_size) \
 552         invalidate_dcache_range(_start, (_start + _size))
 553 #define dma_cache_wback(_start,_size) \
 554         clean_dcache_range(_start, (_start + _size))
 555 #define dma_cache_wback_inv(_start,_size) \
 556         flush_dcache_range(_start, (_start + _size))
 557
 558 #else
 559
 560 #define dma_cache_inv(_start,_size)             do { } while (0)
 561 #define dma_cache_wback(_start,_size)           do { } while (0)
 562 #define dma_cache_wback_inv(_start,_size)       do { } while (0)
 563
 564 #endif
 565
 566 /*
 567  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 568  * access
 569  */
 570 #define xlate_dev_mem_ptr(p)    __va(p)
 571
 572 /*
 573  * Convert a virtual cached pointer to an uncached pointer
 574  */
 575 #define xlate_dev_kmem_ptr(p)   p
 576
 577 /* access ports */
 578 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 579 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 580
 581 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 582 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 583
 584 #endif /* __KERNEL__ */