[PATCH] W1: possible cleanups
[linux-2.6/verdex.git] / include / asm-s390 / ptrace.h
blob4d75d77b0f9960cad73cedb09adaae4e85a6c5c1
1 /*
2 * include/asm-s390/ptrace.h
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
7 */
9 #ifndef _S390_PTRACE_H
10 #define _S390_PTRACE_H
13 * Offsets in the user_regs_struct. They are used for the ptrace
14 * system call and in entry.S
16 #ifndef __s390x__
18 #define PT_PSWMASK 0x00
19 #define PT_PSWADDR 0x04
20 #define PT_GPR0 0x08
21 #define PT_GPR1 0x0C
22 #define PT_GPR2 0x10
23 #define PT_GPR3 0x14
24 #define PT_GPR4 0x18
25 #define PT_GPR5 0x1C
26 #define PT_GPR6 0x20
27 #define PT_GPR7 0x24
28 #define PT_GPR8 0x28
29 #define PT_GPR9 0x2C
30 #define PT_GPR10 0x30
31 #define PT_GPR11 0x34
32 #define PT_GPR12 0x38
33 #define PT_GPR13 0x3C
34 #define PT_GPR14 0x40
35 #define PT_GPR15 0x44
36 #define PT_ACR0 0x48
37 #define PT_ACR1 0x4C
38 #define PT_ACR2 0x50
39 #define PT_ACR3 0x54
40 #define PT_ACR4 0x58
41 #define PT_ACR5 0x5C
42 #define PT_ACR6 0x60
43 #define PT_ACR7 0x64
44 #define PT_ACR8 0x68
45 #define PT_ACR9 0x6C
46 #define PT_ACR10 0x70
47 #define PT_ACR11 0x74
48 #define PT_ACR12 0x78
49 #define PT_ACR13 0x7C
50 #define PT_ACR14 0x80
51 #define PT_ACR15 0x84
52 #define PT_ORIGGPR2 0x88
53 #define PT_FPC 0x90
55 * A nasty fact of life that the ptrace api
56 * only supports passing of longs.
58 #define PT_FPR0_HI 0x98
59 #define PT_FPR0_LO 0x9C
60 #define PT_FPR1_HI 0xA0
61 #define PT_FPR1_LO 0xA4
62 #define PT_FPR2_HI 0xA8
63 #define PT_FPR2_LO 0xAC
64 #define PT_FPR3_HI 0xB0
65 #define PT_FPR3_LO 0xB4
66 #define PT_FPR4_HI 0xB8
67 #define PT_FPR4_LO 0xBC
68 #define PT_FPR5_HI 0xC0
69 #define PT_FPR5_LO 0xC4
70 #define PT_FPR6_HI 0xC8
71 #define PT_FPR6_LO 0xCC
72 #define PT_FPR7_HI 0xD0
73 #define PT_FPR7_LO 0xD4
74 #define PT_FPR8_HI 0xD8
75 #define PT_FPR8_LO 0XDC
76 #define PT_FPR9_HI 0xE0
77 #define PT_FPR9_LO 0xE4
78 #define PT_FPR10_HI 0xE8
79 #define PT_FPR10_LO 0xEC
80 #define PT_FPR11_HI 0xF0
81 #define PT_FPR11_LO 0xF4
82 #define PT_FPR12_HI 0xF8
83 #define PT_FPR12_LO 0xFC
84 #define PT_FPR13_HI 0x100
85 #define PT_FPR13_LO 0x104
86 #define PT_FPR14_HI 0x108
87 #define PT_FPR14_LO 0x10C
88 #define PT_FPR15_HI 0x110
89 #define PT_FPR15_LO 0x114
90 #define PT_CR_9 0x118
91 #define PT_CR_10 0x11C
92 #define PT_CR_11 0x120
93 #define PT_IEEE_IP 0x13C
94 #define PT_LASTOFF PT_IEEE_IP
95 #define PT_ENDREGS 0x140-1
97 #define GPR_SIZE 4
98 #define CR_SIZE 4
100 #define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */
102 #else /* __s390x__ */
104 #define PT_PSWMASK 0x00
105 #define PT_PSWADDR 0x08
106 #define PT_GPR0 0x10
107 #define PT_GPR1 0x18
108 #define PT_GPR2 0x20
109 #define PT_GPR3 0x28
110 #define PT_GPR4 0x30
111 #define PT_GPR5 0x38
112 #define PT_GPR6 0x40
113 #define PT_GPR7 0x48
114 #define PT_GPR8 0x50
115 #define PT_GPR9 0x58
116 #define PT_GPR10 0x60
117 #define PT_GPR11 0x68
118 #define PT_GPR12 0x70
119 #define PT_GPR13 0x78
120 #define PT_GPR14 0x80
121 #define PT_GPR15 0x88
122 #define PT_ACR0 0x90
123 #define PT_ACR1 0x94
124 #define PT_ACR2 0x98
125 #define PT_ACR3 0x9C
126 #define PT_ACR4 0xA0
127 #define PT_ACR5 0xA4
128 #define PT_ACR6 0xA8
129 #define PT_ACR7 0xAC
130 #define PT_ACR8 0xB0
131 #define PT_ACR9 0xB4
132 #define PT_ACR10 0xB8
133 #define PT_ACR11 0xBC
134 #define PT_ACR12 0xC0
135 #define PT_ACR13 0xC4
136 #define PT_ACR14 0xC8
137 #define PT_ACR15 0xCC
138 #define PT_ORIGGPR2 0xD0
139 #define PT_FPC 0xD8
140 #define PT_FPR0 0xE0
141 #define PT_FPR1 0xE8
142 #define PT_FPR2 0xF0
143 #define PT_FPR3 0xF8
144 #define PT_FPR4 0x100
145 #define PT_FPR5 0x108
146 #define PT_FPR6 0x110
147 #define PT_FPR7 0x118
148 #define PT_FPR8 0x120
149 #define PT_FPR9 0x128
150 #define PT_FPR10 0x130
151 #define PT_FPR11 0x138
152 #define PT_FPR12 0x140
153 #define PT_FPR13 0x148
154 #define PT_FPR14 0x150
155 #define PT_FPR15 0x158
156 #define PT_CR_9 0x160
157 #define PT_CR_10 0x168
158 #define PT_CR_11 0x170
159 #define PT_IEEE_IP 0x1A8
160 #define PT_LASTOFF PT_IEEE_IP
161 #define PT_ENDREGS 0x1B0-1
163 #define GPR_SIZE 8
164 #define CR_SIZE 8
166 #define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */
168 #endif /* __s390x__ */
170 #define NUM_GPRS 16
171 #define NUM_FPRS 16
172 #define NUM_CRS 16
173 #define NUM_ACRS 16
175 #define FPR_SIZE 8
176 #define FPC_SIZE 4
177 #define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */
178 #define ACR_SIZE 4
181 #define PTRACE_OLDSETOPTIONS 21
183 #ifndef __ASSEMBLY__
184 #include <linux/stddef.h>
185 #include <linux/types.h>
187 typedef union
189 float f;
190 double d;
191 __u64 ui;
192 struct
194 __u32 hi;
195 __u32 lo;
196 } fp;
197 } freg_t;
199 typedef struct
201 __u32 fpc;
202 freg_t fprs[NUM_FPRS];
203 } s390_fp_regs;
205 #define FPC_EXCEPTION_MASK 0xF8000000
206 #define FPC_FLAGS_MASK 0x00F80000
207 #define FPC_DXC_MASK 0x0000FF00
208 #define FPC_RM_MASK 0x00000003
209 #define FPC_VALID_MASK 0xF8F8FF03
211 /* this typedef defines how a Program Status Word looks like */
212 typedef struct
214 unsigned long mask;
215 unsigned long addr;
216 } __attribute__ ((aligned(8))) psw_t;
218 #ifndef __s390x__
220 #define PSW_MASK_PER 0x40000000UL
221 #define PSW_MASK_DAT 0x04000000UL
222 #define PSW_MASK_IO 0x02000000UL
223 #define PSW_MASK_EXT 0x01000000UL
224 #define PSW_MASK_KEY 0x00F00000UL
225 #define PSW_MASK_MCHECK 0x00040000UL
226 #define PSW_MASK_WAIT 0x00020000UL
227 #define PSW_MASK_PSTATE 0x00010000UL
228 #define PSW_MASK_ASC 0x0000C000UL
229 #define PSW_MASK_CC 0x00003000UL
230 #define PSW_MASK_PM 0x00000F00UL
232 #define PSW_ADDR_AMODE 0x80000000UL
233 #define PSW_ADDR_INSN 0x7FFFFFFFUL
235 #define PSW_BASE_BITS 0x00080000UL
236 #define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20)
238 #define PSW_ASC_PRIMARY 0x00000000UL
239 #define PSW_ASC_ACCREG 0x00004000UL
240 #define PSW_ASC_SECONDARY 0x00008000UL
241 #define PSW_ASC_HOME 0x0000C000UL
243 #else /* __s390x__ */
245 #define PSW_MASK_PER 0x4000000000000000UL
246 #define PSW_MASK_DAT 0x0400000000000000UL
247 #define PSW_MASK_IO 0x0200000000000000UL
248 #define PSW_MASK_EXT 0x0100000000000000UL
249 #define PSW_MASK_KEY 0x00F0000000000000UL
250 #define PSW_MASK_MCHECK 0x0004000000000000UL
251 #define PSW_MASK_WAIT 0x0002000000000000UL
252 #define PSW_MASK_PSTATE 0x0001000000000000UL
253 #define PSW_MASK_ASC 0x0000C00000000000UL
254 #define PSW_MASK_CC 0x0000300000000000UL
255 #define PSW_MASK_PM 0x00000F0000000000UL
257 #define PSW_ADDR_AMODE 0x0000000000000000UL
258 #define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL
260 #define PSW_BASE_BITS 0x0000000180000000UL
261 #define PSW_BASE32_BITS 0x0000000080000000UL
262 #define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52)
264 #define PSW_ASC_PRIMARY 0x0000000000000000UL
265 #define PSW_ASC_ACCREG 0x0000400000000000UL
266 #define PSW_ASC_SECONDARY 0x0000800000000000UL
267 #define PSW_ASC_HOME 0x0000C00000000000UL
269 #define PSW_USER32_BITS (PSW_BASE32_BITS | PSW_MASK_DAT | PSW_ASC_HOME | \
270 PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK | \
271 PSW_MASK_PSTATE | PSW_DEFAULT_KEY)
273 #endif /* __s390x__ */
275 #define PSW_KERNEL_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_PRIMARY | \
276 PSW_MASK_MCHECK | PSW_DEFAULT_KEY)
277 #define PSW_USER_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_HOME | \
278 PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK | \
279 PSW_MASK_PSTATE | PSW_DEFAULT_KEY)
281 /* This macro merges a NEW PSW mask specified by the user into
282 the currently active PSW mask CURRENT, modifying only those
283 bits in CURRENT that the user may be allowed to change: this
284 is the condition code and the program mask bits. */
285 #define PSW_MASK_MERGE(CURRENT,NEW) \
286 (((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
287 ((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
290 * The s390_regs structure is used to define the elf_gregset_t.
292 typedef struct
294 psw_t psw;
295 unsigned long gprs[NUM_GPRS];
296 unsigned int acrs[NUM_ACRS];
297 unsigned long orig_gpr2;
298 } s390_regs;
300 #ifdef __KERNEL__
301 #include <asm/setup.h>
302 #include <asm/page.h>
305 * The pt_regs struct defines the way the registers are stored on
306 * the stack during a system call.
308 struct pt_regs
310 unsigned long args[1];
311 psw_t psw;
312 unsigned long gprs[NUM_GPRS];
313 unsigned long orig_gpr2;
314 unsigned short ilc;
315 unsigned short trap;
317 #endif
320 * Now for the program event recording (trace) definitions.
322 typedef struct
324 unsigned long cr[3];
325 } per_cr_words;
327 #define PER_EM_MASK 0xE8000000UL
329 typedef struct
331 #ifdef __s390x__
332 unsigned : 32;
333 #endif /* __s390x__ */
334 unsigned em_branching : 1;
335 unsigned em_instruction_fetch : 1;
337 * Switching on storage alteration automatically fixes
338 * the storage alteration event bit in the users std.
340 unsigned em_storage_alteration : 1;
341 unsigned em_gpr_alt_unused : 1;
342 unsigned em_store_real_address : 1;
343 unsigned : 3;
344 unsigned branch_addr_ctl : 1;
345 unsigned : 1;
346 unsigned storage_alt_space_ctl : 1;
347 unsigned : 21;
348 unsigned long starting_addr;
349 unsigned long ending_addr;
350 } per_cr_bits;
352 typedef struct
354 unsigned short perc_atmid;
355 unsigned long address;
356 unsigned char access_id;
357 } per_lowcore_words;
359 typedef struct
361 unsigned perc_branching : 1;
362 unsigned perc_instruction_fetch : 1;
363 unsigned perc_storage_alteration : 1;
364 unsigned perc_gpr_alt_unused : 1;
365 unsigned perc_store_real_address : 1;
366 unsigned : 3;
367 unsigned atmid_psw_bit_31 : 1;
368 unsigned atmid_validity_bit : 1;
369 unsigned atmid_psw_bit_32 : 1;
370 unsigned atmid_psw_bit_5 : 1;
371 unsigned atmid_psw_bit_16 : 1;
372 unsigned atmid_psw_bit_17 : 1;
373 unsigned si : 2;
374 unsigned long address;
375 unsigned : 4;
376 unsigned access_id : 4;
377 } per_lowcore_bits;
379 typedef struct
381 union {
382 per_cr_words words;
383 per_cr_bits bits;
384 } control_regs;
386 * Use these flags instead of setting em_instruction_fetch
387 * directly they are used so that single stepping can be
388 * switched on & off while not affecting other tracing
390 unsigned single_step : 1;
391 unsigned instruction_fetch : 1;
392 unsigned : 30;
394 * These addresses are copied into cr10 & cr11 if single
395 * stepping is switched off
397 unsigned long starting_addr;
398 unsigned long ending_addr;
399 union {
400 per_lowcore_words words;
401 per_lowcore_bits bits;
402 } lowcore;
403 } per_struct;
405 typedef struct
407 unsigned int len;
408 unsigned long kernel_addr;
409 unsigned long process_addr;
410 } ptrace_area;
413 * S/390 specific non posix ptrace requests. I chose unusual values so
414 * they are unlikely to clash with future ptrace definitions.
416 #define PTRACE_PEEKUSR_AREA 0x5000
417 #define PTRACE_POKEUSR_AREA 0x5001
418 #define PTRACE_PEEKTEXT_AREA 0x5002
419 #define PTRACE_PEEKDATA_AREA 0x5003
420 #define PTRACE_POKETEXT_AREA 0x5004
421 #define PTRACE_POKEDATA_AREA 0x5005
424 * PT_PROT definition is loosely based on hppa bsd definition in
425 * gdb/hppab-nat.c
427 #define PTRACE_PROT 21
429 typedef enum
431 ptprot_set_access_watchpoint,
432 ptprot_set_write_watchpoint,
433 ptprot_disable_watchpoint
434 } ptprot_flags;
436 typedef struct
438 unsigned long lowaddr;
439 unsigned long hiaddr;
440 ptprot_flags prot;
441 } ptprot_area;
443 /* Sequence of bytes for breakpoint illegal instruction. */
444 #define S390_BREAKPOINT {0x0,0x1}
445 #define S390_BREAKPOINT_U16 ((__u16)0x0001)
446 #define S390_SYSCALL_OPCODE ((__u16)0x0a00)
447 #define S390_SYSCALL_SIZE 2
450 * The user_regs_struct defines the way the user registers are
451 * store on the stack for signal handling.
453 struct user_regs_struct
455 psw_t psw;
456 unsigned long gprs[NUM_GPRS];
457 unsigned int acrs[NUM_ACRS];
458 unsigned long orig_gpr2;
459 s390_fp_regs fp_regs;
461 * These per registers are in here so that gdb can modify them
462 * itself as there is no "official" ptrace interface for hardware
463 * watchpoints. This is the way intel does it.
465 per_struct per_info;
466 unsigned long ieee_instruction_pointer;
467 /* Used to give failing instruction back to user for ieee exceptions */
470 #ifdef __KERNEL__
471 #define __ARCH_SYS_PTRACE 1
473 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
474 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
475 #define profile_pc(regs) instruction_pointer(regs)
476 extern void show_regs(struct pt_regs * regs);
477 #endif
479 static inline void
480 psw_set_key(unsigned int key)
482 asm volatile ( "spka 0(%0)" : : "d" (key) );
485 #endif /* __ASSEMBLY__ */
487 #endif /* _S390_PTRACE_H */