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[PATCH] W1: possible cleanups
[linux-2.6/verdex.git] / include / asm-x86_64 / apicdef.h
blob5a48e9bcf218ac05bcf1dd77821b93e1cb348321
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
3
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0xFFu)
16 #define SET_APIC_ID(x) (((x)<<24))
17 #define APIC_LVR 0x30
18 #define APIC_LVR_MASK 0xFF00FF
19 #define GET_APIC_VERSION(x) ((x)&0xFFu)
20 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
21 #define APIC_INTEGRATED(x) ((x)&0xF0u)
22 #define APIC_TASKPRI 0x80
23 #define APIC_TPRI_MASK 0xFFu
24 #define APIC_ARBPRI 0x90
25 #define APIC_ARBPRI_MASK 0xFFu
26 #define APIC_PROCPRI 0xA0
27 #define APIC_EOI 0xB0
28 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
29 #define APIC_RRR 0xC0
30 #define APIC_LDR 0xD0
31 #define APIC_LDR_MASK (0xFFu<<24)
32 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
33 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
34 #define APIC_ALL_CPUS 0xFFu
35 #define APIC_DFR 0xE0
36 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
37 #define APIC_DFR_FLAT 0xFFFFFFFFul
38 #define APIC_SPIV 0xF0
39 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
40 #define APIC_SPIV_APIC_ENABLED (1<<8)
41 #define APIC_ISR 0x100
42 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
43 #define APIC_TMR 0x180
44 #define APIC_IRR 0x200
45 #define APIC_ESR 0x280
46 #define APIC_ESR_SEND_CS 0x00001
47 #define APIC_ESR_RECV_CS 0x00002
48 #define APIC_ESR_SEND_ACC 0x00004
49 #define APIC_ESR_RECV_ACC 0x00008
50 #define APIC_ESR_SENDILL 0x00020
51 #define APIC_ESR_RECVILL 0x00040
52 #define APIC_ESR_ILLREGA 0x00080
53 #define APIC_ICR 0x300
54 #define APIC_DEST_SELF 0x40000
55 #define APIC_DEST_ALLINC 0x80000
56 #define APIC_DEST_ALLBUT 0xC0000
57 #define APIC_ICR_RR_MASK 0x30000
58 #define APIC_ICR_RR_INVALID 0x00000
59 #define APIC_ICR_RR_INPROG 0x10000
60 #define APIC_ICR_RR_VALID 0x20000
61 #define APIC_INT_LEVELTRIG 0x08000
62 #define APIC_INT_ASSERT 0x04000
63 #define APIC_ICR_BUSY 0x01000
64 #define APIC_DEST_LOGICAL 0x00800
65 #define APIC_DEST_PHYSICAL 0x00000
66 #define APIC_DM_FIXED 0x00000
67 #define APIC_DM_LOWEST 0x00100
68 #define APIC_DM_SMI 0x00200
69 #define APIC_DM_REMRD 0x00300
70 #define APIC_DM_NMI 0x00400
71 #define APIC_DM_INIT 0x00500
72 #define APIC_DM_STARTUP 0x00600
73 #define APIC_DM_EXTINT 0x00700
74 #define APIC_VECTOR_MASK 0x000FF
75 #define APIC_ICR2 0x310
76 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
77 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
78 #define APIC_LVTT 0x320
79 #define APIC_LVTTHMR 0x330
80 #define APIC_LVTPC 0x340
81 #define APIC_LVT0 0x350
82 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
83 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
84 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
85 #define APIC_TIMER_BASE_CLKIN 0x0
86 #define APIC_TIMER_BASE_TMBASE 0x1
87 #define APIC_TIMER_BASE_DIV 0x2
88 #define APIC_LVT_TIMER_PERIODIC (1<<17)
89 #define APIC_LVT_MASKED (1<<16)
90 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
91 #define APIC_LVT_REMOTE_IRR (1<<14)
92 #define APIC_INPUT_POLARITY (1<<13)
93 #define APIC_SEND_PENDING (1<<12)
94 #define APIC_MODE_MASK 0x700
95 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
96 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
97 #define APIC_MODE_FIXED 0x0
98 #define APIC_MODE_NMI 0x4
99 #define APIC_MODE_EXTINT 0x7
100 #define APIC_LVT1 0x360
101 #define APIC_LVTERR 0x370
102 #define APIC_TMICT 0x380
103 #define APIC_TMCCT 0x390
104 #define APIC_TDCR 0x3E0
105 #define APIC_TDR_DIV_TMBASE (1<<2)
106 #define APIC_TDR_DIV_1 0xB
107 #define APIC_TDR_DIV_2 0x0
108 #define APIC_TDR_DIV_4 0x1
109 #define APIC_TDR_DIV_8 0x2
110 #define APIC_TDR_DIV_16 0x3
111 #define APIC_TDR_DIV_32 0x8
112 #define APIC_TDR_DIV_64 0x9
113 #define APIC_TDR_DIV_128 0xA
114
115 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
116
117 #define MAX_IO_APICS 128
118 #define MAX_LOCAL_APIC 256
119
120 /*
121 * All x86-64 systems are xAPIC compatible.
122 * In the following, "apicid" is a physical APIC ID.
123 */
124 #define XAPIC_DEST_CPUS_SHIFT 4
125 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
126 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
127 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
128 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
129 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
130 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
131
132 /*
133 * the local APIC register structure, memory mapped. Not terribly well
134 * tested, but we might eventually use this one in the future - the
135 * problem why we cannot use it right now is the P5 APIC, it has an
136 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
137 */
138 #define u32 unsigned int
139
140 #define lapic ((volatile struct local_apic *)APIC_BASE)
141
142 struct local_apic {
143
144 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
145
146 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
147
148 /*020*/ struct { /* APIC ID Register */
149 u32 __reserved_1 : 24,
150 phys_apic_id : 4,
151 __reserved_2 : 4;
152 u32 __reserved[3];
153 } id;
154
155 /*030*/ const
156 struct { /* APIC Version Register */
157 u32 version : 8,
158 __reserved_1 : 8,
159 max_lvt : 8,
160 __reserved_2 : 8;
161 u32 __reserved[3];
162 } version;
163
164 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
165
166 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
167
168 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
169
170 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
171
172 /*080*/ struct { /* Task Priority Register */
173 u32 priority : 8,
174 __reserved_1 : 24;
175 u32 __reserved_2[3];
176 } tpr;
177
178 /*090*/ const
179 struct { /* Arbitration Priority Register */
180 u32 priority : 8,
181 __reserved_1 : 24;
182 u32 __reserved_2[3];
183 } apr;
184
185 /*0A0*/ const
186 struct { /* Processor Priority Register */
187 u32 priority : 8,
188 __reserved_1 : 24;
189 u32 __reserved_2[3];
190 } ppr;
191
192 /*0B0*/ struct { /* End Of Interrupt Register */
193 u32 eoi;
194 u32 __reserved[3];
195 } eoi;
196
197 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
198
199 /*0D0*/ struct { /* Logical Destination Register */
200 u32 __reserved_1 : 24,
201 logical_dest : 8;
202 u32 __reserved_2[3];
203 } ldr;
204
205 /*0E0*/ struct { /* Destination Format Register */
206 u32 __reserved_1 : 28,
207 model : 4;
208 u32 __reserved_2[3];
209 } dfr;
210
211 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
212 u32 spurious_vector : 8,
213 apic_enabled : 1,
214 focus_cpu : 1,
215 __reserved_2 : 22;
216 u32 __reserved_3[3];
217 } svr;
218
219 /*100*/ struct { /* In Service Register */
220 /*170*/ u32 bitfield;
221 u32 __reserved[3];
222 } isr [8];
223
224 /*180*/ struct { /* Trigger Mode Register */
225 /*1F0*/ u32 bitfield;
226 u32 __reserved[3];
227 } tmr [8];
228
229 /*200*/ struct { /* Interrupt Request Register */
230 /*270*/ u32 bitfield;
231 u32 __reserved[3];
232 } irr [8];
233
234 /*280*/ union { /* Error Status Register */
235 struct {
236 u32 send_cs_error : 1,
237 receive_cs_error : 1,
238 send_accept_error : 1,
239 receive_accept_error : 1,
240 __reserved_1 : 1,
241 send_illegal_vector : 1,
242 receive_illegal_vector : 1,
243 illegal_register_address : 1,
244 __reserved_2 : 24;
245 u32 __reserved_3[3];
246 } error_bits;
247 struct {
248 u32 errors;
249 u32 __reserved_3[3];
250 } all_errors;
251 } esr;
252
253 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
254
255 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
256
257 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
258
259 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
260
261 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
262
263 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
264
265 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
266
267 /*300*/ struct { /* Interrupt Command Register 1 */
268 u32 vector : 8,
269 delivery_mode : 3,
270 destination_mode : 1,
271 delivery_status : 1,
272 __reserved_1 : 1,
273 level : 1,
274 trigger : 1,
275 __reserved_2 : 2,
276 shorthand : 2,
277 __reserved_3 : 12;
278 u32 __reserved_4[3];
279 } icr1;
280
281 /*310*/ struct { /* Interrupt Command Register 2 */
282 union {
283 u32 __reserved_1 : 24,
284 phys_dest : 4,
285 __reserved_2 : 4;
286 u32 __reserved_3 : 24,
287 logical_dest : 8;
288 } dest;
289 u32 __reserved_4[3];
290 } icr2;
291
292 /*320*/ struct { /* LVT - Timer */
293 u32 vector : 8,
294 __reserved_1 : 4,
295 delivery_status : 1,
296 __reserved_2 : 3,
297 mask : 1,
298 timer_mode : 1,
299 __reserved_3 : 14;
300 u32 __reserved_4[3];
301 } lvt_timer;
302
303 /*330*/ struct { /* LVT - Thermal Sensor */
304 u32 vector : 8,
305 delivery_mode : 3,
306 __reserved_1 : 1,
307 delivery_status : 1,
308 __reserved_2 : 3,
309 mask : 1,
310 __reserved_3 : 15;
311 u32 __reserved_4[3];
312 } lvt_thermal;
313
314 /*340*/ struct { /* LVT - Performance Counter */
315 u32 vector : 8,
316 delivery_mode : 3,
317 __reserved_1 : 1,
318 delivery_status : 1,
319 __reserved_2 : 3,
320 mask : 1,
321 __reserved_3 : 15;
322 u32 __reserved_4[3];
323 } lvt_pc;
324
325 /*350*/ struct { /* LVT - LINT0 */
326 u32 vector : 8,
327 delivery_mode : 3,
328 __reserved_1 : 1,
329 delivery_status : 1,
330 polarity : 1,
331 remote_irr : 1,
332 trigger : 1,
333 mask : 1,
334 __reserved_2 : 15;
335 u32 __reserved_3[3];
336 } lvt_lint0;
337
338 /*360*/ struct { /* LVT - LINT1 */
339 u32 vector : 8,
340 delivery_mode : 3,
341 __reserved_1 : 1,
342 delivery_status : 1,
343 polarity : 1,
344 remote_irr : 1,
345 trigger : 1,
346 mask : 1,
347 __reserved_2 : 15;
348 u32 __reserved_3[3];
349 } lvt_lint1;
350
351 /*370*/ struct { /* LVT - Error */
352 u32 vector : 8,
353 __reserved_1 : 4,
354 delivery_status : 1,
355 __reserved_2 : 3,
356 mask : 1,
357 __reserved_3 : 15;
358 u32 __reserved_4[3];
359 } lvt_error;
360
361 /*380*/ struct { /* Timer Initial Count Register */
362 u32 initial_count;
363 u32 __reserved_2[3];
364 } timer_icr;
365
366 /*390*/ const
367 struct { /* Timer Current Count Register */
368 u32 curr_count;
369 u32 __reserved_2[3];
370 } timer_ccr;
371
372 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
373
374 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
375
376 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
377
378 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
379
380 /*3E0*/ struct { /* Timer Divide Configuration Register */
381 u32 divisor : 4,
382 __reserved_1 : 28;
383 u32 __reserved_2[3];
384 } timer_dcr;
385
386 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
387
388 } __attribute__ ((packed));
389
390 #undef u32
391
392 #define BAD_APICID 0xFFu
393
394 #endif
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