arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/leds.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/hardware/amba.h>
  35 #include <asm/hardware/amba_clcd.h>
  36 #include <asm/hardware/icst307.h>
  37
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/flash.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/time.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/mmc.h>
  44
  45 #include "core.h"
  46 #include "clock.h"
  47
  48 /*
  49  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  50  * is the (PA >> 12).
  51  *
  52  * Setup a VA for the Versatile Vectored Interrupt Controller.
  53  */
  54 #define VA_VIC_BASE              IO_ADDRESS(VERSATILE_VIC_BASE)
  55 #define VA_SIC_BASE              IO_ADDRESS(VERSATILE_SIC_BASE)
  56
  57 static void vic_mask_irq(unsigned int irq)
  58 {
  59         irq -= IRQ_VIC_START;
  60         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
  61 }
  62
  63 static void vic_unmask_irq(unsigned int irq)
  64 {
  65         irq -= IRQ_VIC_START;
  66         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
  67 }
  68
  69 static struct irqchip vic_chip = {
  70         .ack    = vic_mask_irq,
  71         .mask   = vic_mask_irq,
  72         .unmask = vic_unmask_irq,
  73 };
  74
  75 static void sic_mask_irq(unsigned int irq)
  76 {
  77         irq -= IRQ_SIC_START;
  78         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  79 }
  80
  81 static void sic_unmask_irq(unsigned int irq)
  82 {
  83         irq -= IRQ_SIC_START;
  84         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  85 }
  86
  87 static struct irqchip sic_chip = {
  88         .ack    = sic_mask_irq,
  89         .mask   = sic_mask_irq,
  90         .unmask = sic_unmask_irq,
  91 };
  92
  93 static void
  94 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  95 {
  96         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  97
  98         if (status == 0) {
  99                 do_bad_IRQ(irq, desc, regs);
 100                 return;
 101         }
 102
 103         do {
 104                 irq = ffs(status) - 1;
 105                 status &= ~(1 << irq);
 106
 107                 irq += IRQ_SIC_START;
 108
 109                 desc = irq_desc + irq;
 110                 desc->handle(irq, desc, regs);
 111         } while (status);
 112 }
 113
 114 #if 1
 115 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 116 #define IRQ_AACI        IRQ_VICSOURCE24
 117 #define IRQ_ETH         IRQ_VICSOURCE25
 118 #define PIC_MASK        0xFFD00000
 119 #else
 120 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 121 #define IRQ_AACI        IRQ_SIC_AACI
 122 #define IRQ_ETH         IRQ_SIC_ETH
 123 #define PIC_MASK        0
 124 #endif
 125
 126 void __init versatile_init_irq(void)
 127 {
 128         unsigned int i, value;
 129
 130         /* Disable all interrupts initially. */
 131
 132         writel(0, VA_VIC_BASE + VIC_INT_SELECT);
 133         writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
 134         writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
 135         writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
 136         writel(0, VA_VIC_BASE + VIC_ITCR);
 137         writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
 138
 139         /*
 140          * Make sure we clear all existing interrupts
 141          */
 142         writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
 143         for (i = 0; i < 19; i++) {
 144                 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
 145                 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
 146         }
 147
 148         for (i = 0; i < 16; i++) {
 149                 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 150                 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
 151         }
 152
 153         writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
 154
 155         for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
 156                 if (i != IRQ_VICSOURCE31) {
 157                         set_irq_chip(i, &vic_chip);
 158                         set_irq_handler(i, do_level_IRQ);
 159                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 160                 }
 161         }
 162
 163         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
 164         vic_unmask_irq(IRQ_VICSOURCE31);
 165
 166         /* Do second interrupt controller */
 167         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 168
 169         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 170                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 171                         set_irq_chip(i, &sic_chip);
 172                         set_irq_handler(i, do_level_IRQ);
 173                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 174                 }
 175         }
 176
 177         /*
 178          * Interrupts on secondary controller from 0 to 8 are routed to
 179          * source 31 on PIC.
 180          * Interrupts from 21 to 31 are routed directly to the VIC on
 181          * the corresponding number on primary controller. This is controlled
 182          * by setting PIC_ENABLEx.
 183          */
 184         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 185 }
 186
 187 static struct map_desc versatile_io_desc[] __initdata = {
 188  { IO_ADDRESS(VERSATILE_SYS_BASE),   VERSATILE_SYS_BASE,   SZ_4K,      MT_DEVICE },
 189  { IO_ADDRESS(VERSATILE_SIC_BASE),   VERSATILE_SIC_BASE,   SZ_4K,      MT_DEVICE },
 190  { IO_ADDRESS(VERSATILE_VIC_BASE),   VERSATILE_VIC_BASE,   SZ_4K,      MT_DEVICE },
 191  { IO_ADDRESS(VERSATILE_SCTL_BASE),  VERSATILE_SCTL_BASE,  SZ_4K * 9,  MT_DEVICE },
 192 #ifdef CONFIG_MACH_VERSATILE_AB
 193  { IO_ADDRESS(VERSATILE_GPIO0_BASE), VERSATILE_GPIO0_BASE, SZ_4K,      MT_DEVICE },
 194  { IO_ADDRESS(VERSATILE_IB2_BASE),   VERSATILE_IB2_BASE,   SZ_64M,     MT_DEVICE },
 195 #endif
 196 #ifdef CONFIG_DEBUG_LL
 197  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
 198 #endif
 199 #ifdef CONFIG_PCI
 200  { IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
 201  { VERSATILE_PCI_VIRT_BASE,          VERSATILE_PCI_BASE,   VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
 202  { VERSATILE_PCI_CFG_VIRT_BASE,      VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
 203 #if 0
 204  { VERSATILE_PCI_VIRT_MEM_BASE0,     VERSATILE_PCI_MEM_BASE0, SZ_16M,  MT_DEVICE },
 205  { VERSATILE_PCI_VIRT_MEM_BASE1,     VERSATILE_PCI_MEM_BASE1, SZ_16M,  MT_DEVICE },
 206  { VERSATILE_PCI_VIRT_MEM_BASE2,     VERSATILE_PCI_MEM_BASE2, SZ_16M,  MT_DEVICE },
 207 #endif
 208 #endif
 209 };
 210
 211 void __init versatile_map_io(void)
 212 {
 213         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 214 }
 215
 216 #define VERSATILE_REFCOUNTER    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 217
 218 /*
 219  * This is the Versatile sched_clock implementation.  This has
 220  * a resolution of 41.7ns, and a maximum value of about 179s.
 221  */
 222 unsigned long long sched_clock(void)
 223 {
 224         unsigned long long v;
 225
 226         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
 227         do_div(v, 3);
 228
 229         return v;
 230 }
 231
 232
 233 #define VERSATILE_FLASHCTRL    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 234
 235 static int versatile_flash_init(void)
 236 {
 237         u32 val;
 238
 239         val = __raw_readl(VERSATILE_FLASHCTRL);
 240         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 241         __raw_writel(val, VERSATILE_FLASHCTRL);
 242
 243         return 0;
 244 }
 245
 246 static void versatile_flash_exit(void)
 247 {
 248         u32 val;
 249
 250         val = __raw_readl(VERSATILE_FLASHCTRL);
 251         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 252         __raw_writel(val, VERSATILE_FLASHCTRL);
 253 }
 254
 255 static void versatile_flash_set_vpp(int on)
 256 {
 257         u32 val;
 258
 259         val = __raw_readl(VERSATILE_FLASHCTRL);
 260         if (on)
 261                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 262         else
 263                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 264         __raw_writel(val, VERSATILE_FLASHCTRL);
 265 }
 266
 267 static struct flash_platform_data versatile_flash_data = {
 268         .map_name               = "cfi_probe",
 269         .width                  = 4,
 270         .init                   = versatile_flash_init,
 271         .exit                   = versatile_flash_exit,
 272         .set_vpp                = versatile_flash_set_vpp,
 273 };
 274
 275 static struct resource versatile_flash_resource = {
 276         .start                  = VERSATILE_FLASH_BASE,
 277         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
 278         .flags                  = IORESOURCE_MEM,
 279 };
 280
 281 static struct platform_device versatile_flash_device = {
 282         .name                   = "armflash",
 283         .id                     = 0,
 284         .dev                    = {
 285                 .platform_data  = &versatile_flash_data,
 286         },
 287         .num_resources          = 1,
 288         .resource               = &versatile_flash_resource,
 289 };
 290
 291 static struct resource smc91x_resources[] = {
 292         [0] = {
 293                 .start          = VERSATILE_ETH_BASE,
 294                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 295                 .flags          = IORESOURCE_MEM,
 296         },
 297         [1] = {
 298                 .start          = IRQ_ETH,
 299                 .end            = IRQ_ETH,
 300                 .flags          = IORESOURCE_IRQ,
 301         },
 302 };
 303
 304 static struct platform_device smc91x_device = {
 305         .name           = "smc91x",
 306         .id             = 0,
 307         .num_resources  = ARRAY_SIZE(smc91x_resources),
 308         .resource       = smc91x_resources,
 309 };
 310
 311 #define VERSATILE_SYSMCI        (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 312
 313 unsigned int mmc_status(struct device *dev)
 314 {
 315         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 316         u32 mask;
 317
 318         if (adev->res.start == VERSATILE_MMCI0_BASE)
 319                 mask = 1;
 320         else
 321                 mask = 2;
 322
 323         return readl(VERSATILE_SYSMCI) & mask;
 324 }
 325
 326 static struct mmc_platform_data mmc0_plat_data = {
 327         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 328         .status         = mmc_status,
 329 };
 330
 331 /*
 332  * Clock handling
 333  */
 334 static const struct icst307_params versatile_oscvco_params = {
 335         .ref            = 24000,
 336         .vco_max        = 200000,
 337         .vd_min         = 4 + 8,
 338         .vd_max         = 511 + 8,
 339         .rd_min         = 1 + 2,
 340         .rd_max         = 127 + 2,
 341 };
 342
 343 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
 344 {
 345         unsigned long sys_lock = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 346 #if defined(CONFIG_ARCH_VERSATILE_PB)
 347         unsigned long sys_osc = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
 348 #elif defined(CONFIG_MACH_VERSATILE_AB)
 349         unsigned long sys_osc = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
 350 #endif
 351         u32 val;
 352
 353         val = readl(sys_osc) & ~0x7ffff;
 354         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 355
 356         writel(0xa05f, sys_lock);
 357         writel(val, sys_osc);
 358         writel(0, sys_lock);
 359 }
 360
 361 static struct clk versatile_clcd_clk = {
 362         .name   = "CLCDCLK",
 363         .params = &versatile_oscvco_params,
 364         .setvco = versatile_oscvco_set,
 365 };
 366
 367 /*
 368  * CLCD support.
 369  */
 370 #define SYS_CLCD_MODE_MASK      (3 << 0)
 371 #define SYS_CLCD_MODE_888       (0 << 0)
 372 #define SYS_CLCD_MODE_5551      (1 << 0)
 373 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 374 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 375 #define SYS_CLCD_NLCDIOON       (1 << 2)
 376 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 377 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 378 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 379 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 380 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 381 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 382 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 383 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 384
 385 static struct clcd_panel vga = {
 386         .mode           = {
 387                 .name           = "VGA",
 388                 .refresh        = 60,
 389                 .xres           = 640,
 390                 .yres           = 480,
 391                 .pixclock       = 39721,
 392                 .left_margin    = 40,
 393                 .right_margin   = 24,
 394                 .upper_margin   = 32,
 395                 .lower_margin   = 11,
 396                 .hsync_len      = 96,
 397                 .vsync_len      = 2,
 398                 .sync           = 0,
 399                 .vmode          = FB_VMODE_NONINTERLACED,
 400         },
 401         .width          = -1,
 402         .height         = -1,
 403         .tim2           = TIM2_BCD | TIM2_IPC,
 404         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 405         .bpp            = 16,
 406 };
 407
 408 static struct clcd_panel sanyo_3_8_in = {
 409         .mode           = {
 410                 .name           = "Sanyo QVGA",
 411                 .refresh        = 116,
 412                 .xres           = 320,
 413                 .yres           = 240,
 414                 .pixclock       = 100000,
 415                 .left_margin    = 6,
 416                 .right_margin   = 6,
 417                 .upper_margin   = 5,
 418                 .lower_margin   = 5,
 419                 .hsync_len      = 6,
 420                 .vsync_len      = 6,
 421                 .sync           = 0,
 422                 .vmode          = FB_VMODE_NONINTERLACED,
 423         },
 424         .width          = -1,
 425         .height         = -1,
 426         .tim2           = TIM2_BCD,
 427         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 428         .bpp            = 16,
 429 };
 430
 431 static struct clcd_panel sanyo_2_5_in = {
 432         .mode           = {
 433                 .name           = "Sanyo QVGA Portrait",
 434                 .refresh        = 116,
 435                 .xres           = 240,
 436                 .yres           = 320,
 437                 .pixclock       = 100000,
 438                 .left_margin    = 20,
 439                 .right_margin   = 10,
 440                 .upper_margin   = 2,
 441                 .lower_margin   = 2,
 442                 .hsync_len      = 10,
 443                 .vsync_len      = 2,
 444                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 445                 .vmode          = FB_VMODE_NONINTERLACED,
 446         },
 447         .width          = -1,
 448         .height         = -1,
 449         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 450         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 451         .bpp            = 16,
 452 };
 453
 454 static struct clcd_panel epson_2_2_in = {
 455         .mode           = {
 456                 .name           = "Epson QCIF",
 457                 .refresh        = 390,
 458                 .xres           = 176,
 459                 .yres           = 220,
 460                 .pixclock       = 62500,
 461                 .left_margin    = 3,
 462                 .right_margin   = 2,
 463                 .upper_margin   = 1,
 464                 .lower_margin   = 0,
 465                 .hsync_len      = 3,
 466                 .vsync_len      = 2,
 467                 .sync           = 0,
 468                 .vmode          = FB_VMODE_NONINTERLACED,
 469         },
 470         .width          = -1,
 471         .height         = -1,
 472         .tim2           = TIM2_BCD | TIM2_IPC,
 473         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 474         .bpp            = 16,
 475 };
 476
 477 /*
 478  * Detect which LCD panel is connected, and return the appropriate
 479  * clcd_panel structure.  Note: we do not have any information on
 480  * the required timings for the 8.4in panel, so we presently assume
 481  * VGA timings.
 482  */
 483 static struct clcd_panel *versatile_clcd_panel(void)
 484 {
 485         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 486         struct clcd_panel *panel = &vga;
 487         u32 val;
 488
 489         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 490         if (val == SYS_CLCD_ID_SANYO_3_8)
 491                 panel = &sanyo_3_8_in;
 492         else if (val == SYS_CLCD_ID_SANYO_2_5)
 493                 panel = &sanyo_2_5_in;
 494         else if (val == SYS_CLCD_ID_EPSON_2_2)
 495                 panel = &epson_2_2_in;
 496         else if (val == SYS_CLCD_ID_VGA)
 497                 panel = &vga;
 498         else {
 499                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 500                         val);
 501                 panel = &vga;
 502         }
 503
 504         return panel;
 505 }
 506
 507 /*
 508  * Disable all display connectors on the interface module.
 509  */
 510 static void versatile_clcd_disable(struct clcd_fb *fb)
 511 {
 512         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 513         u32 val;
 514
 515         val = readl(sys_clcd);
 516         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 517         writel(val, sys_clcd);
 518
 519 #ifdef CONFIG_MACH_VERSATILE_AB
 520         /*
 521          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 522          */
 523         if (fb->panel == &sanyo_2_5_in) {
 524                 unsigned long versatile_ib2_ctrl = IO_ADDRESS(VERSATILE_IB2_CTRL);
 525                 unsigned long ctrl;
 526
 527                 ctrl = readl(versatile_ib2_ctrl);
 528                 ctrl &= ~0x01;
 529                 writel(ctrl, versatile_ib2_ctrl);
 530         }
 531 #endif
 532 }
 533
 534 /*
 535  * Enable the relevant connector on the interface module.
 536  */
 537 static void versatile_clcd_enable(struct clcd_fb *fb)
 538 {
 539         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 540         u32 val;
 541
 542         val = readl(sys_clcd);
 543         val &= ~SYS_CLCD_MODE_MASK;
 544
 545         switch (fb->fb.var.green.length) {
 546         case 5:
 547                 val |= SYS_CLCD_MODE_5551;
 548                 break;
 549         case 6:
 550                 val |= SYS_CLCD_MODE_565_RLSB;
 551                 break;
 552         case 8:
 553                 val |= SYS_CLCD_MODE_888;
 554                 break;
 555         }
 556
 557         /*
 558          * Set the MUX
 559          */
 560         writel(val, sys_clcd);
 561
 562         /*
 563          * And now enable the PSUs
 564          */
 565         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 566         writel(val, sys_clcd);
 567
 568 #ifdef CONFIG_MACH_VERSATILE_AB
 569         /*
 570          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 571          */
 572         if (fb->panel == &sanyo_2_5_in) {
 573                 unsigned long versatile_ib2_ctrl = IO_ADDRESS(VERSATILE_IB2_CTRL);
 574                 unsigned long ctrl;
 575
 576                 ctrl = readl(versatile_ib2_ctrl);
 577                 ctrl |= 0x01;
 578                 writel(ctrl, versatile_ib2_ctrl);
 579         }
 580 #endif
 581 }
 582
 583 static unsigned long framesize = SZ_1M;
 584
 585 static int versatile_clcd_setup(struct clcd_fb *fb)
 586 {
 587         dma_addr_t dma;
 588
 589         fb->panel               = versatile_clcd_panel();
 590
 591         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 592                                                     &dma, GFP_KERNEL);
 593         if (!fb->fb.screen_base) {
 594                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 595                 return -ENOMEM;
 596         }
 597
 598         fb->fb.fix.smem_start   = dma;
 599         fb->fb.fix.smem_len     = framesize;
 600
 601         return 0;
 602 }
 603
 604 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 605 {
 606         return dma_mmap_writecombine(&fb->dev->dev, vma,
 607                                      fb->fb.screen_base,
 608                                      fb->fb.fix.smem_start,
 609                                      fb->fb.fix.smem_len);
 610 }
 611
 612 static void versatile_clcd_remove(struct clcd_fb *fb)
 613 {
 614         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 615                               fb->fb.screen_base, fb->fb.fix.smem_start);
 616 }
 617
 618 static struct clcd_board clcd_plat_data = {
 619         .name           = "Versatile",
 620         .check          = clcdfb_check,
 621         .decode         = clcdfb_decode,
 622         .disable        = versatile_clcd_disable,
 623         .enable         = versatile_clcd_enable,
 624         .setup          = versatile_clcd_setup,
 625         .mmap           = versatile_clcd_mmap,
 626         .remove         = versatile_clcd_remove,
 627 };
 628
 629 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 630 #define AACI_DMA        { 0x80, 0x81 }
 631 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 632 #define MMCI0_DMA       { 0x84, 0 }
 633 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 634 #define KMI0_DMA        { 0, 0 }
 635 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 636 #define KMI1_DMA        { 0, 0 }
 637
 638 /*
 639  * These devices are connected directly to the multi-layer AHB switch
 640  */
 641 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 642 #define SMC_DMA         { 0, 0 }
 643 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 644 #define MPMC_DMA        { 0, 0 }
 645 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 646 #define CLCD_DMA        { 0, 0 }
 647 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 648 #define DMAC_DMA        { 0, 0 }
 649
 650 /*
 651  * These devices are connected via the core APB bridge
 652  */
 653 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 654 #define SCTL_DMA        { 0, 0 }
 655 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 656 #define WATCHDOG_DMA    { 0, 0 }
 657 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 658 #define GPIO0_DMA       { 0, 0 }
 659 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 660 #define GPIO1_DMA       { 0, 0 }
 661 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 662 #define RTC_DMA         { 0, 0 }
 663
 664 /*
 665  * These devices are connected via the DMA APB bridge
 666  */
 667 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 668 #define SCI_DMA         { 7, 6 }
 669 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 670 #define UART0_DMA       { 15, 14 }
 671 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 672 #define UART1_DMA       { 13, 12 }
 673 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 674 #define UART2_DMA       { 11, 10 }
 675 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 676 #define SSP_DMA         { 9, 8 }
 677
 678 /* FPGA Primecells */
 679 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 680 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 681 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 682 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 683
 684 /* DevChip Primecells */
 685 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 686 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 687 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 688 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 689 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 690 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 691 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 692 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 693 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 694 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 695 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 696 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 697 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 698 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 699
 700 static struct amba_device *amba_devs[] __initdata = {
 701         &dmac_device,
 702         &uart0_device,
 703         &uart1_device,
 704         &uart2_device,
 705         &smc_device,
 706         &mpmc_device,
 707         &clcd_device,
 708         &sctl_device,
 709         &wdog_device,
 710         &gpio0_device,
 711         &gpio1_device,
 712         &rtc_device,
 713         &sci0_device,
 714         &ssp0_device,
 715         &aaci_device,
 716         &mmc0_device,
 717         &kmi0_device,
 718         &kmi1_device,
 719 };
 720
 721 #ifdef CONFIG_LEDS
 722 #define VA_LEDS_BASE (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 723
 724 static void versatile_leds_event(led_event_t ledevt)
 725 {
 726         unsigned long flags;
 727         u32 val;
 728
 729         local_irq_save(flags);
 730         val = readl(VA_LEDS_BASE);
 731
 732         switch (ledevt) {
 733         case led_idle_start:
 734                 val = val & ~VERSATILE_SYS_LED0;
 735                 break;
 736
 737         case led_idle_end:
 738                 val = val | VERSATILE_SYS_LED0;
 739                 break;
 740
 741         case led_timer:
 742                 val = val ^ VERSATILE_SYS_LED1;
 743                 break;
 744
 745         case led_halted:
 746                 val = 0;
 747                 break;
 748
 749         default:
 750                 break;
 751         }
 752
 753         writel(val, VA_LEDS_BASE);
 754         local_irq_restore(flags);
 755 }
 756 #endif  /* CONFIG_LEDS */
 757
 758 void __init versatile_init(void)
 759 {
 760         int i;
 761
 762         clk_register(&versatile_clcd_clk);
 763
 764         platform_device_register(&versatile_flash_device);
 765         platform_device_register(&smc91x_device);
 766
 767         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 768                 struct amba_device *d = amba_devs[i];
 769                 amba_device_register(d, &iomem_resource);
 770         }
 771
 772 #ifdef CONFIG_LEDS
 773         leds_event = versatile_leds_event;
 774 #endif
 775 }
 776
 777 /*
 778  * Where is the timer (VA)?
 779  */
 780 #define TIMER0_VA_BASE           IO_ADDRESS(VERSATILE_TIMER0_1_BASE)
 781 #define TIMER1_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER0_1_BASE) + 0x20)
 782 #define TIMER2_VA_BASE           IO_ADDRESS(VERSATILE_TIMER2_3_BASE)
 783 #define TIMER3_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER2_3_BASE) + 0x20)
 784 #define VA_IC_BASE               IO_ADDRESS(VERSATILE_VIC_BASE)
 785
 786 /*
 787  * How long is the timer interval?
 788  */
 789 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 790 #if TIMER_INTERVAL >= 0x100000
 791 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)           /* Divide by 256 */
 792 #define TIMER_CTRL      0x88                            /* Enable, Clock / 256 */
 793 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 794 #elif TIMER_INTERVAL >= 0x10000
 795 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 796 #define TIMER_CTRL      0x84                            /* Enable, Clock / 16 */
 797 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 798 #else
 799 #define TIMER_RELOAD    (TIMER_INTERVAL)
 800 #define TIMER_CTRL      0x80                            /* Enable */
 801 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 802 #endif
 803
 804 #define TIMER_CTRL_IE   (1 << 5)        /* Interrupt Enable */
 805
 806 /*
 807  * What does it look like?
 808  */
 809 typedef struct TimerStruct {
 810         unsigned long TimerLoad;
 811         unsigned long TimerValue;
 812         unsigned long TimerControl;
 813         unsigned long TimerClear;
 814 } TimerStruct_t;
 815
 816 /*
 817  * Returns number of ms since last clock interrupt.  Note that interrupts
 818  * will have been disabled by do_gettimeoffset()
 819  */
 820 static unsigned long versatile_gettimeoffset(void)
 821 {
 822         volatile TimerStruct_t *timer0 = (TimerStruct_t *)TIMER0_VA_BASE;
 823         unsigned long ticks1, ticks2, status;
 824
 825         /*
 826          * Get the current number of ticks.  Note that there is a race
 827          * condition between us reading the timer and checking for
 828          * an interrupt.  We get around this by ensuring that the
 829          * counter has not reloaded between our two reads.
 830          */
 831         ticks2 = timer0->TimerValue & 0xffff;
 832         do {
 833                 ticks1 = ticks2;
 834                 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
 835                 ticks2 = timer0->TimerValue & 0xffff;
 836         } while (ticks2 > ticks1);
 837
 838         /*
 839          * Number of ticks since last interrupt.
 840          */
 841         ticks1 = TIMER_RELOAD - ticks2;
 842
 843         /*
 844          * Interrupt pending?  If so, we've reloaded once already.
 845          *
 846          * FIXME: Need to check this is effectively timer 0 that expires
 847          */
 848         if (status & IRQMASK_TIMERINT0_1)
 849                 ticks1 += TIMER_RELOAD;
 850
 851         /*
 852          * Convert the ticks to usecs
 853          */
 854         return TICKS2USECS(ticks1);
 855 }
 856
 857 /*
 858  * IRQ handler for the timer
 859  */
 860 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 861 {
 862         volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
 863
 864         write_seqlock(&xtime_lock);
 865
 866         // ...clear the interrupt
 867         timer0->TimerClear = 1;
 868
 869         timer_tick(regs);
 870
 871         write_sequnlock(&xtime_lock);
 872
 873         return IRQ_HANDLED;
 874 }
 875
 876 static struct irqaction versatile_timer_irq = {
 877         .name           = "Versatile Timer Tick",
 878         .flags          = SA_INTERRUPT,
 879         .handler        = versatile_timer_interrupt
 880 };
 881
 882 /*
 883  * Set up timer interrupt, and return the current time in seconds.
 884  */
 885 static void __init versatile_timer_init(void)
 886 {
 887         volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
 888         volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
 889         volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
 890         volatile TimerStruct_t *timer3 = (volatile TimerStruct_t *)TIMER3_VA_BASE;
 891
 892         /*
 893          * set clock frequency:
 894          *      VERSATILE_REFCLK is 32KHz
 895          *      VERSATILE_TIMCLK is 1MHz
 896          */
 897         *(volatile unsigned int *)IO_ADDRESS(VERSATILE_SCTL_BASE) |=
 898           ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 899            (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
 900
 901         /*
 902          * Initialise to a known state (all timers off)
 903          */
 904         timer0->TimerControl = 0;
 905         timer1->TimerControl = 0;
 906         timer2->TimerControl = 0;
 907         timer3->TimerControl = 0;
 908
 909         timer0->TimerLoad    = TIMER_RELOAD;
 910         timer0->TimerValue   = TIMER_RELOAD;
 911         timer0->TimerControl = TIMER_CTRL | 0x40 | TIMER_CTRL_IE;  /* periodic + IE */
 912
 913         /*
 914          * Make irqs happen for the system timer
 915          */
 916         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
 917 }
 918
 919 struct sys_timer versatile_timer = {
 920         .init           = versatile_timer_init,
 921         .offset         = versatile_gettimeoffset,
 922 };