arch/mips/pci/ops-it8172.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      IT8172 system controller specific pci support.
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              ppopov@mvista.com or source@mvista.com
   9  *
  10  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36
  37 #include <asm/it8172/it8172.h>
  38 #include <asm/it8172/it8172_pci.h>
  39
  40 #define PCI_ACCESS_READ  0
  41 #define PCI_ACCESS_WRITE 1
  42
  43 #undef DEBUG
  44 #ifdef DEBUG
  45 #define DBG(x...) printk(x)
  46 #else
  47 #define DBG(x...)
  48 #endif
  49
  50 static struct resource pci_mem_resource_1;
  51
  52 static struct resource pci_io_resource = {
  53         "io pci IO space",
  54         0x14018000,
  55         0x17FFFFFF,
  56         IORESOURCE_IO
  57 };
  58
  59 static struct resource pci_mem_resource_0 = {
  60         "ext pci memory space 0/1",
  61         0x10101000,
  62         0x13FFFFFF,
  63         IORESOURCE_MEM,
  64         &pci_mem_resource_0,
  65         NULL,
  66         &pci_mem_resource_1
  67 };
  68
  69 static struct resource pci_mem_resource_1 = {
  70         "ext pci memory space 2/3",
  71         0x1A000000,
  72         0x1FBFFFFF,
  73         IORESOURCE_MEM,
  74         &pci_mem_resource_0,
  75         NULL,
  76         NULL
  77 };
  78
  79 extern struct pci_ops it8172_pci_ops;
  80
  81 struct pci_controller it8172_controller = {
  82         .pci_ops        = &it8172_pci_ops,
  83         .io_resource    = &pci_io_resource,
  84         .mem_resource   = &pci_mem_resource_0,
  85 };
  86
  87 static int it8172_pcibios_config_access(unsigned char access_type,
  88                                         struct pci_bus *bus,
  89                                         unsigned int devfn, int where,
  90                                         u32 * data)
  91 {
  92         /*
  93          * config cycles are on 4 byte boundary only
  94          */
  95
  96         /* Setup address */
  97         IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
  98                  (devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
  99
 100         if (access_type == PCI_ACCESS_WRITE) {
 101                 IT_WRITE(IT_CONFDATA, *data);
 102         } else {
 103                 IT_READ(IT_CONFDATA, *data);
 104         }
 105
 106         /*
 107          * Revisit: check for master or target abort.
 108          */
 109         return 0;
 110 }
 111
 112
 113 /*
 114  * We can't address 8 and 16 bit words directly.  Instead we have to
 115  * read/write a 32bit word and mask/modify the data we actually want.
 116  */
 117 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
 118                     int size, u32 val)
 119 {
 120         u32 data = 0;
 121
 122         switch (size) {
 123         case 1:
 124                 if (it8172_pcibios_config_access
 125                     (PCI_ACCESS_READ, dev, where, &data))
 126                         return -1;
 127
 128                 *val = (data >> ((where & 3) << 3)) & 0xff;
 129
 130                 return PCIBIOS_SUCCESSFUL;
 131
 132         case 2:
 133
 134                 if (where & 1)
 135                         return PCIBIOS_BAD_REGISTER_NUMBER;
 136
 137                 if (it8172_pcibios_config_access
 138                     (PCI_ACCESS_READ, dev, where, &data))
 139                         return -1;
 140
 141                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 142                 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
 143                     dev->bus->number, dev->devfn, where, *val);
 144
 145                 return PCIBIOS_SUCCESSFUL;
 146
 147         case 4:
 148
 149                 if (where & 3)
 150                         return PCIBIOS_BAD_REGISTER_NUMBER;
 151
 152                 if (it8172_pcibios_config_access
 153                     (PCI_ACCESS_READ, dev, where, &data))
 154                         return -1;
 155
 156                 *val = data;
 157
 158                 return PCIBIOS_SUCCESSFUL;
 159         }
 160 }
 161
 162
 163 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
 164                     int size, u32 val)
 165 {
 166         u32 data = 0;
 167
 168         switch (size) {
 169         case 1:
 170                 if (it8172_pcibios_config_access
 171                     (PCI_ACCESS_READ, dev, where, &data))
 172                         return -1;
 173
 174                 data = (data & ~(0xff << ((where & 3) << 3))) |
 175                     (val << ((where & 3) << 3));
 176
 177                 if (it8172_pcibios_config_access
 178                     (PCI_ACCESS_WRITE, dev, where, &data))
 179                         return -1;
 180
 181                 return PCIBIOS_SUCCESSFUL;
 182
 183         case 2:
 184                 if (where & 1)
 185                         return PCIBIOS_BAD_REGISTER_NUMBER;
 186
 187                 if (it8172_pcibios_config_access
 188                     (PCI_ACCESS_READ, dev, where, &data))
 189                         eturn - 1;
 190
 191                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 192                     (val << ((where & 3) << 3));
 193
 194                 if (it8172_pcibios_config_access
 195                     (PCI_ACCESS_WRITE, dev, where, &data))
 196                         return -1;
 197
 198                 return PCIBIOS_SUCCESSFUL;
 199
 200         case 4:
 201                 if (where & 3)
 202                         return PCIBIOS_BAD_REGISTER_NUMBER;
 203
 204                 if (it8172_pcibios_config_access
 205                     (PCI_ACCESS_WRITE, dev, where, &val))
 206                         return -1;
 207
 208                 return PCIBIOS_SUCCESSFUL;
 209         }
 210 }
 211
 212 struct pci_ops it8172_pci_ops = {
 213         .read = read_config,
 214         .write = write_config,
 215 };