include/asm-m32r/m32700ut/m32700ut_lan.h

   1 /*
   2  * include/asm/m32700ut_lan.h
   3  *
   4  * M32700UT-LAN board
   5  *
   6  * Copyright (c) 2002   Takeo Takahashi
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License.  See the file "COPYING" in the main directory of
  10  * this archive for more details.
  11  *
  12  * $Id$
  13  */
  14
  15 #ifndef _M32700UT_M32700UT_LAN_H
  16 #define _M32700UT_M32700UT_LAN_H
  17
  18 #include <linux/config.h>
  19
  20 #ifndef __ASSEMBLY__
  21 /*
  22  * C functions use non-cache address.
  23  */
  24 #define M32700UT_LAN_BASE       (0x10000000 /* + NONCACHE_OFFSET */)
  25 #else
  26 #define M32700UT_LAN_BASE       (0x10000000 + NONCACHE_OFFSET)
  27 #endif  /* __ASSEMBLY__ */
  28
  29 /* ICU
  30  *  ICUISTS:    status register
  31  *  ICUIREQ0:   request register
  32  *  ICUIREQ1:   request register
  33  *  ICUCR3:     control register for CFIREQ# interrupt
  34  *  ICUCR4:     control register for CFC Card insert interrupt
  35  *  ICUCR5:     control register for CFC Card eject interrupt
  36  *  ICUCR6:     control register for external interrupt
  37  *  ICUCR11:    control register for MMC Card insert/eject interrupt
  38  *  ICUCR13:    control register for SC error interrupt
  39  *  ICUCR14:    control register for SC receive interrupt
  40  *  ICUCR15:    control register for SC send interrupt
  41  *  ICUCR16:    control register for SIO0 receive interrupt
  42  *  ICUCR17:    control register for SIO0 send interrupt
  43  */
  44 #define M32700UT_LAN_IRQ_LAN    (M32700UT_LAN_PLD_IRQ_BASE + 1) /* LAN */
  45 #define M32700UT_LAN_IRQ_I2C    (M32700UT_LAN_PLD_IRQ_BASE + 3) /* I2C */
  46
  47 #define M32700UT_LAN_ICUISTS    __reg16(M32700UT_LAN_BASE + 0xc0002)
  48 #define M32700UT_LAN_ICUISTS_VECB_MASK  (0xf000)
  49 #define M32700UT_LAN_VECB(x)    ((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
  50 #define M32700UT_LAN_ICUISTS_ISN_MASK   (0x07c0)
  51 #define M32700UT_LAN_ICUISTS_ISN(x)     ((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
  52 #define M32700UT_LAN_ICUIREQ0   __reg16(M32700UT_LAN_BASE + 0xc0004)
  53 #define M32700UT_LAN_ICUCR1     __reg16(M32700UT_LAN_BASE + 0xc0010)
  54 #define M32700UT_LAN_ICUCR3     __reg16(M32700UT_LAN_BASE + 0xc0014)
  55
  56 /*
  57  * AR register on PLD
  58  */
  59 #define ARVCR0          __reg32(M32700UT_LAN_BASE + 0x40000)
  60 #define ARVCR0_VDS              0x00080000
  61 #define ARVCR0_RST              0x00010000
  62 #define ARVCR1          __reg32(M32700UT_LAN_BASE + 0x40004)
  63 #define ARVCR1_QVGA             0x02000000
  64 #define ARVCR1_NORMAL           0x01000000
  65 #define ARVCR1_HIEN             0x00010000
  66 #define ARVHCOUNT       __reg32(M32700UT_LAN_BASE + 0x40008)
  67 #define ARDATA          __reg32(M32700UT_LAN_BASE + 0x40010)
  68 #define ARINTSEL        __reg32(M32700UT_LAN_BASE + 0x40014)
  69 #define ARINTSEL_INT3           0x10000000      /* CPU INT3 */
  70 #define ARDATA32        __reg32(M32700UT_LAN_BASE + 0x04040010) // Block 5
  71 /*
  72 #define ARINTSEL_SEL2           0x00002000
  73 #define ARINTSEL_SEL3           0x00001000
  74 #define ARINTSEL_SEL6           0x00000200
  75 #define ARINTSEL_SEL7           0x00000100
  76 #define ARINTSEL_SEL9           0x00000040
  77 #define ARINTSEL_SEL10          0x00000020
  78 #define ARINTSEL_SEL11          0x00000010
  79 #define ARINTSEL_SEL12          0x00000008
  80 */
  81
  82 /*
  83  * I2C register on PLD
  84  */
  85 #define PLDI2CCR        __reg32(M32700UT_LAN_BASE + 0x40040)
  86 #define PLDI2CCR_ES0            0x00000001      /* enable I2C interface */
  87 #define PLDI2CMOD       __reg32(M32700UT_LAN_BASE + 0x40044)
  88 #define PLDI2CMOD_ACKCLK        0x00000200
  89 #define PLDI2CMOD_DTWD          0x00000100
  90 #define PLDI2CMOD_10BT          0x00000004
  91 #define PLDI2CMOD_ATM_NORMAL    0x00000000
  92 #define PLDI2CMOD_ATM_AUTO      0x00000003
  93 #define PLDI2CACK       __reg32(M32700UT_LAN_BASE + 0x40048)
  94 #define PLDI2CACK_ACK           0x00000001
  95 #define PLDI2CFREQ      __reg32(M32700UT_LAN_BASE + 0x4004c)
  96 #define PLDI2CCND       __reg32(M32700UT_LAN_BASE + 0x40050)
  97 #define PLDI2CCND_START         0x00000001
  98 #define PLDI2CCND_STOP          0x00000002
  99 #define PLDI2CSTEN      __reg32(M32700UT_LAN_BASE + 0x40054)
 100 #define PLDI2CSTEN_STEN         0x00000001
 101 #define PLDI2CDATA      __reg32(M32700UT_LAN_BASE + 0x40060)
 102 #define PLDI2CSTS       __reg32(M32700UT_LAN_BASE + 0x40064)
 103 #define PLDI2CSTS_TRX           0x00000020
 104 #define PLDI2CSTS_BB            0x00000010
 105 #define PLDI2CSTS_NOACK         0x00000001      /* 0:ack, 1:noack */
 106
 107 #endif  /* _M32700UT_M32700UT_LAN_H */