2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/config.h>
35 #include <linux/bitops.h>
36 #include <asm/processor.h> /* Processor type for cache alignment. */
38 #include <asm/cache.h>
40 /* This is only here until the firmware is ready. In that case,
41 the firmware leaves the ethernet address in the register for us. */
42 #ifdef CONFIG_SIBYTE_STANDALONE
43 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
44 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
45 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
49 /* These identify the driver base version and may not be removed. */
51 static char version1
[] __devinitdata
=
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
56 /* Operational parameters that usually are not changed. */
58 #define CONFIG_SBMAC_COALESCE
60 #define MAX_UNITS 3 /* More are supported, limit only on options */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (2*HZ)
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
69 /* A few user-configurable values which may be modified when a driver
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
74 module_param(debug
, int, S_IRUGO
);
75 MODULE_PARM_DESC(debug
, "Debug messages");
78 static int noisy_mii
= 1;
79 module_param(noisy_mii
, int, S_IRUGO
);
80 MODULE_PARM_DESC(noisy_mii
, "MII status messages");
82 /* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
85 The media type is usually passed in 'options[]'.
88 static int options
[MAX_UNITS
] = {-1, -1, -1};
89 module_param_array(options
, int, NULL
, S_IRUGO
);
90 MODULE_PARM_DESC(options
, "1-" __MODULE_STRING(MAX_UNITS
));
92 static int full_duplex
[MAX_UNITS
] = {-1, -1, -1};
93 module_param_array(full_duplex
, int, NULL
, S_IRUGO
);
94 MODULE_PARM_DESC(full_duplex
, "1-" __MODULE_STRING(MAX_UNITS
));
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt
= 0;
99 module_param(int_pktcnt
, int, S_IRUGO
);
100 MODULE_PARM_DESC(int_pktcnt
, "Packet count");
102 static int int_timeout
= 0;
103 module_param(int_timeout
, int, S_IRUGO
);
104 MODULE_PARM_DESC(int_timeout
, "Timeout value");
107 #include <asm/sibyte/sb1250.h>
108 #include <asm/sibyte/sb1250_defs.h>
109 #include <asm/sibyte/sb1250_regs.h>
110 #include <asm/sibyte/sb1250_mac.h>
111 #include <asm/sibyte/sb1250_dma.h>
112 #include <asm/sibyte/sb1250_int.h>
113 #include <asm/sibyte/sb1250_scd.h>
116 /**********************************************************************
118 ********************************************************************* */
121 typedef enum { sbmac_speed_auto
, sbmac_speed_10
,
122 sbmac_speed_100
, sbmac_speed_1000
} sbmac_speed_t
;
124 typedef enum { sbmac_duplex_auto
, sbmac_duplex_half
,
125 sbmac_duplex_full
} sbmac_duplex_t
;
127 typedef enum { sbmac_fc_auto
, sbmac_fc_disabled
, sbmac_fc_frame
,
128 sbmac_fc_collision
, sbmac_fc_carrier
} sbmac_fc_t
;
130 typedef enum { sbmac_state_uninit
, sbmac_state_off
, sbmac_state_on
,
131 sbmac_state_broken
} sbmac_state_t
;
134 /**********************************************************************
136 ********************************************************************* */
139 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
140 (d)->sbdma_dscrtable : (d)->f+1)
143 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
145 #define SBMAC_MAX_TXDESCR 32
146 #define SBMAC_MAX_RXDESCR 32
148 #define ETHER_ALIGN 2
149 #define ETHER_ADDR_LEN 6
150 #define ENET_PACKET_SIZE 1518
151 /*#define ENET_PACKET_SIZE 9216 */
153 /**********************************************************************
154 * DMA Descriptor structure
155 ********************************************************************* */
157 typedef struct sbdmadscr_s
{
162 typedef unsigned long paddr_t
;
164 /**********************************************************************
165 * DMA Controller structure
166 ********************************************************************* */
168 typedef struct sbmacdma_s
{
171 * This stuff is used to identify the channel and the registers
172 * associated with it.
175 struct sbmac_softc
*sbdma_eth
; /* back pointer to associated MAC */
176 int sbdma_channel
; /* channel number */
177 int sbdma_txdir
; /* direction (1=transmit) */
178 int sbdma_maxdescr
; /* total # of descriptors in ring */
179 #ifdef CONFIG_SBMAC_COALESCE
180 int sbdma_int_pktcnt
; /* # descriptors rx/tx before interrupt*/
181 int sbdma_int_timeout
; /* # usec rx/tx interrupt */
184 volatile void __iomem
*sbdma_config0
; /* DMA config register 0 */
185 volatile void __iomem
*sbdma_config1
; /* DMA config register 1 */
186 volatile void __iomem
*sbdma_dscrbase
; /* Descriptor base address */
187 volatile void __iomem
*sbdma_dscrcnt
; /* Descriptor count register */
188 volatile void __iomem
*sbdma_curdscr
; /* current descriptor address */
191 * This stuff is for maintenance of the ring
194 sbdmadscr_t
*sbdma_dscrtable
; /* base of descriptor table */
195 sbdmadscr_t
*sbdma_dscrtable_end
; /* end of descriptor table */
197 struct sk_buff
**sbdma_ctxtable
; /* context table, one per descr */
199 paddr_t sbdma_dscrtable_phys
; /* and also the phys addr */
200 sbdmadscr_t
*sbdma_addptr
; /* next dscr for sw to add */
201 sbdmadscr_t
*sbdma_remptr
; /* next dscr for sw to remove */
205 /**********************************************************************
206 * Ethernet softc structure
207 ********************************************************************* */
212 * Linux-specific things
215 struct net_device
*sbm_dev
; /* pointer to linux device */
216 spinlock_t sbm_lock
; /* spin lock */
217 struct timer_list sbm_timer
; /* for monitoring MII */
218 struct net_device_stats sbm_stats
;
219 int sbm_devflags
; /* current device flags */
222 int sbm_phy_oldanlpar
;
223 int sbm_phy_oldk1stsr
;
224 int sbm_phy_oldlinkstat
;
227 unsigned char sbm_phys
[2];
230 * Controller-specific things
233 volatile void __iomem
*sbm_base
; /* MAC's base address */
234 sbmac_state_t sbm_state
; /* current state */
236 volatile void __iomem
*sbm_macenable
; /* MAC Enable Register */
237 volatile void __iomem
*sbm_maccfg
; /* MAC Configuration Register */
238 volatile void __iomem
*sbm_fifocfg
; /* FIFO configuration register */
239 volatile void __iomem
*sbm_framecfg
; /* Frame configuration register */
240 volatile void __iomem
*sbm_rxfilter
; /* receive filter register */
241 volatile void __iomem
*sbm_isr
; /* Interrupt status register */
242 volatile void __iomem
*sbm_imr
; /* Interrupt mask register */
243 volatile void __iomem
*sbm_mdio
; /* MDIO register */
245 sbmac_speed_t sbm_speed
; /* current speed */
246 sbmac_duplex_t sbm_duplex
; /* current duplex */
247 sbmac_fc_t sbm_fc
; /* current flow control setting */
249 unsigned char sbm_hwaddr
[ETHER_ADDR_LEN
];
251 sbmacdma_t sbm_txdma
; /* for now, only use channel 0 */
252 sbmacdma_t sbm_rxdma
;
258 /**********************************************************************
260 ********************************************************************* */
262 /**********************************************************************
264 ********************************************************************* */
266 static void sbdma_initctx(sbmacdma_t
*d
,
267 struct sbmac_softc
*s
,
271 static void sbdma_channel_start(sbmacdma_t
*d
, int rxtx
);
272 static int sbdma_add_rcvbuffer(sbmacdma_t
*d
,struct sk_buff
*m
);
273 static int sbdma_add_txbuffer(sbmacdma_t
*d
,struct sk_buff
*m
);
274 static void sbdma_emptyring(sbmacdma_t
*d
);
275 static void sbdma_fillring(sbmacdma_t
*d
);
276 static void sbdma_rx_process(struct sbmac_softc
*sc
,sbmacdma_t
*d
);
277 static void sbdma_tx_process(struct sbmac_softc
*sc
,sbmacdma_t
*d
);
278 static int sbmac_initctx(struct sbmac_softc
*s
);
279 static void sbmac_channel_start(struct sbmac_softc
*s
);
280 static void sbmac_channel_stop(struct sbmac_softc
*s
);
281 static sbmac_state_t
sbmac_set_channel_state(struct sbmac_softc
*,sbmac_state_t
);
282 static void sbmac_promiscuous_mode(struct sbmac_softc
*sc
,int onoff
);
283 static uint64_t sbmac_addr2reg(unsigned char *ptr
);
284 static irqreturn_t
sbmac_intr(int irq
,void *dev_instance
,struct pt_regs
*rgs
);
285 static int sbmac_start_tx(struct sk_buff
*skb
, struct net_device
*dev
);
286 static void sbmac_setmulti(struct sbmac_softc
*sc
);
287 static int sbmac_init(struct net_device
*dev
, int idx
);
288 static int sbmac_set_speed(struct sbmac_softc
*s
,sbmac_speed_t speed
);
289 static int sbmac_set_duplex(struct sbmac_softc
*s
,sbmac_duplex_t duplex
,sbmac_fc_t fc
);
291 static int sbmac_open(struct net_device
*dev
);
292 static void sbmac_timer(unsigned long data
);
293 static void sbmac_tx_timeout (struct net_device
*dev
);
294 static struct net_device_stats
*sbmac_get_stats(struct net_device
*dev
);
295 static void sbmac_set_rx_mode(struct net_device
*dev
);
296 static int sbmac_mii_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
297 static int sbmac_close(struct net_device
*dev
);
298 static int sbmac_mii_poll(struct sbmac_softc
*s
,int noisy
);
299 static int sbmac_mii_probe(struct net_device
*dev
);
301 static void sbmac_mii_sync(struct sbmac_softc
*s
);
302 static void sbmac_mii_senddata(struct sbmac_softc
*s
,unsigned int data
, int bitcnt
);
303 static unsigned int sbmac_mii_read(struct sbmac_softc
*s
,int phyaddr
,int regidx
);
304 static void sbmac_mii_write(struct sbmac_softc
*s
,int phyaddr
,int regidx
,
305 unsigned int regval
);
308 /**********************************************************************
310 ********************************************************************* */
312 static uint64_t sbmac_orig_hwaddr
[MAX_UNITS
];
315 /**********************************************************************
317 ********************************************************************* */
319 #define MII_COMMAND_START 0x01
320 #define MII_COMMAND_READ 0x02
321 #define MII_COMMAND_WRITE 0x01
322 #define MII_COMMAND_ACK 0x02
324 #define BMCR_RESET 0x8000
325 #define BMCR_LOOPBACK 0x4000
326 #define BMCR_SPEED0 0x2000
327 #define BMCR_ANENABLE 0x1000
328 #define BMCR_POWERDOWN 0x0800
329 #define BMCR_ISOLATE 0x0400
330 #define BMCR_RESTARTAN 0x0200
331 #define BMCR_DUPLEX 0x0100
332 #define BMCR_COLTEST 0x0080
333 #define BMCR_SPEED1 0x0040
334 #define BMCR_SPEED1000 BMCR_SPEED1
335 #define BMCR_SPEED100 BMCR_SPEED0
336 #define BMCR_SPEED10 0
338 #define BMSR_100BT4 0x8000
339 #define BMSR_100BT_FDX 0x4000
340 #define BMSR_100BT_HDX 0x2000
341 #define BMSR_10BT_FDX 0x1000
342 #define BMSR_10BT_HDX 0x0800
343 #define BMSR_100BT2_FDX 0x0400
344 #define BMSR_100BT2_HDX 0x0200
345 #define BMSR_1000BT_XSR 0x0100
346 #define BMSR_PRESUP 0x0040
347 #define BMSR_ANCOMPLT 0x0020
348 #define BMSR_REMFAULT 0x0010
349 #define BMSR_AUTONEG 0x0008
350 #define BMSR_LINKSTAT 0x0004
351 #define BMSR_JABDETECT 0x0002
352 #define BMSR_EXTCAPAB 0x0001
354 #define PHYIDR1 0x2000
355 #define PHYIDR2 0x5C60
357 #define ANAR_NP 0x8000
358 #define ANAR_RF 0x2000
359 #define ANAR_ASYPAUSE 0x0800
360 #define ANAR_PAUSE 0x0400
361 #define ANAR_T4 0x0200
362 #define ANAR_TXFD 0x0100
363 #define ANAR_TXHD 0x0080
364 #define ANAR_10FD 0x0040
365 #define ANAR_10HD 0x0020
366 #define ANAR_PSB 0x0001
368 #define ANLPAR_NP 0x8000
369 #define ANLPAR_ACK 0x4000
370 #define ANLPAR_RF 0x2000
371 #define ANLPAR_ASYPAUSE 0x0800
372 #define ANLPAR_PAUSE 0x0400
373 #define ANLPAR_T4 0x0200
374 #define ANLPAR_TXFD 0x0100
375 #define ANLPAR_TXHD 0x0080
376 #define ANLPAR_10FD 0x0040
377 #define ANLPAR_10HD 0x0020
378 #define ANLPAR_PSB 0x0001 /* 802.3 */
380 #define ANER_PDF 0x0010
381 #define ANER_LPNPABLE 0x0008
382 #define ANER_NPABLE 0x0004
383 #define ANER_PAGERX 0x0002
384 #define ANER_LPANABLE 0x0001
386 #define ANNPTR_NP 0x8000
387 #define ANNPTR_MP 0x2000
388 #define ANNPTR_ACK2 0x1000
389 #define ANNPTR_TOGTX 0x0800
390 #define ANNPTR_CODE 0x0008
392 #define ANNPRR_NP 0x8000
393 #define ANNPRR_MP 0x2000
394 #define ANNPRR_ACK3 0x1000
395 #define ANNPRR_TOGTX 0x0800
396 #define ANNPRR_CODE 0x0008
398 #define K1TCR_TESTMODE 0x0000
399 #define K1TCR_MSMCE 0x1000
400 #define K1TCR_MSCV 0x0800
401 #define K1TCR_RPTR 0x0400
402 #define K1TCR_1000BT_FDX 0x200
403 #define K1TCR_1000BT_HDX 0x100
405 #define K1STSR_MSMCFLT 0x8000
406 #define K1STSR_MSCFGRES 0x4000
407 #define K1STSR_LRSTAT 0x2000
408 #define K1STSR_RRSTAT 0x1000
409 #define K1STSR_LP1KFD 0x0800
410 #define K1STSR_LP1KHD 0x0400
411 #define K1STSR_LPASMDIR 0x0200
413 #define K1SCR_1KX_FDX 0x8000
414 #define K1SCR_1KX_HDX 0x4000
415 #define K1SCR_1KT_FDX 0x2000
416 #define K1SCR_1KT_HDX 0x1000
418 #define STRAP_PHY1 0x0800
419 #define STRAP_NCMODE 0x0400
420 #define STRAP_MANMSCFG 0x0200
421 #define STRAP_ANENABLE 0x0100
422 #define STRAP_MSVAL 0x0080
423 #define STRAP_1KHDXADV 0x0010
424 #define STRAP_1KFDXADV 0x0008
425 #define STRAP_100ADV 0x0004
426 #define STRAP_SPEEDSEL 0x0000
427 #define STRAP_SPEED100 0x0001
429 #define PHYSUP_SPEED1000 0x10
430 #define PHYSUP_SPEED100 0x08
431 #define PHYSUP_SPEED10 0x00
432 #define PHYSUP_LINKUP 0x04
433 #define PHYSUP_FDX 0x02
435 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
436 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
437 #define MII_PHYIDR1 0x02
438 #define MII_PHYIDR2 0x03
440 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
441 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
444 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
449 /**********************************************************************
452 * Synchronize with the MII - send a pattern of bits to the MII
453 * that will guarantee that it is ready to accept a command.
456 * s - sbmac structure
460 ********************************************************************* */
462 static void sbmac_mii_sync(struct sbmac_softc
*s
)
468 mac_mdio_genc
= __raw_readq(s
->sbm_mdio
) & M_MAC_GENC
;
470 bits
= M_MAC_MDIO_DIR_OUTPUT
| M_MAC_MDIO_OUT
;
472 __raw_writeq(bits
| mac_mdio_genc
, s
->sbm_mdio
);
474 for (cnt
= 0; cnt
< 32; cnt
++) {
475 __raw_writeq(bits
| M_MAC_MDC
| mac_mdio_genc
, s
->sbm_mdio
);
476 __raw_writeq(bits
| mac_mdio_genc
, s
->sbm_mdio
);
480 /**********************************************************************
481 * SBMAC_MII_SENDDATA(s,data,bitcnt)
483 * Send some bits to the MII. The bits to be sent are right-
484 * justified in the 'data' parameter.
487 * s - sbmac structure
488 * data - data to send
489 * bitcnt - number of bits to send
490 ********************************************************************* */
492 static void sbmac_mii_senddata(struct sbmac_softc
*s
,unsigned int data
, int bitcnt
)
496 unsigned int curmask
;
499 mac_mdio_genc
= __raw_readq(s
->sbm_mdio
) & M_MAC_GENC
;
501 bits
= M_MAC_MDIO_DIR_OUTPUT
;
502 __raw_writeq(bits
| mac_mdio_genc
, s
->sbm_mdio
);
504 curmask
= 1 << (bitcnt
- 1);
506 for (i
= 0; i
< bitcnt
; i
++) {
508 bits
|= M_MAC_MDIO_OUT
;
509 else bits
&= ~M_MAC_MDIO_OUT
;
510 __raw_writeq(bits
| mac_mdio_genc
, s
->sbm_mdio
);
511 __raw_writeq(bits
| M_MAC_MDC
| mac_mdio_genc
, s
->sbm_mdio
);
512 __raw_writeq(bits
| mac_mdio_genc
, s
->sbm_mdio
);
519 /**********************************************************************
520 * SBMAC_MII_READ(s,phyaddr,regidx)
522 * Read a PHY register.
525 * s - sbmac structure
526 * phyaddr - PHY's address
527 * regidx = index of register to read
530 * value read, or 0 if an error occurred.
531 ********************************************************************* */
533 static unsigned int sbmac_mii_read(struct sbmac_softc
*s
,int phyaddr
,int regidx
)
541 * Synchronize ourselves so that the PHY knows the next
542 * thing coming down is a command
548 * Send the data to the PHY. The sequence is
549 * a "start" command (2 bits)
550 * a "read" command (2 bits)
551 * the PHY addr (5 bits)
552 * the register index (5 bits)
555 sbmac_mii_senddata(s
,MII_COMMAND_START
, 2);
556 sbmac_mii_senddata(s
,MII_COMMAND_READ
, 2);
557 sbmac_mii_senddata(s
,phyaddr
, 5);
558 sbmac_mii_senddata(s
,regidx
, 5);
560 mac_mdio_genc
= __raw_readq(s
->sbm_mdio
) & M_MAC_GENC
;
563 * Switch the port around without a clock transition.
565 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, s
->sbm_mdio
);
568 * Send out a clock pulse to signal we want the status
571 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| M_MAC_MDC
| mac_mdio_genc
, s
->sbm_mdio
);
572 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, s
->sbm_mdio
);
575 * If an error occurred, the PHY will signal '1' back
577 error
= __raw_readq(s
->sbm_mdio
) & M_MAC_MDIO_IN
;
580 * Issue an 'idle' clock pulse, but keep the direction
583 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| M_MAC_MDC
| mac_mdio_genc
, s
->sbm_mdio
);
584 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, s
->sbm_mdio
);
588 for (idx
= 0; idx
< 16; idx
++) {
592 if (__raw_readq(s
->sbm_mdio
) & M_MAC_MDIO_IN
)
596 __raw_writeq(M_MAC_MDIO_DIR_INPUT
|M_MAC_MDC
| mac_mdio_genc
, s
->sbm_mdio
);
597 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, s
->sbm_mdio
);
600 /* Switch back to output */
601 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT
| mac_mdio_genc
, s
->sbm_mdio
);
609 /**********************************************************************
610 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
612 * Write a value to a PHY register.
615 * s - sbmac structure
616 * phyaddr - PHY to use
617 * regidx - register within the PHY
618 * regval - data to write to register
622 ********************************************************************* */
624 static void sbmac_mii_write(struct sbmac_softc
*s
,int phyaddr
,int regidx
,
631 sbmac_mii_senddata(s
,MII_COMMAND_START
,2);
632 sbmac_mii_senddata(s
,MII_COMMAND_WRITE
,2);
633 sbmac_mii_senddata(s
,phyaddr
, 5);
634 sbmac_mii_senddata(s
,regidx
, 5);
635 sbmac_mii_senddata(s
,MII_COMMAND_ACK
,2);
636 sbmac_mii_senddata(s
,regval
,16);
638 mac_mdio_genc
= __raw_readq(s
->sbm_mdio
) & M_MAC_GENC
;
640 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT
| mac_mdio_genc
, s
->sbm_mdio
);
645 /**********************************************************************
646 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
648 * Initialize a DMA channel context. Since there are potentially
649 * eight DMA channels per MAC, it's nice to do this in a standard
653 * d - sbmacdma_t structure (DMA channel context)
654 * s - sbmac_softc structure (pointer to a MAC)
655 * chan - channel number (0..1 right now)
656 * txrx - Identifies DMA_TX or DMA_RX for channel direction
657 * maxdescr - number of descriptors
661 ********************************************************************* */
663 static void sbdma_initctx(sbmacdma_t
*d
,
664 struct sbmac_softc
*s
,
670 * Save away interesting stuff in the structure
674 d
->sbdma_channel
= chan
;
675 d
->sbdma_txdir
= txrx
;
679 s
->sbe_idx
=(s
->sbm_base
- A_MAC_BASE_0
)/MAC_SPACING
;
682 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_BYTES
)));
683 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_COLLISIONS
)));
684 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_LATE_COL
)));
685 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_EX_COL
)));
686 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_FCS_ERROR
)));
687 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_ABORT
)));
688 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_BAD
)));
689 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_GOOD
)));
690 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_RUNT
)));
691 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_TX_OVERSIZE
)));
692 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_BYTES
)));
693 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_MCAST
)));
694 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_BCAST
)));
695 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_BAD
)));
696 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_GOOD
)));
697 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_RUNT
)));
698 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_OVERSIZE
)));
699 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_FCS_ERROR
)));
700 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_LENGTH_ERROR
)));
701 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_CODE_ERROR
)));
702 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s
->sbe_idx
, R_MAC_RMON_RX_ALIGN_ERROR
)));
705 * initialize register pointers
709 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CONFIG0
);
711 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CONFIG1
);
713 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_DSCR_BASE
);
715 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_DSCR_CNT
);
717 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CUR_DSCRADDR
);
720 * Allocate memory for the ring
723 d
->sbdma_maxdescr
= maxdescr
;
725 d
->sbdma_dscrtable
= (sbdmadscr_t
*)
726 kmalloc((d
->sbdma_maxdescr
+1)*sizeof(sbdmadscr_t
), GFP_KERNEL
);
729 * The descriptor table must be aligned to at least 16 bytes or the
730 * MAC will corrupt it.
732 d
->sbdma_dscrtable
= (sbdmadscr_t
*)
733 ALIGN((unsigned long)d
->sbdma_dscrtable
, sizeof(sbdmadscr_t
));
735 memset(d
->sbdma_dscrtable
,0,d
->sbdma_maxdescr
*sizeof(sbdmadscr_t
));
737 d
->sbdma_dscrtable_end
= d
->sbdma_dscrtable
+ d
->sbdma_maxdescr
;
739 d
->sbdma_dscrtable_phys
= virt_to_phys(d
->sbdma_dscrtable
);
745 d
->sbdma_ctxtable
= (struct sk_buff
**)
746 kmalloc(d
->sbdma_maxdescr
*sizeof(struct sk_buff
*), GFP_KERNEL
);
748 memset(d
->sbdma_ctxtable
,0,d
->sbdma_maxdescr
*sizeof(struct sk_buff
*));
750 #ifdef CONFIG_SBMAC_COALESCE
752 * Setup Rx/Tx DMA coalescing defaults
756 d
->sbdma_int_pktcnt
= int_pktcnt
;
758 d
->sbdma_int_pktcnt
= 1;
762 d
->sbdma_int_timeout
= int_timeout
;
764 d
->sbdma_int_timeout
= 0;
770 /**********************************************************************
771 * SBDMA_CHANNEL_START(d)
773 * Initialize the hardware registers for a DMA channel.
776 * d - DMA channel to init (context must be previously init'd
777 * rxtx - DMA_RX or DMA_TX depending on what type of channel
781 ********************************************************************* */
783 static void sbdma_channel_start(sbmacdma_t
*d
, int rxtx
)
786 * Turn on the DMA channel
789 #ifdef CONFIG_SBMAC_COALESCE
790 __raw_writeq(V_DMA_INT_TIMEOUT(d
->sbdma_int_timeout
) |
791 0, d
->sbdma_config1
);
792 __raw_writeq(M_DMA_EOP_INT_EN
|
793 V_DMA_RINGSZ(d
->sbdma_maxdescr
) |
794 V_DMA_INT_PKTCNT(d
->sbdma_int_pktcnt
) |
795 0, d
->sbdma_config0
);
797 __raw_writeq(0, d
->sbdma_config1
);
798 __raw_writeq(V_DMA_RINGSZ(d
->sbdma_maxdescr
) |
799 0, d
->sbdma_config0
);
802 __raw_writeq(d
->sbdma_dscrtable_phys
, d
->sbdma_dscrbase
);
805 * Initialize ring pointers
808 d
->sbdma_addptr
= d
->sbdma_dscrtable
;
809 d
->sbdma_remptr
= d
->sbdma_dscrtable
;
812 /**********************************************************************
813 * SBDMA_CHANNEL_STOP(d)
815 * Initialize the hardware registers for a DMA channel.
818 * d - DMA channel to init (context must be previously init'd
822 ********************************************************************* */
824 static void sbdma_channel_stop(sbmacdma_t
*d
)
827 * Turn off the DMA channel
830 __raw_writeq(0, d
->sbdma_config1
);
832 __raw_writeq(0, d
->sbdma_dscrbase
);
834 __raw_writeq(0, d
->sbdma_config0
);
840 d
->sbdma_addptr
= NULL
;
841 d
->sbdma_remptr
= NULL
;
844 static void sbdma_align_skb(struct sk_buff
*skb
,int power2
,int offset
)
847 unsigned long newaddr
;
849 addr
= (unsigned long) skb
->data
;
851 newaddr
= (addr
+ power2
- 1) & ~(power2
- 1);
853 skb_reserve(skb
,newaddr
-addr
+offset
);
857 /**********************************************************************
858 * SBDMA_ADD_RCVBUFFER(d,sb)
860 * Add a buffer to the specified DMA channel. For receive channels,
861 * this queues a buffer for inbound packets.
864 * d - DMA channel descriptor
865 * sb - sk_buff to add, or NULL if we should allocate one
868 * 0 if buffer could not be added (ring is full)
869 * 1 if buffer added successfully
870 ********************************************************************* */
873 static int sbdma_add_rcvbuffer(sbmacdma_t
*d
,struct sk_buff
*sb
)
876 sbdmadscr_t
*nextdsc
;
877 struct sk_buff
*sb_new
= NULL
;
878 int pktsize
= ENET_PACKET_SIZE
;
880 /* get pointer to our current place in the ring */
882 dsc
= d
->sbdma_addptr
;
883 nextdsc
= SBDMA_NEXTBUF(d
,sbdma_addptr
);
886 * figure out if the ring is full - if the next descriptor
887 * is the same as the one that we're going to remove from
888 * the ring, the ring is full
891 if (nextdsc
== d
->sbdma_remptr
) {
896 * Allocate a sk_buff if we don't already have one.
897 * If we do have an sk_buff, reset it so that it's empty.
899 * Note: sk_buffs don't seem to be guaranteed to have any sort
900 * of alignment when they are allocated. Therefore, allocate enough
901 * extra space to make sure that:
903 * 1. the data does not start in the middle of a cache line.
904 * 2. The data does not end in the middle of a cache line
905 * 3. The buffer can be aligned such that the IP addresses are
908 * Remember, the SOCs MAC writes whole cache lines at a time,
909 * without reading the old contents first. So, if the sk_buff's
910 * data portion starts in the middle of a cache line, the SOC
911 * DMA will trash the beginning (and ending) portions.
915 sb_new
= dev_alloc_skb(ENET_PACKET_SIZE
+ SMP_CACHE_BYTES
* 2 + ETHER_ALIGN
);
916 if (sb_new
== NULL
) {
917 printk(KERN_INFO
"%s: sk_buff allocation failed\n",
918 d
->sbdma_eth
->sbm_dev
->name
);
922 sbdma_align_skb(sb_new
, SMP_CACHE_BYTES
, ETHER_ALIGN
);
924 /* mark skbuff owned by our device */
925 sb_new
->dev
= d
->sbdma_eth
->sbm_dev
;
930 * nothing special to reinit buffer, it's already aligned
931 * and sb->data already points to a good place.
936 * fill in the descriptor
939 #ifdef CONFIG_SBMAC_COALESCE
941 * Do not interrupt per DMA transfer.
943 dsc
->dscr_a
= virt_to_phys(sb_new
->data
) |
944 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize
+ETHER_ALIGN
)) | 0;
946 dsc
->dscr_a
= virt_to_phys(sb_new
->data
) |
947 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize
+ETHER_ALIGN
)) |
948 M_DMA_DSCRA_INTERRUPT
;
951 /* receiving: no options */
955 * fill in the context
958 d
->sbdma_ctxtable
[dsc
-d
->sbdma_dscrtable
] = sb_new
;
961 * point at next packet
964 d
->sbdma_addptr
= nextdsc
;
967 * Give the buffer to the DMA engine.
970 __raw_writeq(1, d
->sbdma_dscrcnt
);
972 return 0; /* we did it */
975 /**********************************************************************
976 * SBDMA_ADD_TXBUFFER(d,sb)
978 * Add a transmit buffer to the specified DMA channel, causing a
982 * d - DMA channel descriptor
983 * sb - sk_buff to add
986 * 0 transmit queued successfully
987 * otherwise error code
988 ********************************************************************* */
991 static int sbdma_add_txbuffer(sbmacdma_t
*d
,struct sk_buff
*sb
)
994 sbdmadscr_t
*nextdsc
;
999 /* get pointer to our current place in the ring */
1001 dsc
= d
->sbdma_addptr
;
1002 nextdsc
= SBDMA_NEXTBUF(d
,sbdma_addptr
);
1005 * figure out if the ring is full - if the next descriptor
1006 * is the same as the one that we're going to remove from
1007 * the ring, the ring is full
1010 if (nextdsc
== d
->sbdma_remptr
) {
1015 * Under Linux, it's not necessary to copy/coalesce buffers
1016 * like it is on NetBSD. We think they're all contiguous,
1017 * but that may not be true for GBE.
1023 * fill in the descriptor. Note that the number of cache
1024 * blocks in the descriptor is the number of blocks
1025 * *spanned*, so we need to add in the offset (if any)
1026 * while doing the calculation.
1029 phys
= virt_to_phys(sb
->data
);
1030 ncb
= NUMCACHEBLKS(length
+(phys
& (SMP_CACHE_BYTES
- 1)));
1032 dsc
->dscr_a
= phys
|
1033 V_DMA_DSCRA_A_SIZE(ncb
) |
1034 #ifndef CONFIG_SBMAC_COALESCE
1035 M_DMA_DSCRA_INTERRUPT
|
1039 /* transmitting: set outbound options and length */
1041 dsc
->dscr_b
= V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD
) |
1042 V_DMA_DSCRB_PKT_SIZE(length
);
1045 * fill in the context
1048 d
->sbdma_ctxtable
[dsc
-d
->sbdma_dscrtable
] = sb
;
1051 * point at next packet
1054 d
->sbdma_addptr
= nextdsc
;
1057 * Give the buffer to the DMA engine.
1060 __raw_writeq(1, d
->sbdma_dscrcnt
);
1062 return 0; /* we did it */
1068 /**********************************************************************
1069 * SBDMA_EMPTYRING(d)
1071 * Free all allocated sk_buffs on the specified DMA channel;
1078 ********************************************************************* */
1080 static void sbdma_emptyring(sbmacdma_t
*d
)
1085 for (idx
= 0; idx
< d
->sbdma_maxdescr
; idx
++) {
1086 sb
= d
->sbdma_ctxtable
[idx
];
1089 d
->sbdma_ctxtable
[idx
] = NULL
;
1095 /**********************************************************************
1098 * Fill the specified DMA channel (must be receive channel)
1106 ********************************************************************* */
1108 static void sbdma_fillring(sbmacdma_t
*d
)
1112 for (idx
= 0; idx
< SBMAC_MAX_RXDESCR
-1; idx
++) {
1113 if (sbdma_add_rcvbuffer(d
,NULL
) != 0)
1119 /**********************************************************************
1120 * SBDMA_RX_PROCESS(sc,d)
1122 * Process "completed" receive buffers on the specified DMA channel.
1123 * Note that this isn't really ideal for priority channels, since
1124 * it processes all of the packets on a given channel before
1128 * sc - softc structure
1129 * d - DMA channel context
1133 ********************************************************************* */
1135 static void sbdma_rx_process(struct sbmac_softc
*sc
,sbmacdma_t
*d
)
1145 * figure out where we are (as an index) and where
1146 * the hardware is (also as an index)
1148 * This could be done faster if (for example) the
1149 * descriptor table was page-aligned and contiguous in
1150 * both virtual and physical memory -- you could then
1151 * just compare the low-order bits of the virtual address
1152 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1155 curidx
= d
->sbdma_remptr
- d
->sbdma_dscrtable
;
1156 hwidx
= (int) (((__raw_readq(d
->sbdma_curdscr
) & M_DMA_CURDSCR_ADDR
) -
1157 d
->sbdma_dscrtable_phys
) / sizeof(sbdmadscr_t
));
1160 * If they're the same, that means we've processed all
1161 * of the descriptors up to (but not including) the one that
1162 * the hardware is working on right now.
1165 if (curidx
== hwidx
)
1169 * Otherwise, get the packet's sk_buff ptr back
1172 dsc
= &(d
->sbdma_dscrtable
[curidx
]);
1173 sb
= d
->sbdma_ctxtable
[curidx
];
1174 d
->sbdma_ctxtable
[curidx
] = NULL
;
1176 len
= (int)G_DMA_DSCRB_PKT_SIZE(dsc
->dscr_b
) - 4;
1179 * Check packet status. If good, process it.
1180 * If not, silently drop it and put it back on the
1184 if (!(dsc
->dscr_a
& M_DMA_ETHRX_BAD
)) {
1187 * Add a new buffer to replace the old one. If we fail
1188 * to allocate a buffer, we're going to drop this
1189 * packet and put it right back on the receive ring.
1192 if (sbdma_add_rcvbuffer(d
,NULL
) == -ENOBUFS
) {
1193 sc
->sbm_stats
.rx_dropped
++;
1194 sbdma_add_rcvbuffer(d
,sb
); /* re-add old buffer */
1197 * Set length into the packet
1202 * Buffer has been replaced on the
1203 * receive ring. Pass the buffer to
1206 sc
->sbm_stats
.rx_bytes
+= len
;
1207 sc
->sbm_stats
.rx_packets
++;
1208 sb
->protocol
= eth_type_trans(sb
,d
->sbdma_eth
->sbm_dev
);
1209 /* Check hw IPv4/TCP checksum if supported */
1210 if (sc
->rx_hw_checksum
== ENABLE
) {
1211 if (!((dsc
->dscr_a
) & M_DMA_ETHRX_BADIP4CS
) &&
1212 !((dsc
->dscr_a
) & M_DMA_ETHRX_BADTCPCS
)) {
1213 sb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1214 /* don't need to set sb->csum */
1216 sb
->ip_summed
= CHECKSUM_NONE
;
1224 * Packet was mangled somehow. Just drop it and
1225 * put it back on the receive ring.
1227 sc
->sbm_stats
.rx_errors
++;
1228 sbdma_add_rcvbuffer(d
,sb
);
1233 * .. and advance to the next buffer.
1236 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1243 /**********************************************************************
1244 * SBDMA_TX_PROCESS(sc,d)
1246 * Process "completed" transmit buffers on the specified DMA channel.
1247 * This is normally called within the interrupt service routine.
1248 * Note that this isn't really ideal for priority channels, since
1249 * it processes all of the packets on a given channel before
1253 * sc - softc structure
1254 * d - DMA channel context
1258 ********************************************************************* */
1260 static void sbdma_tx_process(struct sbmac_softc
*sc
,sbmacdma_t
*d
)
1266 unsigned long flags
;
1268 spin_lock_irqsave(&(sc
->sbm_lock
), flags
);
1272 * figure out where we are (as an index) and where
1273 * the hardware is (also as an index)
1275 * This could be done faster if (for example) the
1276 * descriptor table was page-aligned and contiguous in
1277 * both virtual and physical memory -- you could then
1278 * just compare the low-order bits of the virtual address
1279 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1282 curidx
= d
->sbdma_remptr
- d
->sbdma_dscrtable
;
1283 hwidx
= (int) (((__raw_readq(d
->sbdma_curdscr
) & M_DMA_CURDSCR_ADDR
) -
1284 d
->sbdma_dscrtable_phys
) / sizeof(sbdmadscr_t
));
1287 * If they're the same, that means we've processed all
1288 * of the descriptors up to (but not including) the one that
1289 * the hardware is working on right now.
1292 if (curidx
== hwidx
)
1296 * Otherwise, get the packet's sk_buff ptr back
1299 dsc
= &(d
->sbdma_dscrtable
[curidx
]);
1300 sb
= d
->sbdma_ctxtable
[curidx
];
1301 d
->sbdma_ctxtable
[curidx
] = NULL
;
1307 sc
->sbm_stats
.tx_bytes
+= sb
->len
;
1308 sc
->sbm_stats
.tx_packets
++;
1311 * for transmits, we just free buffers.
1314 dev_kfree_skb_irq(sb
);
1317 * .. and advance to the next buffer.
1320 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1325 * Decide if we should wake up the protocol or not.
1326 * Other drivers seem to do this when we reach a low
1327 * watermark on the transmit queue.
1330 netif_wake_queue(d
->sbdma_eth
->sbm_dev
);
1332 spin_unlock_irqrestore(&(sc
->sbm_lock
), flags
);
1338 /**********************************************************************
1341 * Initialize an Ethernet context structure - this is called
1342 * once per MAC on the 1250. Memory is allocated here, so don't
1343 * call it again from inside the ioctl routines that bring the
1347 * s - sbmac context structure
1351 ********************************************************************* */
1353 static int sbmac_initctx(struct sbmac_softc
*s
)
1357 * figure out the addresses of some ports
1360 s
->sbm_macenable
= s
->sbm_base
+ R_MAC_ENABLE
;
1361 s
->sbm_maccfg
= s
->sbm_base
+ R_MAC_CFG
;
1362 s
->sbm_fifocfg
= s
->sbm_base
+ R_MAC_THRSH_CFG
;
1363 s
->sbm_framecfg
= s
->sbm_base
+ R_MAC_FRAMECFG
;
1364 s
->sbm_rxfilter
= s
->sbm_base
+ R_MAC_ADFILTER_CFG
;
1365 s
->sbm_isr
= s
->sbm_base
+ R_MAC_STATUS
;
1366 s
->sbm_imr
= s
->sbm_base
+ R_MAC_INT_MASK
;
1367 s
->sbm_mdio
= s
->sbm_base
+ R_MAC_MDIO
;
1372 s
->sbm_phy_oldbmsr
= 0;
1373 s
->sbm_phy_oldanlpar
= 0;
1374 s
->sbm_phy_oldk1stsr
= 0;
1375 s
->sbm_phy_oldlinkstat
= 0;
1378 * Initialize the DMA channels. Right now, only one per MAC is used
1379 * Note: Only do this _once_, as it allocates memory from the kernel!
1382 sbdma_initctx(&(s
->sbm_txdma
),s
,0,DMA_TX
,SBMAC_MAX_TXDESCR
);
1383 sbdma_initctx(&(s
->sbm_rxdma
),s
,0,DMA_RX
,SBMAC_MAX_RXDESCR
);
1386 * initial state is OFF
1389 s
->sbm_state
= sbmac_state_off
;
1392 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1395 s
->sbm_speed
= sbmac_speed_10
;
1396 s
->sbm_duplex
= sbmac_duplex_half
;
1397 s
->sbm_fc
= sbmac_fc_disabled
;
1403 static void sbdma_uninitctx(struct sbmacdma_s
*d
)
1405 if (d
->sbdma_dscrtable
) {
1406 kfree(d
->sbdma_dscrtable
);
1407 d
->sbdma_dscrtable
= NULL
;
1410 if (d
->sbdma_ctxtable
) {
1411 kfree(d
->sbdma_ctxtable
);
1412 d
->sbdma_ctxtable
= NULL
;
1417 static void sbmac_uninitctx(struct sbmac_softc
*sc
)
1419 sbdma_uninitctx(&(sc
->sbm_txdma
));
1420 sbdma_uninitctx(&(sc
->sbm_rxdma
));
1424 /**********************************************************************
1425 * SBMAC_CHANNEL_START(s)
1427 * Start packet processing on this MAC.
1430 * s - sbmac structure
1434 ********************************************************************* */
1436 static void sbmac_channel_start(struct sbmac_softc
*s
)
1439 volatile void __iomem
*port
;
1440 uint64_t cfg
,fifo
,framecfg
;
1444 * Don't do this if running
1447 if (s
->sbm_state
== sbmac_state_on
)
1451 * Bring the controller out of reset, but leave it off.
1454 __raw_writeq(0, s
->sbm_macenable
);
1457 * Ignore all received packets
1460 __raw_writeq(0, s
->sbm_rxfilter
);
1463 * Calculate values for various control registers.
1466 cfg
= M_MAC_RETRY_EN
|
1467 M_MAC_TX_HOLD_SOP_EN
|
1468 V_MAC_TX_PAUSE_CNT_16K
|
1475 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1476 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1477 * Use a larger RD_THRSH for gigabit
1479 if (periph_rev
>= 2)
1484 fifo
= V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1485 ((s
->sbm_speed
== sbmac_speed_1000
)
1486 ? V_MAC_TX_RD_THRSH(th_value
) : V_MAC_TX_RD_THRSH(4)) |
1487 V_MAC_TX_RL_THRSH(4) |
1488 V_MAC_RX_PL_THRSH(4) |
1489 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1490 V_MAC_RX_PL_THRSH(4) |
1491 V_MAC_RX_RL_THRSH(8) |
1494 framecfg
= V_MAC_MIN_FRAMESZ_DEFAULT
|
1495 V_MAC_MAX_FRAMESZ_DEFAULT
|
1496 V_MAC_BACKOFF_SEL(1);
1499 * Clear out the hash address map
1502 port
= s
->sbm_base
+ R_MAC_HASH_BASE
;
1503 for (idx
= 0; idx
< MAC_HASH_COUNT
; idx
++) {
1504 __raw_writeq(0, port
);
1505 port
+= sizeof(uint64_t);
1509 * Clear out the exact-match table
1512 port
= s
->sbm_base
+ R_MAC_ADDR_BASE
;
1513 for (idx
= 0; idx
< MAC_ADDR_COUNT
; idx
++) {
1514 __raw_writeq(0, port
);
1515 port
+= sizeof(uint64_t);
1519 * Clear out the DMA Channel mapping table registers
1522 port
= s
->sbm_base
+ R_MAC_CHUP0_BASE
;
1523 for (idx
= 0; idx
< MAC_CHMAP_COUNT
; idx
++) {
1524 __raw_writeq(0, port
);
1525 port
+= sizeof(uint64_t);
1529 port
= s
->sbm_base
+ R_MAC_CHLO0_BASE
;
1530 for (idx
= 0; idx
< MAC_CHMAP_COUNT
; idx
++) {
1531 __raw_writeq(0, port
);
1532 port
+= sizeof(uint64_t);
1536 * Program the hardware address. It goes into the hardware-address
1537 * register as well as the first filter register.
1540 reg
= sbmac_addr2reg(s
->sbm_hwaddr
);
1542 port
= s
->sbm_base
+ R_MAC_ADDR_BASE
;
1543 __raw_writeq(reg
, port
);
1544 port
= s
->sbm_base
+ R_MAC_ETHERNET_ADDR
;
1546 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1548 * Pass1 SOCs do not receive packets addressed to the
1549 * destination address in the R_MAC_ETHERNET_ADDR register.
1550 * Set the value to zero.
1552 __raw_writeq(0, port
);
1554 __raw_writeq(reg
, port
);
1558 * Set the receive filter for no packets, and write values
1559 * to the various config registers
1562 __raw_writeq(0, s
->sbm_rxfilter
);
1563 __raw_writeq(0, s
->sbm_imr
);
1564 __raw_writeq(framecfg
, s
->sbm_framecfg
);
1565 __raw_writeq(fifo
, s
->sbm_fifocfg
);
1566 __raw_writeq(cfg
, s
->sbm_maccfg
);
1569 * Initialize DMA channels (rings should be ok now)
1572 sbdma_channel_start(&(s
->sbm_rxdma
), DMA_RX
);
1573 sbdma_channel_start(&(s
->sbm_txdma
), DMA_TX
);
1576 * Configure the speed, duplex, and flow control
1579 sbmac_set_speed(s
,s
->sbm_speed
);
1580 sbmac_set_duplex(s
,s
->sbm_duplex
,s
->sbm_fc
);
1583 * Fill the receive ring
1586 sbdma_fillring(&(s
->sbm_rxdma
));
1589 * Turn on the rest of the bits in the enable register
1592 __raw_writeq(M_MAC_RXDMA_EN0
|
1595 M_MAC_TX_ENABLE
, s
->sbm_macenable
);
1600 #ifdef CONFIG_SBMAC_COALESCE
1602 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1604 __raw_writeq(((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_TX_CH0
) |
1605 ((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_RX_CH0
), s
->sbm_imr
);
1608 * Accept any kind of interrupt on TX and RX DMA channel 0
1610 __raw_writeq((M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
) |
1611 (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
), s
->sbm_imr
);
1615 * Enable receiving unicasts and broadcasts
1618 __raw_writeq(M_MAC_UCAST_EN
| M_MAC_BCAST_EN
, s
->sbm_rxfilter
);
1621 * we're running now.
1624 s
->sbm_state
= sbmac_state_on
;
1627 * Program multicast addresses
1633 * If channel was in promiscuous mode before, turn that on
1636 if (s
->sbm_devflags
& IFF_PROMISC
) {
1637 sbmac_promiscuous_mode(s
,1);
1643 /**********************************************************************
1644 * SBMAC_CHANNEL_STOP(s)
1646 * Stop packet processing on this MAC.
1649 * s - sbmac structure
1653 ********************************************************************* */
1655 static void sbmac_channel_stop(struct sbmac_softc
*s
)
1657 /* don't do this if already stopped */
1659 if (s
->sbm_state
== sbmac_state_off
)
1662 /* don't accept any packets, disable all interrupts */
1664 __raw_writeq(0, s
->sbm_rxfilter
);
1665 __raw_writeq(0, s
->sbm_imr
);
1667 /* Turn off ticker */
1671 /* turn off receiver and transmitter */
1673 __raw_writeq(0, s
->sbm_macenable
);
1675 /* We're stopped now. */
1677 s
->sbm_state
= sbmac_state_off
;
1680 * Stop DMA channels (rings should be ok now)
1683 sbdma_channel_stop(&(s
->sbm_rxdma
));
1684 sbdma_channel_stop(&(s
->sbm_txdma
));
1686 /* Empty the receive and transmit rings */
1688 sbdma_emptyring(&(s
->sbm_rxdma
));
1689 sbdma_emptyring(&(s
->sbm_txdma
));
1693 /**********************************************************************
1694 * SBMAC_SET_CHANNEL_STATE(state)
1696 * Set the channel's state ON or OFF
1703 ********************************************************************* */
1704 static sbmac_state_t
sbmac_set_channel_state(struct sbmac_softc
*sc
,
1705 sbmac_state_t state
)
1707 sbmac_state_t oldstate
= sc
->sbm_state
;
1710 * If same as previous state, return
1713 if (state
== oldstate
) {
1718 * If new state is ON, turn channel on
1721 if (state
== sbmac_state_on
) {
1722 sbmac_channel_start(sc
);
1725 sbmac_channel_stop(sc
);
1729 * Return previous state
1736 /**********************************************************************
1737 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1739 * Turn on or off promiscuous mode
1743 * onoff - 1 to turn on, 0 to turn off
1747 ********************************************************************* */
1749 static void sbmac_promiscuous_mode(struct sbmac_softc
*sc
,int onoff
)
1753 if (sc
->sbm_state
!= sbmac_state_on
)
1757 reg
= __raw_readq(sc
->sbm_rxfilter
);
1758 reg
|= M_MAC_ALLPKT_EN
;
1759 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1762 reg
= __raw_readq(sc
->sbm_rxfilter
);
1763 reg
&= ~M_MAC_ALLPKT_EN
;
1764 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1768 /**********************************************************************
1769 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1771 * Set the iphdr offset as 15 assuming ethernet encapsulation
1778 ********************************************************************* */
1780 static void sbmac_set_iphdr_offset(struct sbmac_softc
*sc
)
1784 /* Hard code the off set to 15 for now */
1785 reg
= __raw_readq(sc
->sbm_rxfilter
);
1786 reg
&= ~M_MAC_IPHDR_OFFSET
| V_MAC_IPHDR_OFFSET(15);
1787 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1789 /* read system identification to determine revision */
1790 if (periph_rev
>= 2) {
1791 sc
->rx_hw_checksum
= ENABLE
;
1793 sc
->rx_hw_checksum
= DISABLE
;
1798 /**********************************************************************
1799 * SBMAC_ADDR2REG(ptr)
1801 * Convert six bytes into the 64-bit register value that
1802 * we typically write into the SBMAC's address/mcast registers
1805 * ptr - pointer to 6 bytes
1809 ********************************************************************* */
1811 static uint64_t sbmac_addr2reg(unsigned char *ptr
)
1817 reg
|= (uint64_t) *(--ptr
);
1819 reg
|= (uint64_t) *(--ptr
);
1821 reg
|= (uint64_t) *(--ptr
);
1823 reg
|= (uint64_t) *(--ptr
);
1825 reg
|= (uint64_t) *(--ptr
);
1827 reg
|= (uint64_t) *(--ptr
);
1833 /**********************************************************************
1834 * SBMAC_SET_SPEED(s,speed)
1836 * Configure LAN speed for the specified MAC.
1837 * Warning: must be called when MAC is off!
1840 * s - sbmac structure
1841 * speed - speed to set MAC to (see sbmac_speed_t enum)
1845 * 0 indicates invalid parameters
1846 ********************************************************************* */
1848 static int sbmac_set_speed(struct sbmac_softc
*s
,sbmac_speed_t speed
)
1854 * Save new current values
1857 s
->sbm_speed
= speed
;
1859 if (s
->sbm_state
== sbmac_state_on
)
1860 return 0; /* save for next restart */
1863 * Read current register values
1866 cfg
= __raw_readq(s
->sbm_maccfg
);
1867 framecfg
= __raw_readq(s
->sbm_framecfg
);
1870 * Mask out the stuff we want to change
1873 cfg
&= ~(M_MAC_BURST_EN
| M_MAC_SPEED_SEL
);
1874 framecfg
&= ~(M_MAC_IFG_RX
| M_MAC_IFG_TX
| M_MAC_IFG_THRSH
|
1878 * Now add in the new bits
1882 case sbmac_speed_10
:
1883 framecfg
|= V_MAC_IFG_RX_10
|
1885 K_MAC_IFG_THRSH_10
|
1887 cfg
|= V_MAC_SPEED_SEL_10MBPS
;
1890 case sbmac_speed_100
:
1891 framecfg
|= V_MAC_IFG_RX_100
|
1893 V_MAC_IFG_THRSH_100
|
1894 V_MAC_SLOT_SIZE_100
;
1895 cfg
|= V_MAC_SPEED_SEL_100MBPS
;
1898 case sbmac_speed_1000
:
1899 framecfg
|= V_MAC_IFG_RX_1000
|
1901 V_MAC_IFG_THRSH_1000
|
1902 V_MAC_SLOT_SIZE_1000
;
1903 cfg
|= V_MAC_SPEED_SEL_1000MBPS
| M_MAC_BURST_EN
;
1906 case sbmac_speed_auto
: /* XXX not implemented */
1913 * Send the bits back to the hardware
1916 __raw_writeq(framecfg
, s
->sbm_framecfg
);
1917 __raw_writeq(cfg
, s
->sbm_maccfg
);
1922 /**********************************************************************
1923 * SBMAC_SET_DUPLEX(s,duplex,fc)
1925 * Set Ethernet duplex and flow control options for this MAC
1926 * Warning: must be called when MAC is off!
1929 * s - sbmac structure
1930 * duplex - duplex setting (see sbmac_duplex_t)
1931 * fc - flow control setting (see sbmac_fc_t)
1935 * 0 if an invalid parameter combination was specified
1936 ********************************************************************* */
1938 static int sbmac_set_duplex(struct sbmac_softc
*s
,sbmac_duplex_t duplex
,sbmac_fc_t fc
)
1943 * Save new current values
1946 s
->sbm_duplex
= duplex
;
1949 if (s
->sbm_state
== sbmac_state_on
)
1950 return 0; /* save for next restart */
1953 * Read current register values
1956 cfg
= __raw_readq(s
->sbm_maccfg
);
1959 * Mask off the stuff we're about to change
1962 cfg
&= ~(M_MAC_FC_SEL
| M_MAC_FC_CMD
| M_MAC_HDX_EN
);
1966 case sbmac_duplex_half
:
1968 case sbmac_fc_disabled
:
1969 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_DISABLED
;
1972 case sbmac_fc_collision
:
1973 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_ENABLED
;
1976 case sbmac_fc_carrier
:
1977 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_ENAB_FALSECARR
;
1980 case sbmac_fc_auto
: /* XXX not implemented */
1982 case sbmac_fc_frame
: /* not valid in half duplex */
1983 default: /* invalid selection */
1988 case sbmac_duplex_full
:
1990 case sbmac_fc_disabled
:
1991 cfg
|= V_MAC_FC_CMD_DISABLED
;
1994 case sbmac_fc_frame
:
1995 cfg
|= V_MAC_FC_CMD_ENABLED
;
1998 case sbmac_fc_collision
: /* not valid in full duplex */
1999 case sbmac_fc_carrier
: /* not valid in full duplex */
2000 case sbmac_fc_auto
: /* XXX not implemented */
2006 case sbmac_duplex_auto
:
2007 /* XXX not implemented */
2012 * Send the bits back to the hardware
2015 __raw_writeq(cfg
, s
->sbm_maccfg
);
2023 /**********************************************************************
2026 * Interrupt handler for MAC interrupts
2033 ********************************************************************* */
2034 static irqreturn_t
sbmac_intr(int irq
,void *dev_instance
,struct pt_regs
*rgs
)
2036 struct net_device
*dev
= (struct net_device
*) dev_instance
;
2037 struct sbmac_softc
*sc
= netdev_priv(dev
);
2044 * Read the ISR (this clears the bits in the real
2045 * register, except for counter addr)
2048 isr
= __raw_readq(sc
->sbm_isr
) & ~M_MAC_COUNTER_ADDR
;
2056 * Transmits on channel 0
2059 if (isr
& (M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
)) {
2060 sbdma_tx_process(sc
,&(sc
->sbm_txdma
));
2064 * Receives on channel 0
2068 * It's important to test all the bits (or at least the
2069 * EOP_SEEN bit) when deciding to do the RX process
2070 * particularly when coalescing, to make sure we
2071 * take care of the following:
2073 * If you have some packets waiting (have been received
2074 * but no interrupt) and get a TX interrupt before
2075 * the RX timer or counter expires, reading the ISR
2076 * above will clear the timer and counter, and you
2077 * won't get another interrupt until a packet shows
2078 * up to start the timer again. Testing
2079 * EOP_SEEN here takes care of this case.
2080 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2084 if (isr
& (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
)) {
2085 sbdma_rx_process(sc
,&(sc
->sbm_rxdma
));
2088 return IRQ_RETVAL(handled
);
2092 /**********************************************************************
2093 * SBMAC_START_TX(skb,dev)
2095 * Start output on the specified interface. Basically, we
2096 * queue as many buffers as we can until the ring fills up, or
2097 * we run off the end of the queue, whichever comes first.
2104 ********************************************************************* */
2105 static int sbmac_start_tx(struct sk_buff
*skb
, struct net_device
*dev
)
2107 struct sbmac_softc
*sc
= netdev_priv(dev
);
2110 spin_lock_irq (&sc
->sbm_lock
);
2113 * Put the buffer on the transmit ring. If we
2114 * don't have room, stop the queue.
2117 if (sbdma_add_txbuffer(&(sc
->sbm_txdma
),skb
)) {
2118 /* XXX save skb that we could not send */
2119 netif_stop_queue(dev
);
2120 spin_unlock_irq(&sc
->sbm_lock
);
2125 dev
->trans_start
= jiffies
;
2127 spin_unlock_irq (&sc
->sbm_lock
);
2132 /**********************************************************************
2133 * SBMAC_SETMULTI(sc)
2135 * Reprogram the multicast table into the hardware, given
2136 * the list of multicasts associated with the interface
2144 ********************************************************************* */
2146 static void sbmac_setmulti(struct sbmac_softc
*sc
)
2149 volatile void __iomem
*port
;
2151 struct dev_mc_list
*mclist
;
2152 struct net_device
*dev
= sc
->sbm_dev
;
2155 * Clear out entire multicast table. We do this by nuking
2156 * the entire hash table and all the direct matches except
2157 * the first one, which is used for our station address
2160 for (idx
= 1; idx
< MAC_ADDR_COUNT
; idx
++) {
2161 port
= sc
->sbm_base
+ R_MAC_ADDR_BASE
+(idx
*sizeof(uint64_t));
2162 __raw_writeq(0, port
);
2165 for (idx
= 0; idx
< MAC_HASH_COUNT
; idx
++) {
2166 port
= sc
->sbm_base
+ R_MAC_HASH_BASE
+(idx
*sizeof(uint64_t));
2167 __raw_writeq(0, port
);
2171 * Clear the filter to say we don't want any multicasts.
2174 reg
= __raw_readq(sc
->sbm_rxfilter
);
2175 reg
&= ~(M_MAC_MCAST_INV
| M_MAC_MCAST_EN
);
2176 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2178 if (dev
->flags
& IFF_ALLMULTI
) {
2180 * Enable ALL multicasts. Do this by inverting the
2181 * multicast enable bit.
2183 reg
= __raw_readq(sc
->sbm_rxfilter
);
2184 reg
|= (M_MAC_MCAST_INV
| M_MAC_MCAST_EN
);
2185 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2191 * Progam new multicast entries. For now, only use the
2192 * perfect filter. In the future we'll need to use the
2193 * hash filter if the perfect filter overflows
2196 /* XXX only using perfect filter for now, need to use hash
2197 * XXX if the table overflows */
2199 idx
= 1; /* skip station address */
2200 mclist
= dev
->mc_list
;
2201 while (mclist
&& (idx
< MAC_ADDR_COUNT
)) {
2202 reg
= sbmac_addr2reg(mclist
->dmi_addr
);
2203 port
= sc
->sbm_base
+ R_MAC_ADDR_BASE
+(idx
* sizeof(uint64_t));
2204 __raw_writeq(reg
, port
);
2206 mclist
= mclist
->next
;
2210 * Enable the "accept multicast bits" if we programmed at least one
2215 reg
= __raw_readq(sc
->sbm_rxfilter
);
2216 reg
|= M_MAC_MCAST_EN
;
2217 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2223 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2224 /**********************************************************************
2225 * SBMAC_PARSE_XDIGIT(str)
2227 * Parse a hex digit, returning its value
2233 * hex value, or -1 if invalid
2234 ********************************************************************* */
2236 static int sbmac_parse_xdigit(char str
)
2240 if ((str
>= '0') && (str
<= '9'))
2242 else if ((str
>= 'a') && (str
<= 'f'))
2243 digit
= str
- 'a' + 10;
2244 else if ((str
>= 'A') && (str
<= 'F'))
2245 digit
= str
- 'A' + 10;
2252 /**********************************************************************
2253 * SBMAC_PARSE_HWADDR(str,hwaddr)
2255 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2260 * hwaddr - pointer to hardware address
2264 ********************************************************************* */
2266 static int sbmac_parse_hwaddr(char *str
, unsigned char *hwaddr
)
2271 while (*str
&& (idx
> 0)) {
2272 digit1
= sbmac_parse_xdigit(*str
);
2279 if ((*str
== ':') || (*str
== '-')) {
2284 digit2
= sbmac_parse_xdigit(*str
);
2290 *hwaddr
++ = (digit1
<< 4) | digit2
;
2302 static int sb1250_change_mtu(struct net_device
*_dev
, int new_mtu
)
2304 if (new_mtu
> ENET_PACKET_SIZE
)
2306 _dev
->mtu
= new_mtu
;
2307 printk(KERN_INFO
"changing the mtu to %d\n", new_mtu
);
2311 /**********************************************************************
2314 * Attach routine - init hardware and hook ourselves into linux
2317 * dev - net_device structure
2321 ********************************************************************* */
2323 static int sbmac_init(struct net_device
*dev
, int idx
)
2325 struct sbmac_softc
*sc
;
2326 unsigned char *eaddr
;
2331 sc
= netdev_priv(dev
);
2333 /* Determine controller base address */
2335 sc
->sbm_base
= IOADDR(dev
->base_addr
);
2339 eaddr
= sc
->sbm_hwaddr
;
2342 * Read the ethernet address. The firwmare left this programmed
2343 * for us in the ethernet address register for each mac.
2346 ea_reg
= __raw_readq(sc
->sbm_base
+ R_MAC_ETHERNET_ADDR
);
2347 __raw_writeq(0, sc
->sbm_base
+ R_MAC_ETHERNET_ADDR
);
2348 for (i
= 0; i
< 6; i
++) {
2349 eaddr
[i
] = (uint8_t) (ea_reg
& 0xFF);
2353 for (i
= 0; i
< 6; i
++) {
2354 dev
->dev_addr
[i
] = eaddr
[i
];
2362 sc
->sbm_buffersize
= ENET_PACKET_SIZE
+ SMP_CACHE_BYTES
* 2 + ETHER_ALIGN
;
2365 * Initialize context (get pointers to registers and stuff), then
2366 * allocate the memory for the descriptor tables.
2372 * Set up Linux device callins
2375 spin_lock_init(&(sc
->sbm_lock
));
2377 dev
->open
= sbmac_open
;
2378 dev
->hard_start_xmit
= sbmac_start_tx
;
2379 dev
->stop
= sbmac_close
;
2380 dev
->get_stats
= sbmac_get_stats
;
2381 dev
->set_multicast_list
= sbmac_set_rx_mode
;
2382 dev
->do_ioctl
= sbmac_mii_ioctl
;
2383 dev
->tx_timeout
= sbmac_tx_timeout
;
2384 dev
->watchdog_timeo
= TX_TIMEOUT
;
2386 dev
->change_mtu
= sb1250_change_mtu
;
2388 /* This is needed for PASS2 for Rx H/W checksum feature */
2389 sbmac_set_iphdr_offset(sc
);
2391 err
= register_netdev(dev
);
2395 if (sc
->rx_hw_checksum
== ENABLE
) {
2396 printk(KERN_INFO
"%s: enabling TCP rcv checksum\n",
2401 * Display Ethernet address (this is called during the config
2402 * process so we need to finish off the config message that
2403 * was being displayed)
2406 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2407 dev
->name
, dev
->base_addr
,
2408 eaddr
[0],eaddr
[1],eaddr
[2],eaddr
[3],eaddr
[4],eaddr
[5]);
2414 sbmac_uninitctx(sc
);
2420 static int sbmac_open(struct net_device
*dev
)
2422 struct sbmac_softc
*sc
= netdev_priv(dev
);
2425 printk(KERN_DEBUG
"%s: sbmac_open() irq %d.\n", dev
->name
, dev
->irq
);
2429 * map/route interrupt (clear status first, in case something
2430 * weird is pending; we haven't initialized the mac registers
2434 __raw_readq(sc
->sbm_isr
);
2435 if (request_irq(dev
->irq
, &sbmac_intr
, SA_SHIRQ
, dev
->name
, dev
))
2442 if(sbmac_mii_probe(dev
) == -1) {
2443 printk("%s: failed to probe PHY.\n", dev
->name
);
2448 * Configure default speed
2451 sbmac_mii_poll(sc
,noisy_mii
);
2454 * Turn on the channel
2457 sbmac_set_channel_state(sc
,sbmac_state_on
);
2460 * XXX Station address is in dev->dev_addr
2463 if (dev
->if_port
== 0)
2466 netif_start_queue(dev
);
2468 sbmac_set_rx_mode(dev
);
2470 /* Set the timer to check for link beat. */
2471 init_timer(&sc
->sbm_timer
);
2472 sc
->sbm_timer
.expires
= jiffies
+ 2 * HZ
/100;
2473 sc
->sbm_timer
.data
= (unsigned long)dev
;
2474 sc
->sbm_timer
.function
= &sbmac_timer
;
2475 add_timer(&sc
->sbm_timer
);
2480 static int sbmac_mii_probe(struct net_device
*dev
)
2483 struct sbmac_softc
*s
= netdev_priv(dev
);
2487 for (i
=1; i
<31; i
++) {
2488 bmsr
= sbmac_mii_read(s
, i
, MII_BMSR
);
2491 id1
= sbmac_mii_read(s
, i
, MII_PHYIDR1
);
2492 id2
= sbmac_mii_read(s
, i
, MII_PHYIDR2
);
2493 vendor
= ((u32
)id1
<< 6) | ((id2
>> 10) & 0x3f);
2494 device
= (id2
>> 4) & 0x3f;
2496 printk(KERN_INFO
"%s: found phy %d, vendor %06x part %02x\n",
2497 dev
->name
, i
, vendor
, device
);
2505 static int sbmac_mii_poll(struct sbmac_softc
*s
,int noisy
)
2507 int bmsr
,bmcr
,k1stsr
,anlpar
;
2512 /* Read the mode status and mode control registers. */
2513 bmsr
= sbmac_mii_read(s
,s
->sbm_phys
[0],MII_BMSR
);
2514 bmcr
= sbmac_mii_read(s
,s
->sbm_phys
[0],MII_BMCR
);
2516 /* get the link partner status */
2517 anlpar
= sbmac_mii_read(s
,s
->sbm_phys
[0],MII_ANLPAR
);
2519 /* if supported, read the 1000baseT register */
2520 if (bmsr
& BMSR_1000BT_XSR
) {
2521 k1stsr
= sbmac_mii_read(s
,s
->sbm_phys
[0],MII_K1STSR
);
2529 if ((bmsr
& BMSR_LINKSTAT
) == 0) {
2531 * If link status is down, clear out old info so that when
2532 * it comes back up it will force us to reconfigure speed
2534 s
->sbm_phy_oldbmsr
= 0;
2535 s
->sbm_phy_oldanlpar
= 0;
2536 s
->sbm_phy_oldk1stsr
= 0;
2540 if ((s
->sbm_phy_oldbmsr
!= bmsr
) ||
2541 (s
->sbm_phy_oldanlpar
!= anlpar
) ||
2542 (s
->sbm_phy_oldk1stsr
!= k1stsr
)) {
2544 printk(KERN_DEBUG
"%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2546 s
->sbm_phy_oldbmsr
,bmsr
,
2547 s
->sbm_phy_oldanlpar
,anlpar
,
2548 s
->sbm_phy_oldk1stsr
,k1stsr
);
2550 s
->sbm_phy_oldbmsr
= bmsr
;
2551 s
->sbm_phy_oldanlpar
= anlpar
;
2552 s
->sbm_phy_oldk1stsr
= k1stsr
;
2559 p
+= sprintf(p
,"Link speed: ");
2561 if (k1stsr
& K1STSR_LP1KFD
) {
2562 s
->sbm_speed
= sbmac_speed_1000
;
2563 s
->sbm_duplex
= sbmac_duplex_full
;
2564 s
->sbm_fc
= sbmac_fc_frame
;
2565 p
+= sprintf(p
,"1000BaseT FDX");
2567 else if (k1stsr
& K1STSR_LP1KHD
) {
2568 s
->sbm_speed
= sbmac_speed_1000
;
2569 s
->sbm_duplex
= sbmac_duplex_half
;
2570 s
->sbm_fc
= sbmac_fc_disabled
;
2571 p
+= sprintf(p
,"1000BaseT HDX");
2573 else if (anlpar
& ANLPAR_TXFD
) {
2574 s
->sbm_speed
= sbmac_speed_100
;
2575 s
->sbm_duplex
= sbmac_duplex_full
;
2576 s
->sbm_fc
= (anlpar
& ANLPAR_PAUSE
) ? sbmac_fc_frame
: sbmac_fc_disabled
;
2577 p
+= sprintf(p
,"100BaseT FDX");
2579 else if (anlpar
& ANLPAR_TXHD
) {
2580 s
->sbm_speed
= sbmac_speed_100
;
2581 s
->sbm_duplex
= sbmac_duplex_half
;
2582 s
->sbm_fc
= sbmac_fc_disabled
;
2583 p
+= sprintf(p
,"100BaseT HDX");
2585 else if (anlpar
& ANLPAR_10FD
) {
2586 s
->sbm_speed
= sbmac_speed_10
;
2587 s
->sbm_duplex
= sbmac_duplex_full
;
2588 s
->sbm_fc
= sbmac_fc_frame
;
2589 p
+= sprintf(p
,"10BaseT FDX");
2591 else if (anlpar
& ANLPAR_10HD
) {
2592 s
->sbm_speed
= sbmac_speed_10
;
2593 s
->sbm_duplex
= sbmac_duplex_half
;
2594 s
->sbm_fc
= sbmac_fc_collision
;
2595 p
+= sprintf(p
,"10BaseT HDX");
2598 p
+= sprintf(p
,"Unknown");
2602 printk(KERN_INFO
"%s: %s\n",s
->sbm_dev
->name
,buffer
);
2609 static void sbmac_timer(unsigned long data
)
2611 struct net_device
*dev
= (struct net_device
*)data
;
2612 struct sbmac_softc
*sc
= netdev_priv(dev
);
2616 spin_lock_irq (&sc
->sbm_lock
);
2618 /* make IFF_RUNNING follow the MII status bit "Link established" */
2619 mii_status
= sbmac_mii_read(sc
, sc
->sbm_phys
[0], MII_BMSR
);
2621 if ( (mii_status
& BMSR_LINKSTAT
) != (sc
->sbm_phy_oldlinkstat
) ) {
2622 sc
->sbm_phy_oldlinkstat
= mii_status
& BMSR_LINKSTAT
;
2623 if (mii_status
& BMSR_LINKSTAT
) {
2624 netif_carrier_on(dev
);
2627 netif_carrier_off(dev
);
2632 * Poll the PHY to see what speed we should be running at
2635 if (sbmac_mii_poll(sc
,noisy_mii
)) {
2636 if (sc
->sbm_state
!= sbmac_state_off
) {
2638 * something changed, restart the channel
2641 printk("%s: restarting channel because speed changed\n",
2644 sbmac_channel_stop(sc
);
2645 sbmac_channel_start(sc
);
2649 spin_unlock_irq (&sc
->sbm_lock
);
2651 sc
->sbm_timer
.expires
= jiffies
+ next_tick
;
2652 add_timer(&sc
->sbm_timer
);
2656 static void sbmac_tx_timeout (struct net_device
*dev
)
2658 struct sbmac_softc
*sc
= netdev_priv(dev
);
2660 spin_lock_irq (&sc
->sbm_lock
);
2663 dev
->trans_start
= jiffies
;
2664 sc
->sbm_stats
.tx_errors
++;
2666 spin_unlock_irq (&sc
->sbm_lock
);
2668 printk (KERN_WARNING
"%s: Transmit timed out\n",dev
->name
);
2674 static struct net_device_stats
*sbmac_get_stats(struct net_device
*dev
)
2676 struct sbmac_softc
*sc
= netdev_priv(dev
);
2677 unsigned long flags
;
2679 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2681 /* XXX update other stats here */
2683 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2685 return &sc
->sbm_stats
;
2690 static void sbmac_set_rx_mode(struct net_device
*dev
)
2692 unsigned long flags
;
2694 struct sbmac_softc
*sc
= netdev_priv(dev
);
2696 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2697 if ((dev
->flags
^ sc
->sbm_devflags
) & IFF_PROMISC
) {
2699 * Promiscuous changed.
2702 if (dev
->flags
& IFF_PROMISC
) {
2703 /* Unconditionally log net taps. */
2705 sbmac_promiscuous_mode(sc
,1);
2709 sbmac_promiscuous_mode(sc
,0);
2712 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2715 printk(KERN_NOTICE
"%s: Promiscuous mode %sabled.\n",
2716 dev
->name
,(msg_flag
==1)?"en":"dis");
2720 * Program the multicasts. Do this every time.
2727 static int sbmac_mii_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2729 struct sbmac_softc
*sc
= netdev_priv(dev
);
2730 u16
*data
= (u16
*)&rq
->ifr_ifru
;
2731 unsigned long flags
;
2734 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2738 case SIOCDEVPRIVATE
: /* Get the address of the PHY in use. */
2739 data
[0] = sc
->sbm_phys
[0] & 0x1f;
2741 case SIOCDEVPRIVATE
+1: /* Read the specified MII register. */
2742 data
[3] = sbmac_mii_read(sc
, data
[0] & 0x1f, data
[1] & 0x1f);
2744 case SIOCDEVPRIVATE
+2: /* Write the specified MII register */
2745 if (!capable(CAP_NET_ADMIN
)) {
2750 printk(KERN_DEBUG
"%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev
->name
,
2751 data
[0],data
[1],data
[2]);
2753 sbmac_mii_write(sc
, data
[0] & 0x1f, data
[1] & 0x1f, data
[2]);
2756 retval
= -EOPNOTSUPP
;
2759 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2763 static int sbmac_close(struct net_device
*dev
)
2765 struct sbmac_softc
*sc
= netdev_priv(dev
);
2766 unsigned long flags
;
2769 sbmac_set_channel_state(sc
,sbmac_state_off
);
2771 del_timer_sync(&sc
->sbm_timer
);
2773 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2775 netif_stop_queue(dev
);
2778 printk(KERN_DEBUG
"%s: Shutting down ethercard\n",dev
->name
);
2781 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2784 synchronize_irq(irq
);
2787 sbdma_emptyring(&(sc
->sbm_txdma
));
2788 sbdma_emptyring(&(sc
->sbm_rxdma
));
2795 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2797 sbmac_setup_hwaddr(int chan
,char *addr
)
2803 port
= A_MAC_CHANNEL_BASE(chan
);
2804 sbmac_parse_hwaddr(addr
,eaddr
);
2805 val
= sbmac_addr2reg(eaddr
);
2806 __raw_writeq(val
, IOADDR(port
+R_MAC_ETHERNET_ADDR
));
2807 val
= __raw_readq(IOADDR(port
+R_MAC_ETHERNET_ADDR
));
2811 static struct net_device
*dev_sbmac
[MAX_UNITS
];
2814 sbmac_init_module(void)
2817 struct net_device
*dev
;
2822 * For bringup when not using the firmware, we can pre-fill
2823 * the MAC addresses using the environment variables
2824 * specified in this file (or maybe from the config file?)
2826 #ifdef SBMAC_ETH0_HWADDR
2827 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR
);
2829 #ifdef SBMAC_ETH1_HWADDR
2830 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR
);
2832 #ifdef SBMAC_ETH2_HWADDR
2833 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR
);
2837 * Walk through the Ethernet controllers and find
2838 * those who have their MAC addresses set.
2841 case K_SYS_SOC_TYPE_BCM1250
:
2842 case K_SYS_SOC_TYPE_BCM1250_ALT
:
2845 case K_SYS_SOC_TYPE_BCM1120
:
2846 case K_SYS_SOC_TYPE_BCM1125
:
2847 case K_SYS_SOC_TYPE_BCM1125H
:
2848 case K_SYS_SOC_TYPE_BCM1250_ALT2
: /* Hybrid */
2855 if (chip_max_units
> MAX_UNITS
)
2856 chip_max_units
= MAX_UNITS
;
2858 for (idx
= 0; idx
< chip_max_units
; idx
++) {
2861 * This is the base address of the MAC.
2864 port
= A_MAC_CHANNEL_BASE(idx
);
2867 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2868 * value for us by the firmware if we're going to use this MAC.
2869 * If we find a zero, skip this MAC.
2872 sbmac_orig_hwaddr
[idx
] = __raw_readq(IOADDR(port
+R_MAC_ETHERNET_ADDR
));
2873 if (sbmac_orig_hwaddr
[idx
] == 0) {
2874 printk(KERN_DEBUG
"sbmac: not configuring MAC at "
2880 * Okay, cool. Initialize this MAC.
2883 dev
= alloc_etherdev(sizeof(struct sbmac_softc
));
2885 return -ENOMEM
; /* return ENOMEM */
2887 printk(KERN_DEBUG
"sbmac: configuring MAC at %lx\n", port
);
2889 dev
->irq
= K_INT_MAC_0
+ idx
;
2890 dev
->base_addr
= port
;
2892 if (sbmac_init(dev
, idx
)) {
2893 port
= A_MAC_CHANNEL_BASE(idx
);
2894 __raw_writeq(sbmac_orig_hwaddr
[idx
], IOADDR(port
+R_MAC_ETHERNET_ADDR
));
2898 dev_sbmac
[idx
] = dev
;
2905 sbmac_cleanup_module(void)
2907 struct net_device
*dev
;
2910 for (idx
= 0; idx
< MAX_UNITS
; idx
++) {
2911 struct sbmac_softc
*sc
;
2912 dev
= dev_sbmac
[idx
];
2916 sc
= netdev_priv(dev
);
2917 unregister_netdev(dev
);
2918 sbmac_uninitctx(sc
);
2923 module_init(sbmac_init_module
);
2924 module_exit(sbmac_cleanup_module
);