arch/arm/mach-iop33x/irq.c

   1 /*
   2  * linux/arch/arm/mach-iop33x/irq.c
   3  *
   4  * Generic IOP331 IRQ handling functionality
   5  *
   6  * Author: Dave Jiang <dave.jiang@intel.com>
   7  * Copyright (C) 2003 Intel Corp.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  *
  14  */
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18
  19 #include <asm/mach/irq.h>
  20 #include <asm/irq.h>
  21 #include <asm/hardware.h>
  22
  23 #include <asm/mach-types.h>
  24
  25 static u32 iop331_mask0 = 0;
  26 static u32 iop331_mask1 = 0;
  27
  28 static inline void intctl_write0(u32 val)
  29 {
  30     // INTCTL0
  31         iop3xx_cp6_enable();
  32         asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
  33         iop3xx_cp6_disable();
  34 }
  35
  36 static inline void intctl_write1(u32 val)
  37 {
  38     // INTCTL1
  39         iop3xx_cp6_enable();
  40     asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
  41         iop3xx_cp6_disable();
  42 }
  43
  44 static inline void intstr_write0(u32 val)
  45 {
  46     // INTSTR0
  47         iop3xx_cp6_enable();
  48         asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
  49         iop3xx_cp6_disable();
  50 }
  51
  52 static inline void intstr_write1(u32 val)
  53 {
  54     // INTSTR1
  55         iop3xx_cp6_enable();
  56         asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
  57         iop3xx_cp6_disable();
  58 }
  59
  60 static inline void intbase_write(u32 val)
  61 {
  62         iop3xx_cp6_enable();
  63         asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
  64         iop3xx_cp6_disable();
  65 }
  66
  67 static inline void intsize_write(u32 val)
  68 {
  69         iop3xx_cp6_enable();
  70         asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
  71         iop3xx_cp6_disable();
  72 }
  73
  74 static void
  75 iop331_irq_mask1 (unsigned int irq)
  76 {
  77         iop331_mask0 &= ~(1 << irq);
  78         intctl_write0(iop331_mask0);
  79 }
  80
  81 static void
  82 iop331_irq_mask2 (unsigned int irq)
  83 {
  84         iop331_mask1 &= ~(1 << (irq - 32));
  85         intctl_write1(iop331_mask1);
  86 }
  87
  88 static void
  89 iop331_irq_unmask1(unsigned int irq)
  90 {
  91         iop331_mask0 |= (1 << irq);
  92         intctl_write0(iop331_mask0);
  93 }
  94
  95 static void
  96 iop331_irq_unmask2(unsigned int irq)
  97 {
  98         iop331_mask1 |= (1 << (irq - 32));
  99         intctl_write1(iop331_mask1);
 100 }
 101
 102 struct irq_chip iop331_irqchip1 = {
 103         .name   = "IOP-1",
 104         .ack    = iop331_irq_mask1,
 105         .mask   = iop331_irq_mask1,
 106         .unmask = iop331_irq_unmask1,
 107 };
 108
 109 struct irq_chip iop331_irqchip2 = {
 110         .name   = "IOP-2",
 111         .ack    = iop331_irq_mask2,
 112         .mask   = iop331_irq_mask2,
 113         .unmask = iop331_irq_unmask2,
 114 };
 115
 116 void __init iop331_init_irq(void)
 117 {
 118         unsigned int i;
 119
 120         intctl_write0(0);               // disable all interrupts
 121         intctl_write1(0);
 122         intstr_write0(0);               // treat all as IRQ
 123         intstr_write1(0);
 124         intbase_write(0);
 125         intsize_write(1);
 126         if(machine_is_iq80331())        // all interrupts are inputs to chip
 127                 *IOP3XX_PCIIRSR = 0x0f;
 128
 129         for(i = 0; i < NR_IRQS; i++)
 130         {
 131                 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
 132                 set_irq_handler(i, do_level_IRQ);
 133                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 134         }
 135 }
 136