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[SPARC64]: Simplify TSB insert checks.
[linux-2.6/verdex.git] / arch / sparc64 / mm / init.c
blob5930e87dafbc32e2e0f76abf6299de38def0416e
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mm.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26
27 #include <asm/head.h>
28 #include <asm/system.h>
29 #include <asm/page.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/dma.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
43 #include <asm/tsb.h>
44 #include <asm/hypervisor.h>
45
46 extern void device_scan(void);
47
48 #define MAX_PHYS_ADDRESS (1UL << 42UL)
49 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50 #define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
52
53 unsigned long kern_linear_pte_xor[2] __read_mostly;
54
55 /* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
58 */
59 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
60
61 /* A special kernel TSB for 4MB and 256MB linear mappings. */
62 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
63
64 #define MAX_BANKS 32
65
66 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68 static int pavail_ents __initdata;
69 static int pavail_rescan_ents __initdata;
70
71 static int cmp_p64(const void *a, const void *b)
72 {
73 const struct linux_prom64_registers *x = a, *y = b;
74
75 if (x->phys_addr > y->phys_addr)
76 return 1;
77 if (x->phys_addr < y->phys_addr)
78 return -1;
79 return 0;
80 }
81
82 static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
84 int *num_ents)
85 {
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
88 int ents, ret, i;
89
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
94 property, MAX_BANKS);
95 prom_halt();
96 }
97
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
99 if (ret == -1) {
100 prom_printf("Couldn't get %s property from /memory.\n");
101 prom_halt();
102 }
103
104 *num_ents = ents;
105
106 /* Sanitize what we got from the firmware, by page aligning
107 * everything.
108 */
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
111
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
114
115 size &= PAGE_MASK;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
118
119 size -= new_base - base;
120 if ((long) size < 0L)
121 size = 0UL;
122 base = new_base;
123 }
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
126 }
127 sort(regs, ents, sizeof(struct linux_prom64_registers),
128 cmp_p64, NULL);
129 }
130
131 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
132
133 /* Ugly, but necessary... -DaveM */
134 unsigned long phys_base __read_mostly;
135 unsigned long kern_base __read_mostly;
136 unsigned long kern_size __read_mostly;
137 unsigned long pfn_base __read_mostly;
138
139 /* get_new_mmu_context() uses "cache + 1". */
140 DEFINE_SPINLOCK(ctx_alloc_lock);
141 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
142 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
143 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
144
145 /* References to special section boundaries */
146 extern char _start[], _end[];
147
148 /* Initial ramdisk setup */
149 extern unsigned long sparc_ramdisk_image64;
150 extern unsigned int sparc_ramdisk_image;
151 extern unsigned int sparc_ramdisk_size;
152
153 struct page *mem_map_zero __read_mostly;
154
155 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
156
157 unsigned long sparc64_kern_pri_context __read_mostly;
158 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
159 unsigned long sparc64_kern_sec_context __read_mostly;
160
161 int bigkernel = 0;
162
163 kmem_cache_t *pgtable_cache __read_mostly;
164
165 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
166 {
167 clear_page(addr);
168 }
169
170 void pgtable_cache_init(void)
171 {
172 pgtable_cache = kmem_cache_create("pgtable_cache",
173 PAGE_SIZE, PAGE_SIZE,
174 SLAB_HWCACHE_ALIGN |
175 SLAB_MUST_HWCACHE_ALIGN,
176 zero_ctor,
177 NULL);
178 if (!pgtable_cache) {
179 prom_printf("pgtable_cache_init(): Could not create!\n");
180 prom_halt();
181 }
182 }
183
184 #ifdef CONFIG_DEBUG_DCFLUSH
185 atomic_t dcpage_flushes = ATOMIC_INIT(0);
186 #ifdef CONFIG_SMP
187 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
188 #endif
189 #endif
190
191 inline void flush_dcache_page_impl(struct page *page)
192 {
193 BUG_ON(tlb_type == hypervisor);
194 #ifdef CONFIG_DEBUG_DCFLUSH
195 atomic_inc(&dcpage_flushes);
196 #endif
197
198 #ifdef DCACHE_ALIASING_POSSIBLE
199 __flush_dcache_page(page_address(page),
200 ((tlb_type == spitfire) &&
201 page_mapping(page) != NULL));
202 #else
203 if (page_mapping(page) != NULL &&
204 tlb_type == spitfire)
205 __flush_icache_page(__pa(page_address(page)));
206 #endif
207 }
208
209 #define PG_dcache_dirty PG_arch_1
210 #define PG_dcache_cpu_shift 24
211 #define PG_dcache_cpu_mask (256 - 1)
212
213 #if NR_CPUS > 256
214 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
215 #endif
216
217 #define dcache_dirty_cpu(page) \
218 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
219
220 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
221 {
222 unsigned long mask = this_cpu;
223 unsigned long non_cpu_bits;
224
225 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
226 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
227
228 __asm__ __volatile__("1:\n\t"
229 "ldx [%2], %%g7\n\t"
230 "and %%g7, %1, %%g1\n\t"
231 "or %%g1, %0, %%g1\n\t"
232 "casx [%2], %%g7, %%g1\n\t"
233 "cmp %%g7, %%g1\n\t"
234 "membar #StoreLoad | #StoreStore\n\t"
235 "bne,pn %%xcc, 1b\n\t"
236 " nop"
237 : /* no outputs */
238 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
239 : "g1", "g7");
240 }
241
242 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
243 {
244 unsigned long mask = (1UL << PG_dcache_dirty);
245
246 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
247 "1:\n\t"
248 "ldx [%2], %%g7\n\t"
249 "srlx %%g7, %4, %%g1\n\t"
250 "and %%g1, %3, %%g1\n\t"
251 "cmp %%g1, %0\n\t"
252 "bne,pn %%icc, 2f\n\t"
253 " andn %%g7, %1, %%g1\n\t"
254 "casx [%2], %%g7, %%g1\n\t"
255 "cmp %%g7, %%g1\n\t"
256 "membar #StoreLoad | #StoreStore\n\t"
257 "bne,pn %%xcc, 1b\n\t"
258 " nop\n"
259 "2:"
260 : /* no outputs */
261 : "r" (cpu), "r" (mask), "r" (&page->flags),
262 "i" (PG_dcache_cpu_mask),
263 "i" (PG_dcache_cpu_shift)
264 : "g1", "g7");
265 }
266
267 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
268 {
269 unsigned long tsb_addr = (unsigned long) ent;
270
271 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
272 tsb_addr = __pa(tsb_addr);
273
274 __tsb_insert(tsb_addr, tag, pte);
275 }
276
277 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
278 unsigned long _PAGE_SZBITS __read_mostly;
279
280 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
281 {
282 struct mm_struct *mm;
283 struct tsb *tsb;
284 unsigned long tag;
285
286 if (tlb_type != hypervisor) {
287 unsigned long pfn = pte_pfn(pte);
288 unsigned long pg_flags;
289 struct page *page;
290
291 if (pfn_valid(pfn) &&
292 (page = pfn_to_page(pfn), page_mapping(page)) &&
293 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
294 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
295 PG_dcache_cpu_mask);
296 int this_cpu = get_cpu();
297
298 /* This is just to optimize away some function calls
299 * in the SMP case.
300 */
301 if (cpu == this_cpu)
302 flush_dcache_page_impl(page);
303 else
304 smp_flush_dcache_page_impl(page, cpu);
305
306 clear_dcache_dirty_cpu(page, cpu);
307
308 put_cpu();
309 }
310 }
311
312 mm = vma->vm_mm;
313 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
314 (mm->context.tsb_nentries - 1UL)];
315 tag = (address >> 22UL);
316 tsb_insert(tsb, tag, pte_val(pte));
317 }
318
319 void flush_dcache_page(struct page *page)
320 {
321 struct address_space *mapping;
322 int this_cpu;
323
324 if (tlb_type == hypervisor)
325 return;
326
327 /* Do not bother with the expensive D-cache flush if it
328 * is merely the zero page. The 'bigcore' testcase in GDB
329 * causes this case to run millions of times.
330 */
331 if (page == ZERO_PAGE(0))
332 return;
333
334 this_cpu = get_cpu();
335
336 mapping = page_mapping(page);
337 if (mapping && !mapping_mapped(mapping)) {
338 int dirty = test_bit(PG_dcache_dirty, &page->flags);
339 if (dirty) {
340 int dirty_cpu = dcache_dirty_cpu(page);
341
342 if (dirty_cpu == this_cpu)
343 goto out;
344 smp_flush_dcache_page_impl(page, dirty_cpu);
345 }
346 set_dcache_dirty(page, this_cpu);
347 } else {
348 /* We could delay the flush for the !page_mapping
349 * case too. But that case is for exec env/arg
350 * pages and those are %99 certainly going to get
351 * faulted into the tlb (and thus flushed) anyways.
352 */
353 flush_dcache_page_impl(page);
354 }
355
356 out:
357 put_cpu();
358 }
359
360 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
361 {
362 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
363 if (tlb_type == spitfire) {
364 unsigned long kaddr;
365
366 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
367 __flush_icache_page(__get_phys(kaddr));
368 }
369 }
370
371 unsigned long page_to_pfn(struct page *page)
372 {
373 return (unsigned long) ((page - mem_map) + pfn_base);
374 }
375
376 struct page *pfn_to_page(unsigned long pfn)
377 {
378 return (mem_map + (pfn - pfn_base));
379 }
380
381 void show_mem(void)
382 {
383 printk("Mem-info:\n");
384 show_free_areas();
385 printk("Free swap: %6ldkB\n",
386 nr_swap_pages << (PAGE_SHIFT-10));
387 printk("%ld pages of RAM\n", num_physpages);
388 printk("%d free pages\n", nr_free_pages());
389 }
390
391 void mmu_info(struct seq_file *m)
392 {
393 if (tlb_type == cheetah)
394 seq_printf(m, "MMU Type\t: Cheetah\n");
395 else if (tlb_type == cheetah_plus)
396 seq_printf(m, "MMU Type\t: Cheetah+\n");
397 else if (tlb_type == spitfire)
398 seq_printf(m, "MMU Type\t: Spitfire\n");
399 else if (tlb_type == hypervisor)
400 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
401 else
402 seq_printf(m, "MMU Type\t: ???\n");
403
404 #ifdef CONFIG_DEBUG_DCFLUSH
405 seq_printf(m, "DCPageFlushes\t: %d\n",
406 atomic_read(&dcpage_flushes));
407 #ifdef CONFIG_SMP
408 seq_printf(m, "DCPageFlushesXC\t: %d\n",
409 atomic_read(&dcpage_flushes_xcall));
410 #endif /* CONFIG_SMP */
411 #endif /* CONFIG_DEBUG_DCFLUSH */
412 }
413
414 struct linux_prom_translation {
415 unsigned long virt;
416 unsigned long size;
417 unsigned long data;
418 };
419
420 /* Exported for kernel TLB miss handling in ktlb.S */
421 struct linux_prom_translation prom_trans[512] __read_mostly;
422 unsigned int prom_trans_ents __read_mostly;
423
424 /* Exported for SMP bootup purposes. */
425 unsigned long kern_locked_tte_data;
426
427 /* The obp translations are saved based on 8k pagesize, since obp can
428 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
429 * HI_OBP_ADDRESS range are handled in ktlb.S.
430 */
431 static inline int in_obp_range(unsigned long vaddr)
432 {
433 return (vaddr >= LOW_OBP_ADDRESS &&
434 vaddr < HI_OBP_ADDRESS);
435 }
436
437 static int cmp_ptrans(const void *a, const void *b)
438 {
439 const struct linux_prom_translation *x = a, *y = b;
440
441 if (x->virt > y->virt)
442 return 1;
443 if (x->virt < y->virt)
444 return -1;
445 return 0;
446 }
447
448 /* Read OBP translations property into 'prom_trans[]'. */
449 static void __init read_obp_translations(void)
450 {
451 int n, node, ents, first, last, i;
452
453 node = prom_finddevice("/virtual-memory");
454 n = prom_getproplen(node, "translations");
455 if (unlikely(n == 0 || n == -1)) {
456 prom_printf("prom_mappings: Couldn't get size.\n");
457 prom_halt();
458 }
459 if (unlikely(n > sizeof(prom_trans))) {
460 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
461 prom_halt();
462 }
463
464 if ((n = prom_getproperty(node, "translations",
465 (char *)&prom_trans[0],
466 sizeof(prom_trans))) == -1) {
467 prom_printf("prom_mappings: Couldn't get property.\n");
468 prom_halt();
469 }
470
471 n = n / sizeof(struct linux_prom_translation);
472
473 ents = n;
474
475 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
476 cmp_ptrans, NULL);
477
478 /* Now kick out all the non-OBP entries. */
479 for (i = 0; i < ents; i++) {
480 if (in_obp_range(prom_trans[i].virt))
481 break;
482 }
483 first = i;
484 for (; i < ents; i++) {
485 if (!in_obp_range(prom_trans[i].virt))
486 break;
487 }
488 last = i;
489
490 for (i = 0; i < (last - first); i++) {
491 struct linux_prom_translation *src = &prom_trans[i + first];
492 struct linux_prom_translation *dest = &prom_trans[i];
493
494 *dest = *src;
495 }
496 for (; i < ents; i++) {
497 struct linux_prom_translation *dest = &prom_trans[i];
498 dest->virt = dest->size = dest->data = 0x0UL;
499 }
500
501 prom_trans_ents = last - first;
502
503 if (tlb_type == spitfire) {
504 /* Clear diag TTE bits. */
505 for (i = 0; i < prom_trans_ents; i++)
506 prom_trans[i].data &= ~0x0003fe0000000000UL;
507 }
508 }
509
510 static void __init hypervisor_tlb_lock(unsigned long vaddr,
511 unsigned long pte,
512 unsigned long mmu)
513 {
514 register unsigned long func asm("%o5");
515 register unsigned long arg0 asm("%o0");
516 register unsigned long arg1 asm("%o1");
517 register unsigned long arg2 asm("%o2");
518 register unsigned long arg3 asm("%o3");
519
520 func = HV_FAST_MMU_MAP_PERM_ADDR;
521 arg0 = vaddr;
522 arg1 = 0;
523 arg2 = pte;
524 arg3 = mmu;
525 __asm__ __volatile__("ta 0x80"
526 : "=&r" (func), "=&r" (arg0),
527 "=&r" (arg1), "=&r" (arg2),
528 "=&r" (arg3)
529 : "0" (func), "1" (arg0), "2" (arg1),
530 "3" (arg2), "4" (arg3));
531 if (arg0 != 0) {
532 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
533 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
534 prom_halt();
535 }
536 }
537
538 static unsigned long kern_large_tte(unsigned long paddr);
539
540 static void __init remap_kernel(void)
541 {
542 unsigned long phys_page, tte_vaddr, tte_data;
543 int tlb_ent = sparc64_highest_locked_tlbent();
544
545 tte_vaddr = (unsigned long) KERNBASE;
546 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
547 tte_data = kern_large_tte(phys_page);
548
549 kern_locked_tte_data = tte_data;
550
551 /* Now lock us into the TLBs via Hypervisor or OBP. */
552 if (tlb_type == hypervisor) {
553 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
554 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
555 if (bigkernel) {
556 tte_vaddr += 0x400000;
557 tte_data += 0x400000;
558 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
559 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
560 }
561 } else {
562 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
563 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
564 if (bigkernel) {
565 tlb_ent -= 1;
566 prom_dtlb_load(tlb_ent,
567 tte_data + 0x400000,
568 tte_vaddr + 0x400000);
569 prom_itlb_load(tlb_ent,
570 tte_data + 0x400000,
571 tte_vaddr + 0x400000);
572 }
573 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
574 }
575 if (tlb_type == cheetah_plus) {
576 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
577 CTX_CHEETAH_PLUS_NUC);
578 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
579 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
580 }
581 }
582
583
584 static void __init inherit_prom_mappings(void)
585 {
586 read_obp_translations();
587
588 /* Now fixup OBP's idea about where we really are mapped. */
589 prom_printf("Remapping the kernel... ");
590 remap_kernel();
591 prom_printf("done.\n");
592 }
593
594 void prom_world(int enter)
595 {
596 if (!enter)
597 set_fs((mm_segment_t) { get_thread_current_ds() });
598
599 __asm__ __volatile__("flushw");
600 }
601
602 #ifdef DCACHE_ALIASING_POSSIBLE
603 void __flush_dcache_range(unsigned long start, unsigned long end)
604 {
605 unsigned long va;
606
607 if (tlb_type == spitfire) {
608 int n = 0;
609
610 for (va = start; va < end; va += 32) {
611 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
612 if (++n >= 512)
613 break;
614 }
615 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
616 start = __pa(start);
617 end = __pa(end);
618 for (va = start; va < end; va += 32)
619 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
620 "membar #Sync"
621 : /* no outputs */
622 : "r" (va),
623 "i" (ASI_DCACHE_INVALIDATE));
624 }
625 }
626 #endif /* DCACHE_ALIASING_POSSIBLE */
627
628 /* Caller does TLB context flushing on local CPU if necessary.
629 * The caller also ensures that CTX_VALID(mm->context) is false.
630 *
631 * We must be careful about boundary cases so that we never
632 * let the user have CTX 0 (nucleus) or we ever use a CTX
633 * version of zero (and thus NO_CONTEXT would not be caught
634 * by version mis-match tests in mmu_context.h).
635 *
636 * Always invoked with interrupts disabled.
637 */
638 void get_new_mmu_context(struct mm_struct *mm)
639 {
640 unsigned long ctx, new_ctx;
641 unsigned long orig_pgsz_bits;
642 int new_version;
643
644 spin_lock(&ctx_alloc_lock);
645 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
646 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
647 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
648 new_version = 0;
649 if (new_ctx >= (1 << CTX_NR_BITS)) {
650 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
651 if (new_ctx >= ctx) {
652 int i;
653 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
654 CTX_FIRST_VERSION;
655 if (new_ctx == 1)
656 new_ctx = CTX_FIRST_VERSION;
657
658 /* Don't call memset, for 16 entries that's just
659 * plain silly...
660 */
661 mmu_context_bmap[0] = 3;
662 mmu_context_bmap[1] = 0;
663 mmu_context_bmap[2] = 0;
664 mmu_context_bmap[3] = 0;
665 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
666 mmu_context_bmap[i + 0] = 0;
667 mmu_context_bmap[i + 1] = 0;
668 mmu_context_bmap[i + 2] = 0;
669 mmu_context_bmap[i + 3] = 0;
670 }
671 new_version = 1;
672 goto out;
673 }
674 }
675 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
676 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
677 out:
678 tlb_context_cache = new_ctx;
679 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
680 spin_unlock(&ctx_alloc_lock);
681
682 if (unlikely(new_version))
683 smp_new_mmu_context_version();
684 }
685
686 void sparc_ultra_dump_itlb(void)
687 {
688 int slot;
689
690 if (tlb_type == spitfire) {
691 printk ("Contents of itlb: ");
692 for (slot = 0; slot < 14; slot++) printk (" ");
693 printk ("%2x:%016lx,%016lx\n",
694 0,
695 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
696 for (slot = 1; slot < 64; slot+=3) {
697 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
698 slot,
699 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
700 slot+1,
701 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
702 slot+2,
703 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
704 }
705 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
706 printk ("Contents of itlb0:\n");
707 for (slot = 0; slot < 16; slot+=2) {
708 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
709 slot,
710 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
711 slot+1,
712 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
713 }
714 printk ("Contents of itlb2:\n");
715 for (slot = 0; slot < 128; slot+=2) {
716 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
717 slot,
718 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
719 slot+1,
720 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
721 }
722 }
723 }
724
725 void sparc_ultra_dump_dtlb(void)
726 {
727 int slot;
728
729 if (tlb_type == spitfire) {
730 printk ("Contents of dtlb: ");
731 for (slot = 0; slot < 14; slot++) printk (" ");
732 printk ("%2x:%016lx,%016lx\n", 0,
733 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
734 for (slot = 1; slot < 64; slot+=3) {
735 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
736 slot,
737 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
738 slot+1,
739 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
740 slot+2,
741 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
742 }
743 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
744 printk ("Contents of dtlb0:\n");
745 for (slot = 0; slot < 16; slot+=2) {
746 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
747 slot,
748 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
749 slot+1,
750 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
751 }
752 printk ("Contents of dtlb2:\n");
753 for (slot = 0; slot < 512; slot+=2) {
754 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
755 slot,
756 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
757 slot+1,
758 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
759 }
760 if (tlb_type == cheetah_plus) {
761 printk ("Contents of dtlb3:\n");
762 for (slot = 0; slot < 512; slot+=2) {
763 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
764 slot,
765 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
766 slot+1,
767 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
768 }
769 }
770 }
771 }
772
773 extern unsigned long cmdline_memory_size;
774
775 unsigned long __init bootmem_init(unsigned long *pages_avail)
776 {
777 unsigned long bootmap_size, start_pfn, end_pfn;
778 unsigned long end_of_phys_memory = 0UL;
779 unsigned long bootmap_pfn, bytes_avail, size;
780 int i;
781
782 #ifdef CONFIG_DEBUG_BOOTMEM
783 prom_printf("bootmem_init: Scan pavail, ");
784 #endif
785
786 bytes_avail = 0UL;
787 for (i = 0; i < pavail_ents; i++) {
788 end_of_phys_memory = pavail[i].phys_addr +
789 pavail[i].reg_size;
790 bytes_avail += pavail[i].reg_size;
791 if (cmdline_memory_size) {
792 if (bytes_avail > cmdline_memory_size) {
793 unsigned long slack = bytes_avail - cmdline_memory_size;
794
795 bytes_avail -= slack;
796 end_of_phys_memory -= slack;
797
798 pavail[i].reg_size -= slack;
799 if ((long)pavail[i].reg_size <= 0L) {
800 pavail[i].phys_addr = 0xdeadbeefUL;
801 pavail[i].reg_size = 0UL;
802 pavail_ents = i;
803 } else {
804 pavail[i+1].reg_size = 0Ul;
805 pavail[i+1].phys_addr = 0xdeadbeefUL;
806 pavail_ents = i + 1;
807 }
808 break;
809 }
810 }
811 }
812
813 *pages_avail = bytes_avail >> PAGE_SHIFT;
814
815 /* Start with page aligned address of last symbol in kernel
816 * image. The kernel is hard mapped below PAGE_OFFSET in a
817 * 4MB locked TLB translation.
818 */
819 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
820
821 bootmap_pfn = start_pfn;
822
823 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
824
825 #ifdef CONFIG_BLK_DEV_INITRD
826 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
827 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
828 unsigned long ramdisk_image = sparc_ramdisk_image ?
829 sparc_ramdisk_image : sparc_ramdisk_image64;
830 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
831 ramdisk_image -= KERNBASE;
832 initrd_start = ramdisk_image + phys_base;
833 initrd_end = initrd_start + sparc_ramdisk_size;
834 if (initrd_end > end_of_phys_memory) {
835 printk(KERN_CRIT "initrd extends beyond end of memory "
836 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
837 initrd_end, end_of_phys_memory);
838 initrd_start = 0;
839 }
840 if (initrd_start) {
841 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
842 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
843 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
844 }
845 }
846 #endif
847 /* Initialize the boot-time allocator. */
848 max_pfn = max_low_pfn = end_pfn;
849 min_low_pfn = pfn_base;
850
851 #ifdef CONFIG_DEBUG_BOOTMEM
852 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
853 min_low_pfn, bootmap_pfn, max_low_pfn);
854 #endif
855 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
856
857 /* Now register the available physical memory with the
858 * allocator.
859 */
860 for (i = 0; i < pavail_ents; i++) {
861 #ifdef CONFIG_DEBUG_BOOTMEM
862 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
863 i, pavail[i].phys_addr, pavail[i].reg_size);
864 #endif
865 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
866 }
867
868 #ifdef CONFIG_BLK_DEV_INITRD
869 if (initrd_start) {
870 size = initrd_end - initrd_start;
871
872 /* Resert the initrd image area. */
873 #ifdef CONFIG_DEBUG_BOOTMEM
874 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
875 initrd_start, initrd_end);
876 #endif
877 reserve_bootmem(initrd_start, size);
878 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
879
880 initrd_start += PAGE_OFFSET;
881 initrd_end += PAGE_OFFSET;
882 }
883 #endif
884 /* Reserve the kernel text/data/bss. */
885 #ifdef CONFIG_DEBUG_BOOTMEM
886 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
887 #endif
888 reserve_bootmem(kern_base, kern_size);
889 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
890
891 /* Reserve the bootmem map. We do not account for it
892 * in pages_avail because we will release that memory
893 * in free_all_bootmem.
894 */
895 size = bootmap_size;
896 #ifdef CONFIG_DEBUG_BOOTMEM
897 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
898 (bootmap_pfn << PAGE_SHIFT), size);
899 #endif
900 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
901 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
902
903 return end_pfn;
904 }
905
906 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
907 static int pall_ents __initdata;
908
909 #ifdef CONFIG_DEBUG_PAGEALLOC
910 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
911 {
912 unsigned long vstart = PAGE_OFFSET + pstart;
913 unsigned long vend = PAGE_OFFSET + pend;
914 unsigned long alloc_bytes = 0UL;
915
916 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
917 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
918 vstart, vend);
919 prom_halt();
920 }
921
922 while (vstart < vend) {
923 unsigned long this_end, paddr = __pa(vstart);
924 pgd_t *pgd = pgd_offset_k(vstart);
925 pud_t *pud;
926 pmd_t *pmd;
927 pte_t *pte;
928
929 pud = pud_offset(pgd, vstart);
930 if (pud_none(*pud)) {
931 pmd_t *new;
932
933 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
934 alloc_bytes += PAGE_SIZE;
935 pud_populate(&init_mm, pud, new);
936 }
937
938 pmd = pmd_offset(pud, vstart);
939 if (!pmd_present(*pmd)) {
940 pte_t *new;
941
942 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
943 alloc_bytes += PAGE_SIZE;
944 pmd_populate_kernel(&init_mm, pmd, new);
945 }
946
947 pte = pte_offset_kernel(pmd, vstart);
948 this_end = (vstart + PMD_SIZE) & PMD_MASK;
949 if (this_end > vend)
950 this_end = vend;
951
952 while (vstart < this_end) {
953 pte_val(*pte) = (paddr | pgprot_val(prot));
954
955 vstart += PAGE_SIZE;
956 paddr += PAGE_SIZE;
957 pte++;
958 }
959 }
960
961 return alloc_bytes;
962 }
963
964 extern unsigned int kvmap_linear_patch[1];
965 #endif /* CONFIG_DEBUG_PAGEALLOC */
966
967 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
968 {
969 const unsigned long shift_256MB = 28;
970 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
971 const unsigned long size_256MB = (1UL << shift_256MB);
972
973 while (start < end) {
974 long remains;
975
976 if (start & mask_256MB) {
977 start = (start + size_256MB) & ~mask_256MB;
978 continue;
979 }
980
981 remains = end - start;
982 while (remains >= size_256MB) {
983 unsigned long index = start >> shift_256MB;
984
985 __set_bit(index, kpte_linear_bitmap);
986
987 start += size_256MB;
988 remains -= size_256MB;
989 }
990 }
991 }
992
993 static void __init kernel_physical_mapping_init(void)
994 {
995 unsigned long i;
996 #ifdef CONFIG_DEBUG_PAGEALLOC
997 unsigned long mem_alloced = 0UL;
998 #endif
999
1000 read_obp_memory("reg", &pall[0], &pall_ents);
1001
1002 for (i = 0; i < pall_ents; i++) {
1003 unsigned long phys_start, phys_end;
1004
1005 phys_start = pall[i].phys_addr;
1006 phys_end = phys_start + pall[i].reg_size;
1007
1008 mark_kpte_bitmap(phys_start, phys_end);
1009
1010 #ifdef CONFIG_DEBUG_PAGEALLOC
1011 mem_alloced += kernel_map_range(phys_start, phys_end,
1012 PAGE_KERNEL);
1013 #endif
1014 }
1015
1016 #ifdef CONFIG_DEBUG_PAGEALLOC
1017 printk("Allocated %ld bytes for kernel page tables.\n",
1018 mem_alloced);
1019
1020 kvmap_linear_patch[0] = 0x01000000; /* nop */
1021 flushi(&kvmap_linear_patch[0]);
1022
1023 __flush_tlb_all();
1024 #endif
1025 }
1026
1027 #ifdef CONFIG_DEBUG_PAGEALLOC
1028 void kernel_map_pages(struct page *page, int numpages, int enable)
1029 {
1030 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1031 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1032
1033 kernel_map_range(phys_start, phys_end,
1034 (enable ? PAGE_KERNEL : __pgprot(0)));
1035
1036 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1037 PAGE_OFFSET + phys_end);
1038
1039 /* we should perform an IPI and flush all tlbs,
1040 * but that can deadlock->flush only current cpu.
1041 */
1042 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1043 PAGE_OFFSET + phys_end);
1044 }
1045 #endif
1046
1047 unsigned long __init find_ecache_flush_span(unsigned long size)
1048 {
1049 int i;
1050
1051 for (i = 0; i < pavail_ents; i++) {
1052 if (pavail[i].reg_size >= size)
1053 return pavail[i].phys_addr;
1054 }
1055
1056 return ~0UL;
1057 }
1058
1059 static void __init tsb_phys_patch(void)
1060 {
1061 struct tsb_ldquad_phys_patch_entry *pquad;
1062 struct tsb_phys_patch_entry *p;
1063
1064 pquad = &__tsb_ldquad_phys_patch;
1065 while (pquad < &__tsb_ldquad_phys_patch_end) {
1066 unsigned long addr = pquad->addr;
1067
1068 if (tlb_type == hypervisor)
1069 *(unsigned int *) addr = pquad->sun4v_insn;
1070 else
1071 *(unsigned int *) addr = pquad->sun4u_insn;
1072 wmb();
1073 __asm__ __volatile__("flush %0"
1074 : /* no outputs */
1075 : "r" (addr));
1076
1077 pquad++;
1078 }
1079
1080 p = &__tsb_phys_patch;
1081 while (p < &__tsb_phys_patch_end) {
1082 unsigned long addr = p->addr;
1083
1084 *(unsigned int *) addr = p->insn;
1085 wmb();
1086 __asm__ __volatile__("flush %0"
1087 : /* no outputs */
1088 : "r" (addr));
1089
1090 p++;
1091 }
1092 }
1093
1094 /* Don't mark as init, we give this to the Hypervisor. */
1095 static struct hv_tsb_descr ktsb_descr[2];
1096 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1097
1098 static void __init sun4v_ktsb_init(void)
1099 {
1100 unsigned long ktsb_pa;
1101
1102 /* First KTSB for PAGE_SIZE mappings. */
1103 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1104
1105 switch (PAGE_SIZE) {
1106 case 8 * 1024:
1107 default:
1108 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1109 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1110 break;
1111
1112 case 64 * 1024:
1113 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1114 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1115 break;
1116
1117 case 512 * 1024:
1118 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1119 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1120 break;
1121
1122 case 4 * 1024 * 1024:
1123 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1124 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1125 break;
1126 };
1127
1128 ktsb_descr[0].assoc = 1;
1129 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1130 ktsb_descr[0].ctx_idx = 0;
1131 ktsb_descr[0].tsb_base = ktsb_pa;
1132 ktsb_descr[0].resv = 0;
1133
1134 /* Second KTSB for 4MB/256MB mappings. */
1135 ktsb_pa = (kern_base +
1136 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1137
1138 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1139 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1140 HV_PGSZ_MASK_256MB);
1141 ktsb_descr[1].assoc = 1;
1142 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1143 ktsb_descr[1].ctx_idx = 0;
1144 ktsb_descr[1].tsb_base = ktsb_pa;
1145 ktsb_descr[1].resv = 0;
1146 }
1147
1148 void __cpuinit sun4v_ktsb_register(void)
1149 {
1150 register unsigned long func asm("%o5");
1151 register unsigned long arg0 asm("%o0");
1152 register unsigned long arg1 asm("%o1");
1153 unsigned long pa;
1154
1155 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1156
1157 func = HV_FAST_MMU_TSB_CTX0;
1158 arg0 = 2;
1159 arg1 = pa;
1160 __asm__ __volatile__("ta %6"
1161 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1162 : "0" (func), "1" (arg0), "2" (arg1),
1163 "i" (HV_FAST_TRAP));
1164 }
1165
1166 /* paging_init() sets up the page tables */
1167
1168 extern void cheetah_ecache_flush_init(void);
1169 extern void sun4v_patch_tlb_handlers(void);
1170
1171 static unsigned long last_valid_pfn;
1172 pgd_t swapper_pg_dir[2048];
1173
1174 static void sun4u_pgprot_init(void);
1175 static void sun4v_pgprot_init(void);
1176
1177 void __init paging_init(void)
1178 {
1179 unsigned long end_pfn, pages_avail, shift;
1180 unsigned long real_end, i;
1181
1182 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1183 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1184
1185 /* Invalidate both kernel TSBs. */
1186 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1187 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1188
1189 if (tlb_type == hypervisor)
1190 sun4v_pgprot_init();
1191 else
1192 sun4u_pgprot_init();
1193
1194 if (tlb_type == cheetah_plus ||
1195 tlb_type == hypervisor)
1196 tsb_phys_patch();
1197
1198 if (tlb_type == hypervisor) {
1199 sun4v_patch_tlb_handlers();
1200 sun4v_ktsb_init();
1201 }
1202
1203 /* Find available physical memory... */
1204 read_obp_memory("available", &pavail[0], &pavail_ents);
1205
1206 phys_base = 0xffffffffffffffffUL;
1207 for (i = 0; i < pavail_ents; i++)
1208 phys_base = min(phys_base, pavail[i].phys_addr);
1209
1210 pfn_base = phys_base >> PAGE_SHIFT;
1211
1212 set_bit(0, mmu_context_bmap);
1213
1214 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1215
1216 real_end = (unsigned long)_end;
1217 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1218 bigkernel = 1;
1219 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1220 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1221 prom_halt();
1222 }
1223
1224 /* Set kernel pgd to upper alias so physical page computations
1225 * work.
1226 */
1227 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1228
1229 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1230
1231 /* Now can init the kernel/bad page tables. */
1232 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1233 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1234
1235 inherit_prom_mappings();
1236
1237 /* Ok, we can use our TLB miss and window trap handlers safely. */
1238 setup_tba();
1239
1240 __flush_tlb_all();
1241
1242 if (tlb_type == hypervisor)
1243 sun4v_ktsb_register();
1244
1245 /* Setup bootmem... */
1246 pages_avail = 0;
1247 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1248
1249 kernel_physical_mapping_init();
1250
1251 {
1252 unsigned long zones_size[MAX_NR_ZONES];
1253 unsigned long zholes_size[MAX_NR_ZONES];
1254 unsigned long npages;
1255 int znum;
1256
1257 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1258 zones_size[znum] = zholes_size[znum] = 0;
1259
1260 npages = end_pfn - pfn_base;
1261 zones_size[ZONE_DMA] = npages;
1262 zholes_size[ZONE_DMA] = npages - pages_avail;
1263
1264 free_area_init_node(0, &contig_page_data, zones_size,
1265 phys_base >> PAGE_SHIFT, zholes_size);
1266 }
1267
1268 device_scan();
1269 }
1270
1271 static void __init taint_real_pages(void)
1272 {
1273 int i;
1274
1275 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1276
1277 /* Find changes discovered in the physmem available rescan and
1278 * reserve the lost portions in the bootmem maps.
1279 */
1280 for (i = 0; i < pavail_ents; i++) {
1281 unsigned long old_start, old_end;
1282
1283 old_start = pavail[i].phys_addr;
1284 old_end = old_start +
1285 pavail[i].reg_size;
1286 while (old_start < old_end) {
1287 int n;
1288
1289 for (n = 0; pavail_rescan_ents; n++) {
1290 unsigned long new_start, new_end;
1291
1292 new_start = pavail_rescan[n].phys_addr;
1293 new_end = new_start +
1294 pavail_rescan[n].reg_size;
1295
1296 if (new_start <= old_start &&
1297 new_end >= (old_start + PAGE_SIZE)) {
1298 set_bit(old_start >> 22,
1299 sparc64_valid_addr_bitmap);
1300 goto do_next_page;
1301 }
1302 }
1303 reserve_bootmem(old_start, PAGE_SIZE);
1304
1305 do_next_page:
1306 old_start += PAGE_SIZE;
1307 }
1308 }
1309 }
1310
1311 void __init mem_init(void)
1312 {
1313 unsigned long codepages, datapages, initpages;
1314 unsigned long addr, last;
1315 int i;
1316
1317 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1318 i += 1;
1319 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1320 if (sparc64_valid_addr_bitmap == NULL) {
1321 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1322 prom_halt();
1323 }
1324 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1325
1326 addr = PAGE_OFFSET + kern_base;
1327 last = PAGE_ALIGN(kern_size) + addr;
1328 while (addr < last) {
1329 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1330 addr += PAGE_SIZE;
1331 }
1332
1333 taint_real_pages();
1334
1335 max_mapnr = last_valid_pfn - pfn_base;
1336 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1337
1338 #ifdef CONFIG_DEBUG_BOOTMEM
1339 prom_printf("mem_init: Calling free_all_bootmem().\n");
1340 #endif
1341 totalram_pages = num_physpages = free_all_bootmem() - 1;
1342
1343 /*
1344 * Set up the zero page, mark it reserved, so that page count
1345 * is not manipulated when freeing the page from user ptes.
1346 */
1347 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1348 if (mem_map_zero == NULL) {
1349 prom_printf("paging_init: Cannot alloc zero page.\n");
1350 prom_halt();
1351 }
1352 SetPageReserved(mem_map_zero);
1353
1354 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1355 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1356 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1357 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1358 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1359 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1360
1361 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1362 nr_free_pages() << (PAGE_SHIFT-10),
1363 codepages << (PAGE_SHIFT-10),
1364 datapages << (PAGE_SHIFT-10),
1365 initpages << (PAGE_SHIFT-10),
1366 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1367
1368 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1369 cheetah_ecache_flush_init();
1370 }
1371
1372 void free_initmem(void)
1373 {
1374 unsigned long addr, initend;
1375
1376 /*
1377 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1378 */
1379 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1380 initend = (unsigned long)(__init_end) & PAGE_MASK;
1381 for (; addr < initend; addr += PAGE_SIZE) {
1382 unsigned long page;
1383 struct page *p;
1384
1385 page = (addr +
1386 ((unsigned long) __va(kern_base)) -
1387 ((unsigned long) KERNBASE));
1388 memset((void *)addr, 0xcc, PAGE_SIZE);
1389 p = virt_to_page(page);
1390
1391 ClearPageReserved(p);
1392 set_page_count(p, 1);
1393 __free_page(p);
1394 num_physpages++;
1395 totalram_pages++;
1396 }
1397 }
1398
1399 #ifdef CONFIG_BLK_DEV_INITRD
1400 void free_initrd_mem(unsigned long start, unsigned long end)
1401 {
1402 if (start < end)
1403 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1404 for (; start < end; start += PAGE_SIZE) {
1405 struct page *p = virt_to_page(start);
1406
1407 ClearPageReserved(p);
1408 set_page_count(p, 1);
1409 __free_page(p);
1410 num_physpages++;
1411 totalram_pages++;
1412 }
1413 }
1414 #endif
1415
1416 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1417 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1418 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1419 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1420 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1421 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1422
1423 pgprot_t PAGE_KERNEL __read_mostly;
1424 EXPORT_SYMBOL(PAGE_KERNEL);
1425
1426 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1427 pgprot_t PAGE_COPY __read_mostly;
1428
1429 pgprot_t PAGE_SHARED __read_mostly;
1430 EXPORT_SYMBOL(PAGE_SHARED);
1431
1432 pgprot_t PAGE_EXEC __read_mostly;
1433 unsigned long pg_iobits __read_mostly;
1434
1435 unsigned long _PAGE_IE __read_mostly;
1436
1437 unsigned long _PAGE_E __read_mostly;
1438 EXPORT_SYMBOL(_PAGE_E);
1439
1440 unsigned long _PAGE_CACHE __read_mostly;
1441 EXPORT_SYMBOL(_PAGE_CACHE);
1442
1443 static void prot_init_common(unsigned long page_none,
1444 unsigned long page_shared,
1445 unsigned long page_copy,
1446 unsigned long page_readonly,
1447 unsigned long page_exec_bit)
1448 {
1449 PAGE_COPY = __pgprot(page_copy);
1450 PAGE_SHARED = __pgprot(page_shared);
1451
1452 protection_map[0x0] = __pgprot(page_none);
1453 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1454 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1455 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1456 protection_map[0x4] = __pgprot(page_readonly);
1457 protection_map[0x5] = __pgprot(page_readonly);
1458 protection_map[0x6] = __pgprot(page_copy);
1459 protection_map[0x7] = __pgprot(page_copy);
1460 protection_map[0x8] = __pgprot(page_none);
1461 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1462 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1463 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1464 protection_map[0xc] = __pgprot(page_readonly);
1465 protection_map[0xd] = __pgprot(page_readonly);
1466 protection_map[0xe] = __pgprot(page_shared);
1467 protection_map[0xf] = __pgprot(page_shared);
1468 }
1469
1470 static void __init sun4u_pgprot_init(void)
1471 {
1472 unsigned long page_none, page_shared, page_copy, page_readonly;
1473 unsigned long page_exec_bit;
1474
1475 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1476 _PAGE_CACHE_4U | _PAGE_P_4U |
1477 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1478 _PAGE_EXEC_4U);
1479 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1480 _PAGE_CACHE_4U | _PAGE_P_4U |
1481 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1482 _PAGE_EXEC_4U | _PAGE_L_4U);
1483 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1484
1485 _PAGE_IE = _PAGE_IE_4U;
1486 _PAGE_E = _PAGE_E_4U;
1487 _PAGE_CACHE = _PAGE_CACHE_4U;
1488
1489 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1490 __ACCESS_BITS_4U | _PAGE_E_4U);
1491
1492 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1493 0xfffff80000000000;
1494 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1495 _PAGE_P_4U | _PAGE_W_4U);
1496
1497 /* XXX Should use 256MB on Panther. XXX */
1498 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1499
1500 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1501 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1502 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1503 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1504
1505
1506 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1507 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1508 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1509 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1510 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1511 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1512 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1513
1514 page_exec_bit = _PAGE_EXEC_4U;
1515
1516 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1517 page_exec_bit);
1518 }
1519
1520 static void __init sun4v_pgprot_init(void)
1521 {
1522 unsigned long page_none, page_shared, page_copy, page_readonly;
1523 unsigned long page_exec_bit;
1524
1525 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1526 _PAGE_CACHE_4V | _PAGE_P_4V |
1527 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1528 _PAGE_EXEC_4V);
1529 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1530 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1531
1532 _PAGE_IE = _PAGE_IE_4V;
1533 _PAGE_E = _PAGE_E_4V;
1534 _PAGE_CACHE = _PAGE_CACHE_4V;
1535
1536 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1537 0xfffff80000000000;
1538 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1539 _PAGE_P_4V | _PAGE_W_4V);
1540
1541 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1542 0xfffff80000000000;
1543 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1544 _PAGE_P_4V | _PAGE_W_4V);
1545
1546 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1547 __ACCESS_BITS_4V | _PAGE_E_4V);
1548
1549 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1550 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1551 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1552 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1553 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1554
1555 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1556 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1557 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1558 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1559 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1560 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1561 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1562
1563 page_exec_bit = _PAGE_EXEC_4V;
1564
1565 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1566 page_exec_bit);
1567 }
1568
1569 unsigned long pte_sz_bits(unsigned long sz)
1570 {
1571 if (tlb_type == hypervisor) {
1572 switch (sz) {
1573 case 8 * 1024:
1574 default:
1575 return _PAGE_SZ8K_4V;
1576 case 64 * 1024:
1577 return _PAGE_SZ64K_4V;
1578 case 512 * 1024:
1579 return _PAGE_SZ512K_4V;
1580 case 4 * 1024 * 1024:
1581 return _PAGE_SZ4MB_4V;
1582 };
1583 } else {
1584 switch (sz) {
1585 case 8 * 1024:
1586 default:
1587 return _PAGE_SZ8K_4U;
1588 case 64 * 1024:
1589 return _PAGE_SZ64K_4U;
1590 case 512 * 1024:
1591 return _PAGE_SZ512K_4U;
1592 case 4 * 1024 * 1024:
1593 return _PAGE_SZ4MB_4U;
1594 };
1595 }
1596 }
1597
1598 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1599 {
1600 pte_t pte;
1601
1602 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1603 pte_val(pte) |= (((unsigned long)space) << 32);
1604 pte_val(pte) |= pte_sz_bits(page_size);
1605
1606 return pte;
1607 }
1608
1609 static unsigned long kern_large_tte(unsigned long paddr)
1610 {
1611 unsigned long val;
1612
1613 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1614 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1615 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1616 if (tlb_type == hypervisor)
1617 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1618 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1619 _PAGE_EXEC_4V | _PAGE_W_4V);
1620
1621 return val | paddr;
1622 }
1623
1624 /*
1625 * Translate PROM's mapping we capture at boot time into physical address.
1626 * The second parameter is only set from prom_callback() invocations.
1627 */
1628 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1629 {
1630 unsigned long mask;
1631 int i;
1632
1633 mask = _PAGE_PADDR_4U;
1634 if (tlb_type == hypervisor)
1635 mask = _PAGE_PADDR_4V;
1636
1637 for (i = 0; i < prom_trans_ents; i++) {
1638 struct linux_prom_translation *p = &prom_trans[i];
1639
1640 if (promva >= p->virt &&
1641 promva < (p->virt + p->size)) {
1642 unsigned long base = p->data & mask;
1643
1644 if (error)
1645 *error = 0;
1646 return base + (promva & (8192 - 1));
1647 }
1648 }
1649 if (error)
1650 *error = 1;
1651 return 0UL;
1652 }
1653
1654 /* XXX We should kill off this ugly thing at so me point. XXX */
1655 unsigned long sun4u_get_pte(unsigned long addr)
1656 {
1657 pgd_t *pgdp;
1658 pud_t *pudp;
1659 pmd_t *pmdp;
1660 pte_t *ptep;
1661 unsigned long mask = _PAGE_PADDR_4U;
1662
1663 if (tlb_type == hypervisor)
1664 mask = _PAGE_PADDR_4V;
1665
1666 if (addr >= PAGE_OFFSET)
1667 return addr & mask;
1668
1669 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1670 return prom_virt_to_phys(addr, NULL);
1671
1672 pgdp = pgd_offset_k(addr);
1673 pudp = pud_offset(pgdp, addr);
1674 pmdp = pmd_offset(pudp, addr);
1675 ptep = pte_offset_kernel(pmdp, addr);
1676
1677 return pte_val(*ptep) & mask;
1678 }
1679
1680 /* If not locked, zap it. */
1681 void __flush_tlb_all(void)
1682 {
1683 unsigned long pstate;
1684 int i;
1685
1686 __asm__ __volatile__("flushw\n\t"
1687 "rdpr %%pstate, %0\n\t"
1688 "wrpr %0, %1, %%pstate"
1689 : "=r" (pstate)
1690 : "i" (PSTATE_IE));
1691 if (tlb_type == spitfire) {
1692 for (i = 0; i < 64; i++) {
1693 /* Spitfire Errata #32 workaround */
1694 /* NOTE: Always runs on spitfire, so no
1695 * cheetah+ page size encodings.
1696 */
1697 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1698 "flush %%g6"
1699 : /* No outputs */
1700 : "r" (0),
1701 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1702
1703 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1704 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1705 "membar #Sync"
1706 : /* no outputs */
1707 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1708 spitfire_put_dtlb_data(i, 0x0UL);
1709 }
1710
1711 /* Spitfire Errata #32 workaround */
1712 /* NOTE: Always runs on spitfire, so no
1713 * cheetah+ page size encodings.
1714 */
1715 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1716 "flush %%g6"
1717 : /* No outputs */
1718 : "r" (0),
1719 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1720
1721 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1722 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1723 "membar #Sync"
1724 : /* no outputs */
1725 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1726 spitfire_put_itlb_data(i, 0x0UL);
1727 }
1728 }
1729 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1730 cheetah_flush_dtlb_all();
1731 cheetah_flush_itlb_all();
1732 }
1733 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1734 : : "r" (pstate));
1735 }
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