1 /* savage_drv.h -- Private header for the savage driver
3 * Copyright 2004 Felix Kuehling
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __SAVAGE_DRV_H__
27 #define __SAVAGE_DRV_H__
29 #define DRIVER_AUTHOR "Felix Kuehling"
31 #define DRIVER_NAME "savage"
32 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
33 #define DRIVER_DATE "20050313"
35 #define DRIVER_MAJOR 2
36 #define DRIVER_MINOR 4
37 #define DRIVER_PATCHLEVEL 1
40 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy
41 * 2.0 The first real DRM
42 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by
43 * cliprects of the cmdbuf ioctl
44 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
45 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
46 * wide and thus very long lived (unlikely to ever wrap). The size
47 * in the struct was 32 bits before, but only 16 bits were used
48 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
52 typedef struct drm_savage_age
{
57 typedef struct drm_savage_buf_priv
{
58 struct drm_savage_buf_priv
*next
;
59 struct drm_savage_buf_priv
*prev
;
62 } drm_savage_buf_priv_t
;
64 typedef struct drm_savage_dma_page
{
66 unsigned int used
, flushed
;
67 } drm_savage_dma_page_t
;
68 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
69 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
70 * size of 16kbytes or 4k entries. Minimum requirement would be
71 * 10kbytes for 255 40-byte vertices in one drawing command. */
72 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
74 /* interesting bits of hardware state that are saved in dev_priv */
76 struct drm_savage_common_state
{
80 unsigned char pad
[sizeof(struct drm_savage_common_state
)];
81 uint32_t texctrl
, texaddr
;
82 uint32_t scstart
, new_scstart
;
83 uint32_t scend
, new_scend
;
86 unsigned char pad
[sizeof(struct drm_savage_common_state
)];
87 uint32_t texdescr
, texaddr0
, texaddr1
;
88 uint32_t drawctrl0
, new_drawctrl0
;
89 uint32_t drawctrl1
, new_drawctrl1
;
93 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */
107 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
109 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
110 || (chip==S3_PROSAVAGE) \
111 || (chip==S3_TWISTER) \
112 || (chip==S3_PROSAVAGEDDR))
114 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
116 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
118 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \
119 ||(chip==S3_PROSAVAGEDDR))
122 #define SAVAGE_IS_AGP 1
124 typedef struct drm_savage_private
{
125 drm_savage_sarea_t
*sarea_priv
;
127 drm_savage_buf_priv_t head
, tail
;
130 enum savage_family chipset
;
132 unsigned int cob_size
;
133 unsigned int bci_threshold_lo
, bci_threshold_hi
;
134 unsigned int dma_type
;
136 /* frame buffer layout */
138 unsigned int front_offset
, front_pitch
;
139 unsigned int back_offset
, back_pitch
;
140 unsigned int depth_bpp
;
141 unsigned int depth_offset
, depth_pitch
;
143 /* bitmap descriptors for swap and clear */
144 unsigned int front_bd
, back_bd
, depth_bd
;
147 unsigned int texture_offset
;
148 unsigned int texture_size
;
150 /* memory regions in physical memory */
151 drm_local_map_t
*sarea
;
152 drm_local_map_t
*mmio
;
154 drm_local_map_t
*aperture
;
155 drm_local_map_t
*status
;
156 drm_local_map_t
*agp_textures
;
157 drm_local_map_t
*cmd_dma
;
158 drm_local_map_t fake_dma
;
162 unsigned long base
, size
;
165 /* BCI and status-related stuff */
166 volatile uint32_t *status_ptr
, *bci_ptr
;
167 uint32_t status_used_mask
;
168 uint16_t event_counter
;
169 unsigned int event_wrap
;
171 /* Savage4 command DMA */
172 drm_savage_dma_page_t
*dma_pages
;
173 unsigned int nr_dma_pages
, first_dma_page
, current_dma_page
;
174 drm_savage_age_t last_dma_age
;
176 /* saved hw state for global/local check on S3D */
177 uint32_t hw_draw_ctrl
, hw_zbuf_ctrl
;
178 /* and for scissors (global, so don't emit if not changed) */
179 uint32_t hw_scissors_start
, hw_scissors_end
;
181 drm_savage_state_t state
;
183 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
184 unsigned int waiting
;
186 /* config/hardware-dependent function pointers */
187 int (*wait_fifo
)(struct drm_savage_private
*dev_priv
, unsigned int n
);
188 int (*wait_evnt
)(struct drm_savage_private
*dev_priv
, uint16_t e
);
189 /* Err, there is a macro wait_event in include/linux/wait.h.
190 * Avoid unwanted macro expansion. */
191 void (*emit_clip_rect
)(struct drm_savage_private
*dev_priv
,
192 drm_clip_rect_t
*pbox
);
193 void (*dma_flush
)(struct drm_savage_private
*dev_priv
);
194 } drm_savage_private_t
;
197 extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS
);
198 extern int savage_bci_buffers(DRM_IOCTL_ARGS
);
201 extern uint16_t savage_bci_emit_event(drm_savage_private_t
*dev_priv
,
203 extern void savage_freelist_put(drm_device_t
*dev
, drm_buf_t
*buf
);
204 extern void savage_dma_reset(drm_savage_private_t
*dev_priv
);
205 extern void savage_dma_wait(drm_savage_private_t
*dev_priv
, unsigned int page
);
206 extern uint32_t *savage_dma_alloc(drm_savage_private_t
*dev_priv
,
208 extern int savage_preinit(drm_device_t
*dev
, unsigned long chipset
);
209 extern int savage_postcleanup(drm_device_t
*dev
);
210 extern int savage_do_cleanup_bci(drm_device_t
*dev
);
211 extern void savage_reclaim_buffers(drm_device_t
*dev
, DRMFILE filp
);
213 /* state functions */
214 extern void savage_emit_clip_rect_s3d(drm_savage_private_t
*dev_priv
,
215 drm_clip_rect_t
*pbox
);
216 extern void savage_emit_clip_rect_s4(drm_savage_private_t
*dev_priv
,
217 drm_clip_rect_t
*pbox
);
219 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
220 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
221 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
222 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
223 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
225 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
226 * inside the MMIO region */
227 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
233 #define SAVAGE_STATUS_WORD0 0x48C00
234 #define SAVAGE_STATUS_WORD1 0x48C04
235 #define SAVAGE_ALT_STATUS_WORD0 0x48C60
237 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
238 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
240 /* Copied from savage_bci.h in the 2D driver with some renaming. */
242 /* Bitmap descriptors */
243 #define SAVAGE_BD_STRIDE_SHIFT 0
244 #define SAVAGE_BD_BPP_SHIFT 16
245 #define SAVAGE_BD_TILE_SHIFT 24
246 #define SAVAGE_BD_BW_DISABLE (1<<28)
248 #define SAVAGE_BD_TILE_LINEAR 0
249 /* savage4, MX, IX, 3D */
250 #define SAVAGE_BD_TILE_16BPP 2
251 #define SAVAGE_BD_TILE_32BPP 3
252 /* twister, prosavage, DDR, supersavage, 2000 */
253 #define SAVAGE_BD_TILE_DEST 1
254 #define SAVAGE_BD_TILE_TEXTURE 2
255 /* GBD - BCI enable */
256 /* savage4, MX, IX, 3D */
257 #define SAVAGE_GBD_BCI_ENABLE 8
258 /* twister, prosavage, DDR, supersavage, 2000 */
259 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0
261 #define SAVAGE_GBD_BIG_ENDIAN 4
262 #define SAVAGE_GBD_LITTLE_ENDIAN 0
263 #define SAVAGE_GBD_64 1
265 /* Global Bitmap Descriptor */
266 #define SAVAGE_BCI_GLB_BD_LOW 0x8168
267 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C
272 /* Savage4/Twister/ProSavage 3D registers */
273 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e
274 #define SAVAGE_TEXPALADDR_S4 0x1f
275 #define SAVAGE_TEXCTRL0_S4 0x20
276 #define SAVAGE_TEXCTRL1_S4 0x21
277 #define SAVAGE_TEXADDR0_S4 0x22
278 #define SAVAGE_TEXADDR1_S4 0x23
279 #define SAVAGE_TEXBLEND0_S4 0x24
280 #define SAVAGE_TEXBLEND1_S4 0x25
281 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
282 #define SAVAGE_TEXDESCR_S4 0x27
283 #define SAVAGE_FOGTABLE_S4 0x28
284 #define SAVAGE_FOGCTRL_S4 0x30
285 #define SAVAGE_STENCILCTRL_S4 0x31
286 #define SAVAGE_ZBUFCTRL_S4 0x32
287 #define SAVAGE_ZBUFOFF_S4 0x33
288 #define SAVAGE_DESTCTRL_S4 0x34
289 #define SAVAGE_DRAWCTRL0_S4 0x35
290 #define SAVAGE_DRAWCTRL1_S4 0x36
291 #define SAVAGE_ZWATERMARK_S4 0x37
292 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38
293 #define SAVAGE_TEXBLENDCOLOR_S4 0x39
294 /* Savage3D/MX/IX 3D registers */
295 #define SAVAGE_TEXPALADDR_S3D 0x18
296 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
297 #define SAVAGE_TEXADDR_S3D 0x1A
298 #define SAVAGE_TEXDESCR_S3D 0x1B
299 #define SAVAGE_TEXCTRL_S3D 0x1C
300 #define SAVAGE_FOGTABLE_S3D 0x20
301 #define SAVAGE_FOGCTRL_S3D 0x30
302 #define SAVAGE_DRAWCTRL_S3D 0x31
303 #define SAVAGE_ZBUFCTRL_S3D 0x32
304 #define SAVAGE_ZBUFOFF_S3D 0x33
305 #define SAVAGE_DESTCTRL_S3D 0x34
306 #define SAVAGE_SCSTART_S3D 0x35
307 #define SAVAGE_SCEND_S3D 0x36
308 #define SAVAGE_ZWATERMARK_S3D 0x37
309 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
311 #define SAVAGE_VERTBUFADDR 0x3e
312 #define SAVAGE_BITPLANEWTMASK 0xd7
313 #define SAVAGE_DMABUFADDR 0x51
315 /* texture enable bits (needed for tex addr checking) */
316 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
317 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
318 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
320 /* Global fields in Savage4/Twister/ProSavage 3D registers:
322 * All texture registers and DrawLocalCtrl are local. All other
323 * registers are global. */
325 /* Global fields in Savage3D/MX/IX 3D registers:
327 * All texture registers are local. DrawCtrl and ZBufCtrl are
328 * partially local. All other registers are global.
330 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
331 * ZBufCtrl global fields: zCmpFunc, zBufEn
333 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c
334 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027
336 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
338 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff
339 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff
344 #define BCI_CMD_NOP 0x40000000
345 #define BCI_CMD_RECT 0x48000000
346 #define BCI_CMD_RECT_XP 0x01000000
347 #define BCI_CMD_RECT_YP 0x02000000
348 #define BCI_CMD_SCANLINE 0x50000000
349 #define BCI_CMD_LINE 0x5C000000
350 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000
351 #define BCI_CMD_BYTE_TEXT 0x63000000
352 #define BCI_CMD_NT_BYTE_TEXT 0x67000000
353 #define BCI_CMD_BIT_TEXT 0x6C000000
354 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
355 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
356 #define BCI_CMD_SEND_COLOR 0x00008000
358 #define BCI_CMD_CLIP_NONE 0x00000000
359 #define BCI_CMD_CLIP_CURRENT 0x00002000
360 #define BCI_CMD_CLIP_LR 0x00004000
361 #define BCI_CMD_CLIP_NEW 0x00006000
363 #define BCI_CMD_DEST_GBD 0x00000000
364 #define BCI_CMD_DEST_PBD 0x00000800
365 #define BCI_CMD_DEST_PBD_NEW 0x00000C00
366 #define BCI_CMD_DEST_SBD 0x00001000
367 #define BCI_CMD_DEST_SBD_NEW 0x00001400
369 #define BCI_CMD_SRC_TRANSPARENT 0x00000200
370 #define BCI_CMD_SRC_SOLID 0x00000000
371 #define BCI_CMD_SRC_GBD 0x00000020
372 #define BCI_CMD_SRC_COLOR 0x00000040
373 #define BCI_CMD_SRC_MONO 0x00000060
374 #define BCI_CMD_SRC_PBD_COLOR 0x00000080
375 #define BCI_CMD_SRC_PBD_MONO 0x000000A0
376 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0
377 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0
378 #define BCI_CMD_SRC_SBD_COLOR 0x00000100
379 #define BCI_CMD_SRC_SBD_MONO 0x00000120
380 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140
381 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160
383 #define BCI_CMD_PAT_TRANSPARENT 0x00000010
384 #define BCI_CMD_PAT_NONE 0x00000000
385 #define BCI_CMD_PAT_COLOR 0x00000002
386 #define BCI_CMD_PAT_MONO 0x00000003
387 #define BCI_CMD_PAT_PBD_COLOR 0x00000004
388 #define BCI_CMD_PAT_PBD_MONO 0x00000005
389 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006
390 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007
391 #define BCI_CMD_PAT_SBD_COLOR 0x00000008
392 #define BCI_CMD_PAT_SBD_MONO 0x00000009
393 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A
394 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B
396 #define BCI_BD_BW_DISABLE 0x10000000
397 #define BCI_BD_TILE_MASK 0x03000000
398 #define BCI_BD_TILE_NONE 0x00000000
399 #define BCI_BD_TILE_16 0x02000000
400 #define BCI_BD_TILE_32 0x03000000
401 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF)
402 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
403 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF)
404 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
406 #define BCI_CMD_SET_REGISTER 0x96000000
408 #define BCI_CMD_WAIT 0xC0000000
409 #define BCI_CMD_WAIT_3D 0x00010000
410 #define BCI_CMD_WAIT_2D 0x00020000
412 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000
414 #define BCI_CMD_DRAW_PRIM 0x80000000
415 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000
416 #define BCI_CMD_DRAW_CONT 0x01000000
417 #define BCI_CMD_DRAW_TRILIST 0x00000000
418 #define BCI_CMD_DRAW_TRISTRIP 0x02000000
419 #define BCI_CMD_DRAW_TRIFAN 0x04000000
420 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff
421 #define BCI_CMD_DRAW_NO_Z 0x00000001
422 #define BCI_CMD_DRAW_NO_W 0x00000002
423 #define BCI_CMD_DRAW_NO_CD 0x00000004
424 #define BCI_CMD_DRAW_NO_CS 0x00000008
425 #define BCI_CMD_DRAW_NO_U0 0x00000010
426 #define BCI_CMD_DRAW_NO_V0 0x00000020
427 #define BCI_CMD_DRAW_NO_UV0 0x00000030
428 #define BCI_CMD_DRAW_NO_U1 0x00000040
429 #define BCI_CMD_DRAW_NO_V1 0x00000080
430 #define BCI_CMD_DRAW_NO_UV1 0x000000c0
432 #define BCI_CMD_DMA 0xa8000000
434 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF)
435 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF)
436 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF)
437 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
438 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
439 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
441 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF))
442 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF))
443 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \
444 (((maj) & 0x1FFF) | \
445 ((ym) ? 1<<13 : 0) | \
446 ((xp) ? 1<<14 : 0) | \
447 ((yp) ? 1<<15 : 0) | \
453 #define BCI_SET_REGISTERS( first, n ) \
454 BCI_WRITE(BCI_CMD_SET_REGISTER | \
455 ((uint32_t)(n) & 0xff) << 16 | \
456 ((uint32_t)(first) & 0xffff))
457 #define DMA_SET_REGISTERS( first, n ) \
458 DMA_WRITE(BCI_CMD_SET_REGISTER | \
459 ((uint32_t)(n) & 0xff) << 16 | \
460 ((uint32_t)(first) & 0xffff))
462 #define BCI_DRAW_PRIMITIVE(n, type, skip) \
463 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
465 #define DMA_DRAW_PRIMITIVE(n, type, skip) \
466 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
469 #define BCI_DRAW_INDICES_S3D(n, type, i0) \
470 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
473 #define BCI_DRAW_INDICES_S4(n, type, skip) \
474 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
475 (skip) | ((n) << 16))
478 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
483 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
484 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
487 * access to the burst command interface (BCI)
489 #define SAVAGE_BCI_DEBUG 1
491 #define BCI_LOCALS volatile uint32_t *bci_ptr;
493 #define BEGIN_BCI( n ) do { \
494 dev_priv->wait_fifo(dev_priv, (n)); \
495 bci_ptr = dev_priv->bci_ptr; \
498 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
500 #define BCI_COPY_FROM_USER(src,n) do { \
502 for (i = 0; i < n; ++i) { \
504 DRM_GET_USER_UNCHECKED(val, &((uint32_t*)(src))[i]); \
510 * command DMA support
512 #define SAVAGE_DMA_DEBUG 1
514 #define DMA_LOCALS uint32_t *dma_ptr;
516 #define BEGIN_DMA( n ) do { \
517 unsigned int cur = dev_priv->current_dma_page; \
518 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \
519 dev_priv->dma_pages[cur].used; \
521 dma_ptr = savage_dma_alloc(dev_priv, (n)); \
522 } else { /* fast path for small allocations */ \
523 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \
524 cur * SAVAGE_DMA_PAGE_SIZE + \
525 dev_priv->dma_pages[cur].used; \
526 if (dev_priv->dma_pages[cur].used == 0) \
527 savage_dma_wait(dev_priv, cur); \
528 dev_priv->dma_pages[cur].used += (n); \
532 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
534 #define DMA_COPY_FROM_USER(src,n) do { \
535 DRM_COPY_FROM_USER_UNCHECKED(dma_ptr, (src), (n)*4); \
540 #define DMA_COMMIT() do { \
541 unsigned int cur = dev_priv->current_dma_page; \
542 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \
543 cur * SAVAGE_DMA_PAGE_SIZE + \
544 dev_priv->dma_pages[cur].used; \
545 if (dma_ptr != expected) { \
546 DRM_ERROR("DMA allocation and use don't match: " \
547 "%p != %p\n", expected, dma_ptr); \
548 savage_dma_reset(dev_priv); \
552 #define DMA_COMMIT() do {/* nothing */} while(0)
555 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
557 /* Buffer aging via event tag
560 #define UPDATE_EVENT_COUNTER( ) do { \
561 if (dev_priv->status_ptr) { \
563 /* coordinate with Xserver */ \
564 count = dev_priv->status_ptr[1023]; \
565 if (count < dev_priv->event_counter) \
566 dev_priv->event_wrap++; \
567 dev_priv->event_counter = count; \
571 #define SET_AGE( age, e, w ) do { \
576 #define TEST_AGE( age, e, w ) \
577 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
579 #endif /* __SAVAGE_DRV_H__ */