2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
100 * We suspect that on some hardware no TX done interrupts are generated.
101 * This means recovery from netif_stop_queue only happens if the hw timer
102 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
103 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
104 * If your hardware reliably generates tx done interrupts, then you can remove
105 * DEV_NEED_TIMERIRQ from the driver_data flags.
106 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
107 * superfluous timer interrupts from the nic.
109 #define FORCEDETH_VERSION "0.41"
110 #define DRV_NAME "forcedeth"
112 #include <linux/module.h>
113 #include <linux/types.h>
114 #include <linux/pci.h>
115 #include <linux/interrupt.h>
116 #include <linux/netdevice.h>
117 #include <linux/etherdevice.h>
118 #include <linux/delay.h>
119 #include <linux/spinlock.h>
120 #include <linux/ethtool.h>
121 #include <linux/timer.h>
122 #include <linux/skbuff.h>
123 #include <linux/mii.h>
124 #include <linux/random.h>
125 #include <linux/init.h>
126 #include <linux/if_vlan.h>
130 #include <asm/uaccess.h>
131 #include <asm/system.h>
134 #define dprintk printk
136 #define dprintk(x...) do { } while (0)
144 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
145 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
146 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
147 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
150 NvRegIrqStatus
= 0x000,
151 #define NVREG_IRQSTAT_MIIEVENT 0x040
152 #define NVREG_IRQSTAT_MASK 0x1ff
153 NvRegIrqMask
= 0x004,
154 #define NVREG_IRQ_RX_ERROR 0x0001
155 #define NVREG_IRQ_RX 0x0002
156 #define NVREG_IRQ_RX_NOBUF 0x0004
157 #define NVREG_IRQ_TX_ERR 0x0008
158 #define NVREG_IRQ_TX_OK 0x0010
159 #define NVREG_IRQ_TIMER 0x0020
160 #define NVREG_IRQ_LINK 0x0040
161 #define NVREG_IRQ_TX_ERROR 0x0080
162 #define NVREG_IRQ_TX1 0x0100
163 #define NVREG_IRQMASK_WANTED 0x00df
165 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
166 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
169 NvRegUnknownSetupReg6
= 0x008,
170 #define NVREG_UNKSETUP6_VAL 3
173 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
174 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
176 NvRegPollingInterval
= 0x00c,
177 #define NVREG_POLL_DEFAULT 970
179 #define NVREG_MISC1_HD 0x02
180 #define NVREG_MISC1_FORCE 0x3b0f3c
182 NvRegTransmitterControl
= 0x084,
183 #define NVREG_XMITCTL_START 0x01
184 NvRegTransmitterStatus
= 0x088,
185 #define NVREG_XMITSTAT_BUSY 0x01
187 NvRegPacketFilterFlags
= 0x8c,
188 #define NVREG_PFF_ALWAYS 0x7F0008
189 #define NVREG_PFF_PROMISC 0x80
190 #define NVREG_PFF_MYADDR 0x20
192 NvRegOffloadConfig
= 0x90,
193 #define NVREG_OFFLOAD_HOMEPHY 0x601
194 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
195 NvRegReceiverControl
= 0x094,
196 #define NVREG_RCVCTL_START 0x01
197 NvRegReceiverStatus
= 0x98,
198 #define NVREG_RCVSTAT_BUSY 0x01
200 NvRegRandomSeed
= 0x9c,
201 #define NVREG_RNDSEED_MASK 0x00ff
202 #define NVREG_RNDSEED_FORCE 0x7f00
203 #define NVREG_RNDSEED_FORCE2 0x2d00
204 #define NVREG_RNDSEED_FORCE3 0x7400
206 NvRegUnknownSetupReg1
= 0xA0,
207 #define NVREG_UNKSETUP1_VAL 0x16070f
208 NvRegUnknownSetupReg2
= 0xA4,
209 #define NVREG_UNKSETUP2_VAL 0x16
210 NvRegMacAddrA
= 0xA8,
211 NvRegMacAddrB
= 0xAC,
212 NvRegMulticastAddrA
= 0xB0,
213 #define NVREG_MCASTADDRA_FORCE 0x01
214 NvRegMulticastAddrB
= 0xB4,
215 NvRegMulticastMaskA
= 0xB8,
216 NvRegMulticastMaskB
= 0xBC,
218 NvRegPhyInterface
= 0xC0,
219 #define PHY_RGMII 0x10000000
221 NvRegTxRingPhysAddr
= 0x100,
222 NvRegRxRingPhysAddr
= 0x104,
223 NvRegRingSizes
= 0x108,
224 #define NVREG_RINGSZ_TXSHIFT 0
225 #define NVREG_RINGSZ_RXSHIFT 16
226 NvRegUnknownTransmitterReg
= 0x10c,
227 NvRegLinkSpeed
= 0x110,
228 #define NVREG_LINKSPEED_FORCE 0x10000
229 #define NVREG_LINKSPEED_10 1000
230 #define NVREG_LINKSPEED_100 100
231 #define NVREG_LINKSPEED_1000 50
232 #define NVREG_LINKSPEED_MASK (0xFFF)
233 NvRegUnknownSetupReg5
= 0x130,
234 #define NVREG_UNKSETUP5_BIT31 (1<<31)
235 NvRegUnknownSetupReg3
= 0x13c,
236 #define NVREG_UNKSETUP3_VAL1 0x200010
237 NvRegTxRxControl
= 0x144,
238 #define NVREG_TXRXCTL_KICK 0x0001
239 #define NVREG_TXRXCTL_BIT1 0x0002
240 #define NVREG_TXRXCTL_BIT2 0x0004
241 #define NVREG_TXRXCTL_IDLE 0x0008
242 #define NVREG_TXRXCTL_RESET 0x0010
243 #define NVREG_TXRXCTL_RXCHECK 0x0400
244 NvRegMIIStatus
= 0x180,
245 #define NVREG_MIISTAT_ERROR 0x0001
246 #define NVREG_MIISTAT_LINKCHANGE 0x0008
247 #define NVREG_MIISTAT_MASK 0x000f
248 #define NVREG_MIISTAT_MASK2 0x000f
249 NvRegUnknownSetupReg4
= 0x184,
250 #define NVREG_UNKSETUP4_VAL 8
252 NvRegAdapterControl
= 0x188,
253 #define NVREG_ADAPTCTL_START 0x02
254 #define NVREG_ADAPTCTL_LINKUP 0x04
255 #define NVREG_ADAPTCTL_PHYVALID 0x40000
256 #define NVREG_ADAPTCTL_RUNNING 0x100000
257 #define NVREG_ADAPTCTL_PHYSHIFT 24
258 NvRegMIISpeed
= 0x18c,
259 #define NVREG_MIISPEED_BIT8 (1<<8)
260 #define NVREG_MIIDELAY 5
261 NvRegMIIControl
= 0x190,
262 #define NVREG_MIICTL_INUSE 0x08000
263 #define NVREG_MIICTL_WRITE 0x00400
264 #define NVREG_MIICTL_ADDRSHIFT 5
265 NvRegMIIData
= 0x194,
266 NvRegWakeUpFlags
= 0x200,
267 #define NVREG_WAKEUPFLAGS_VAL 0x7770
268 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
269 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
270 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
271 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
272 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
273 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
274 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
275 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
276 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
277 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
279 NvRegPatternCRC
= 0x204,
280 NvRegPatternMask
= 0x208,
281 NvRegPowerCap
= 0x268,
282 #define NVREG_POWERCAP_D3SUPP (1<<30)
283 #define NVREG_POWERCAP_D2SUPP (1<<26)
284 #define NVREG_POWERCAP_D1SUPP (1<<25)
285 NvRegPowerState
= 0x26c,
286 #define NVREG_POWERSTATE_POWEREDUP 0x8000
287 #define NVREG_POWERSTATE_VALID 0x0100
288 #define NVREG_POWERSTATE_MASK 0x0003
289 #define NVREG_POWERSTATE_D0 0x0000
290 #define NVREG_POWERSTATE_D1 0x0001
291 #define NVREG_POWERSTATE_D2 0x0002
292 #define NVREG_POWERSTATE_D3 0x0003
295 /* Big endian: should work, but is untested */
301 struct ring_desc_ex
{
302 u32 PacketBufferHigh
;
308 typedef union _ring_type
{
309 struct ring_desc
* orig
;
310 struct ring_desc_ex
* ex
;
313 #define FLAG_MASK_V1 0xffff0000
314 #define FLAG_MASK_V2 0xffffc000
315 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
316 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
318 #define NV_TX_LASTPACKET (1<<16)
319 #define NV_TX_RETRYERROR (1<<19)
320 #define NV_TX_FORCED_INTERRUPT (1<<24)
321 #define NV_TX_DEFERRED (1<<26)
322 #define NV_TX_CARRIERLOST (1<<27)
323 #define NV_TX_LATECOLLISION (1<<28)
324 #define NV_TX_UNDERFLOW (1<<29)
325 #define NV_TX_ERROR (1<<30)
326 #define NV_TX_VALID (1<<31)
328 #define NV_TX2_LASTPACKET (1<<29)
329 #define NV_TX2_RETRYERROR (1<<18)
330 #define NV_TX2_FORCED_INTERRUPT (1<<30)
331 #define NV_TX2_DEFERRED (1<<25)
332 #define NV_TX2_CARRIERLOST (1<<26)
333 #define NV_TX2_LATECOLLISION (1<<27)
334 #define NV_TX2_UNDERFLOW (1<<28)
335 /* error and valid are the same for both */
336 #define NV_TX2_ERROR (1<<30)
337 #define NV_TX2_VALID (1<<31)
339 #define NV_RX_DESCRIPTORVALID (1<<16)
340 #define NV_RX_MISSEDFRAME (1<<17)
341 #define NV_RX_SUBSTRACT1 (1<<18)
342 #define NV_RX_ERROR1 (1<<23)
343 #define NV_RX_ERROR2 (1<<24)
344 #define NV_RX_ERROR3 (1<<25)
345 #define NV_RX_ERROR4 (1<<26)
346 #define NV_RX_CRCERR (1<<27)
347 #define NV_RX_OVERFLOW (1<<28)
348 #define NV_RX_FRAMINGERR (1<<29)
349 #define NV_RX_ERROR (1<<30)
350 #define NV_RX_AVAIL (1<<31)
352 #define NV_RX2_CHECKSUMMASK (0x1C000000)
353 #define NV_RX2_CHECKSUMOK1 (0x10000000)
354 #define NV_RX2_CHECKSUMOK2 (0x14000000)
355 #define NV_RX2_CHECKSUMOK3 (0x18000000)
356 #define NV_RX2_DESCRIPTORVALID (1<<29)
357 #define NV_RX2_SUBSTRACT1 (1<<25)
358 #define NV_RX2_ERROR1 (1<<18)
359 #define NV_RX2_ERROR2 (1<<19)
360 #define NV_RX2_ERROR3 (1<<20)
361 #define NV_RX2_ERROR4 (1<<21)
362 #define NV_RX2_CRCERR (1<<22)
363 #define NV_RX2_OVERFLOW (1<<23)
364 #define NV_RX2_FRAMINGERR (1<<24)
365 /* error and avail are the same for both */
366 #define NV_RX2_ERROR (1<<30)
367 #define NV_RX2_AVAIL (1<<31)
369 /* Miscelaneous hardware related defines: */
370 #define NV_PCI_REGSZ 0x270
372 /* various timeout delays: all in usec */
373 #define NV_TXRX_RESET_DELAY 4
374 #define NV_TXSTOP_DELAY1 10
375 #define NV_TXSTOP_DELAY1MAX 500000
376 #define NV_TXSTOP_DELAY2 100
377 #define NV_RXSTOP_DELAY1 10
378 #define NV_RXSTOP_DELAY1MAX 500000
379 #define NV_RXSTOP_DELAY2 100
380 #define NV_SETUP5_DELAY 5
381 #define NV_SETUP5_DELAYMAX 50000
382 #define NV_POWERUP_DELAY 5
383 #define NV_POWERUP_DELAYMAX 5000
384 #define NV_MIIBUSY_DELAY 50
385 #define NV_MIIPHY_DELAY 10
386 #define NV_MIIPHY_DELAYMAX 10000
388 #define NV_WAKEUPPATTERNS 5
389 #define NV_WAKEUPMASKENTRIES 4
391 /* General driver defaults */
392 #define NV_WATCHDOG_TIMEO (5*HZ)
397 * If your nic mysteriously hangs then try to reduce the limits
398 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
399 * last valid ring entry. But this would be impossible to
400 * implement - probably a disassembly error.
402 #define TX_LIMIT_STOP 63
403 #define TX_LIMIT_START 62
405 /* rx/tx mac addr + type + vlan + align + slack*/
406 #define NV_RX_HEADERS (64)
407 /* even more slack. */
408 #define NV_RX_ALLOC_PAD (64)
410 /* maximum mtu size */
411 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
412 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
414 #define OOM_REFILL (1+HZ/20)
415 #define POLL_WAIT (1+HZ/100)
416 #define LINK_TIMEOUT (3*HZ)
420 * This field has two purposes:
421 * - Newer nics uses a different ring layout. The layout is selected by
422 * comparing np->desc_ver with DESC_VER_xy.
423 * - It contains bits that are forced on when writing to NvRegTxRxControl.
425 #define DESC_VER_1 0x0
426 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
427 #define DESC_VER_3 (0x02200|NVREG_TXRXCTL_RXCHECK)
430 #define PHY_OUI_MARVELL 0x5043
431 #define PHY_OUI_CICADA 0x03f1
432 #define PHYID1_OUI_MASK 0x03ff
433 #define PHYID1_OUI_SHFT 6
434 #define PHYID2_OUI_MASK 0xfc00
435 #define PHYID2_OUI_SHFT 10
436 #define PHY_INIT1 0x0f000
437 #define PHY_INIT2 0x0e00
438 #define PHY_INIT3 0x01000
439 #define PHY_INIT4 0x0200
440 #define PHY_INIT5 0x0004
441 #define PHY_INIT6 0x02000
442 #define PHY_GIGABIT 0x0100
444 #define PHY_TIMEOUT 0x1
445 #define PHY_ERROR 0x2
449 #define PHY_HALF 0x100
451 /* FIXME: MII defines that should be added to <linux/mii.h> */
452 #define MII_1000BT_CR 0x09
453 #define MII_1000BT_SR 0x0a
454 #define ADVERTISE_1000FULL 0x0200
455 #define ADVERTISE_1000HALF 0x0100
456 #define LPA_1000FULL 0x0800
457 #define LPA_1000HALF 0x0400
462 * All hardware access under dev->priv->lock, except the performance
464 * - rx is (pseudo-) lockless: it relies on the single-threading provided
465 * by the arch code for interrupts.
466 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
467 * needs dev->priv->lock :-(
468 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
471 /* in dev: base, irq */
476 * Locking: spin_lock(&np->lock); */
477 struct net_device_stats stats
;
485 unsigned int phy_oui
;
488 /* General data: RO fields */
489 dma_addr_t ring_addr
;
490 struct pci_dev
*pci_dev
;
497 /* rx specific fields.
498 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
501 unsigned int cur_rx
, refill_rx
;
502 struct sk_buff
*rx_skbuff
[RX_RING
];
503 dma_addr_t rx_dma
[RX_RING
];
504 unsigned int rx_buf_sz
;
505 unsigned int pkt_limit
;
506 struct timer_list oom_kick
;
507 struct timer_list nic_poll
;
509 /* media detection workaround.
510 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
513 unsigned long link_timeout
;
515 * tx specific fields.
518 unsigned int next_tx
, nic_tx
;
519 struct sk_buff
*tx_skbuff
[TX_RING
];
520 dma_addr_t tx_dma
[TX_RING
];
525 * Maximum number of loops until we assume that a bit in the irq mask
526 * is stuck. Overridable with module param.
528 static int max_interrupt_work
= 5;
530 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
532 return netdev_priv(dev
);
535 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
537 return get_nvpriv(dev
)->base
;
540 static inline void pci_push(u8 __iomem
*base
)
542 /* force out pending posted writes */
546 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
548 return le32_to_cpu(prd
->FlagLen
)
549 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
552 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
554 return le32_to_cpu(prd
->FlagLen
) & LEN_MASK_V2
;
557 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
558 int delay
, int delaymax
, const char *msg
)
560 u8 __iomem
*base
= get_hwbase(dev
);
571 } while ((readl(base
+ offset
) & mask
) != target
);
575 #define MII_READ (-1)
576 /* mii_rw: read/write a register on the PHY.
578 * Caller must guarantee serialization
580 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
582 u8 __iomem
*base
= get_hwbase(dev
);
586 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
588 reg
= readl(base
+ NvRegMIIControl
);
589 if (reg
& NVREG_MIICTL_INUSE
) {
590 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
591 udelay(NV_MIIBUSY_DELAY
);
594 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
595 if (value
!= MII_READ
) {
596 writel(value
, base
+ NvRegMIIData
);
597 reg
|= NVREG_MIICTL_WRITE
;
599 writel(reg
, base
+ NvRegMIIControl
);
601 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
602 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
603 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
604 dev
->name
, miireg
, addr
);
606 } else if (value
!= MII_READ
) {
607 /* it was a write operation - fewer failures are detectable */
608 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
609 dev
->name
, value
, miireg
, addr
);
611 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
612 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
613 dev
->name
, miireg
, addr
);
616 retval
= readl(base
+ NvRegMIIData
);
617 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
618 dev
->name
, miireg
, addr
, retval
);
624 static int phy_reset(struct net_device
*dev
)
626 struct fe_priv
*np
= get_nvpriv(dev
);
628 unsigned int tries
= 0;
630 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
631 miicontrol
|= BMCR_RESET
;
632 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
639 /* must wait till reset is deasserted */
640 while (miicontrol
& BMCR_RESET
) {
642 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
643 /* FIXME: 100 tries seem excessive */
650 static int phy_init(struct net_device
*dev
)
652 struct fe_priv
*np
= get_nvpriv(dev
);
653 u8 __iomem
*base
= get_hwbase(dev
);
654 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
656 /* set advertise register */
657 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
658 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|0x800|0x400);
659 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
660 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
664 /* get phy interface type */
665 phyinterface
= readl(base
+ NvRegPhyInterface
);
667 /* see if gigabit phy */
668 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
669 if (mii_status
& PHY_GIGABIT
) {
670 np
->gigabit
= PHY_GIGABIT
;
671 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
672 mii_control_1000
&= ~ADVERTISE_1000HALF
;
673 if (phyinterface
& PHY_RGMII
)
674 mii_control_1000
|= ADVERTISE_1000FULL
;
676 mii_control_1000
&= ~ADVERTISE_1000FULL
;
678 if (mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, mii_control_1000
)) {
679 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
687 if (phy_reset(dev
)) {
688 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
692 /* phy vendor specific configuration */
693 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
694 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
695 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
696 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
697 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
698 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
701 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
702 phy_reserved
|= PHY_INIT5
;
703 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
704 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
708 if (np
->phy_oui
== PHY_OUI_CICADA
) {
709 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
710 phy_reserved
|= PHY_INIT6
;
711 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
712 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
717 /* restart auto negotiation */
718 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
719 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
720 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
727 static void nv_start_rx(struct net_device
*dev
)
729 struct fe_priv
*np
= get_nvpriv(dev
);
730 u8 __iomem
*base
= get_hwbase(dev
);
732 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
733 /* Already running? Stop it. */
734 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
735 writel(0, base
+ NvRegReceiverControl
);
738 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
740 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
741 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
742 dev
->name
, np
->duplex
, np
->linkspeed
);
746 static void nv_stop_rx(struct net_device
*dev
)
748 u8 __iomem
*base
= get_hwbase(dev
);
750 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
751 writel(0, base
+ NvRegReceiverControl
);
752 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
753 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
754 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
756 udelay(NV_RXSTOP_DELAY2
);
757 writel(0, base
+ NvRegLinkSpeed
);
760 static void nv_start_tx(struct net_device
*dev
)
762 u8 __iomem
*base
= get_hwbase(dev
);
764 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
765 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
769 static void nv_stop_tx(struct net_device
*dev
)
771 u8 __iomem
*base
= get_hwbase(dev
);
773 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
774 writel(0, base
+ NvRegTransmitterControl
);
775 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
776 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
777 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
779 udelay(NV_TXSTOP_DELAY2
);
780 writel(0, base
+ NvRegUnknownTransmitterReg
);
783 static void nv_txrx_reset(struct net_device
*dev
)
785 struct fe_priv
*np
= get_nvpriv(dev
);
786 u8 __iomem
*base
= get_hwbase(dev
);
788 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
789 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->desc_ver
, base
+ NvRegTxRxControl
);
791 udelay(NV_TXRX_RESET_DELAY
);
792 writel(NVREG_TXRXCTL_BIT2
| np
->desc_ver
, base
+ NvRegTxRxControl
);
797 * nv_get_stats: dev->get_stats function
798 * Get latest stats value from the nic.
799 * Called with read_lock(&dev_base_lock) held for read -
800 * only synchronized against unregister_netdevice.
802 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
804 struct fe_priv
*np
= get_nvpriv(dev
);
806 /* It seems that the nic always generates interrupts and doesn't
807 * accumulate errors internally. Thus the current values in np->stats
808 * are already up to date.
814 * nv_alloc_rx: fill rx ring entries.
815 * Return 1 if the allocations for the skbs failed and the
816 * rx engine is without Available descriptors
818 static int nv_alloc_rx(struct net_device
*dev
)
820 struct fe_priv
*np
= get_nvpriv(dev
);
821 unsigned int refill_rx
= np
->refill_rx
;
824 while (np
->cur_rx
!= refill_rx
) {
827 nr
= refill_rx
% RX_RING
;
828 if (np
->rx_skbuff
[nr
] == NULL
) {
830 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
835 np
->rx_skbuff
[nr
] = skb
;
837 skb
= np
->rx_skbuff
[nr
];
839 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
, skb
->len
,
841 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
842 np
->rx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->rx_dma
[nr
]);
844 np
->rx_ring
.orig
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
846 np
->rx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->rx_dma
[nr
]) >> 32;
847 np
->rx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->rx_dma
[nr
]) & 0x0FFFFFFFF;
849 np
->rx_ring
.ex
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
851 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
852 dev
->name
, refill_rx
);
855 np
->refill_rx
= refill_rx
;
856 if (np
->cur_rx
- refill_rx
== RX_RING
)
861 static void nv_do_rx_refill(unsigned long data
)
863 struct net_device
*dev
= (struct net_device
*) data
;
864 struct fe_priv
*np
= get_nvpriv(dev
);
866 disable_irq(dev
->irq
);
867 if (nv_alloc_rx(dev
)) {
868 spin_lock(&np
->lock
);
869 if (!np
->in_shutdown
)
870 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
871 spin_unlock(&np
->lock
);
873 enable_irq(dev
->irq
);
876 static void nv_init_rx(struct net_device
*dev
)
878 struct fe_priv
*np
= get_nvpriv(dev
);
881 np
->cur_rx
= RX_RING
;
883 for (i
= 0; i
< RX_RING
; i
++)
884 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
885 np
->rx_ring
.orig
[i
].FlagLen
= 0;
887 np
->rx_ring
.ex
[i
].FlagLen
= 0;
890 static void nv_init_tx(struct net_device
*dev
)
892 struct fe_priv
*np
= get_nvpriv(dev
);
895 np
->next_tx
= np
->nic_tx
= 0;
896 for (i
= 0; i
< TX_RING
; i
++)
897 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
898 np
->tx_ring
.orig
[i
].FlagLen
= 0;
900 np
->tx_ring
.ex
[i
].FlagLen
= 0;
903 static int nv_init_ring(struct net_device
*dev
)
907 return nv_alloc_rx(dev
);
910 static void nv_drain_tx(struct net_device
*dev
)
912 struct fe_priv
*np
= get_nvpriv(dev
);
914 for (i
= 0; i
< TX_RING
; i
++) {
915 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
916 np
->tx_ring
.orig
[i
].FlagLen
= 0;
918 np
->tx_ring
.ex
[i
].FlagLen
= 0;
919 if (np
->tx_skbuff
[i
]) {
920 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
921 np
->tx_skbuff
[i
]->len
,
923 dev_kfree_skb(np
->tx_skbuff
[i
]);
924 np
->tx_skbuff
[i
] = NULL
;
925 np
->stats
.tx_dropped
++;
930 static void nv_drain_rx(struct net_device
*dev
)
932 struct fe_priv
*np
= get_nvpriv(dev
);
934 for (i
= 0; i
< RX_RING
; i
++) {
935 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
936 np
->rx_ring
.orig
[i
].FlagLen
= 0;
938 np
->rx_ring
.ex
[i
].FlagLen
= 0;
940 if (np
->rx_skbuff
[i
]) {
941 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
942 np
->rx_skbuff
[i
]->len
,
944 dev_kfree_skb(np
->rx_skbuff
[i
]);
945 np
->rx_skbuff
[i
] = NULL
;
950 static void drain_ring(struct net_device
*dev
)
957 * nv_start_xmit: dev->hard_start_xmit function
958 * Called with dev->xmit_lock held.
960 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
962 struct fe_priv
*np
= get_nvpriv(dev
);
963 int nr
= np
->next_tx
% TX_RING
;
965 np
->tx_skbuff
[nr
] = skb
;
966 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,skb
->len
,
969 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
970 np
->tx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
972 np
->tx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
973 np
->tx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
976 spin_lock_irq(&np
->lock
);
978 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
979 np
->tx_ring
.orig
[nr
].FlagLen
= cpu_to_le32( (skb
->len
-1) | np
->tx_flags
);
981 np
->tx_ring
.ex
[nr
].FlagLen
= cpu_to_le32( (skb
->len
-1) | np
->tx_flags
);
982 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet packet %d queued for transmission.\n",
983 dev
->name
, np
->next_tx
);
986 for (j
=0; j
<64; j
++) {
988 dprintk("\n%03x:", j
);
989 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
996 dev
->trans_start
= jiffies
;
997 if (np
->next_tx
- np
->nic_tx
>= TX_LIMIT_STOP
)
998 netif_stop_queue(dev
);
999 spin_unlock_irq(&np
->lock
);
1000 writel(NVREG_TXRXCTL_KICK
|np
->desc_ver
, get_hwbase(dev
) + NvRegTxRxControl
);
1001 pci_push(get_hwbase(dev
));
1006 * nv_tx_done: check for completed packets, release the skbs.
1008 * Caller must own np->lock.
1010 static void nv_tx_done(struct net_device
*dev
)
1012 struct fe_priv
*np
= get_nvpriv(dev
);
1016 while (np
->nic_tx
!= np
->next_tx
) {
1017 i
= np
->nic_tx
% TX_RING
;
1019 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1020 Flags
= le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
);
1022 Flags
= le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
);
1024 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1025 dev
->name
, np
->nic_tx
, Flags
);
1026 if (Flags
& NV_TX_VALID
)
1028 if (np
->desc_ver
== DESC_VER_1
) {
1029 if (Flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1030 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1031 if (Flags
& NV_TX_UNDERFLOW
)
1032 np
->stats
.tx_fifo_errors
++;
1033 if (Flags
& NV_TX_CARRIERLOST
)
1034 np
->stats
.tx_carrier_errors
++;
1035 np
->stats
.tx_errors
++;
1037 np
->stats
.tx_packets
++;
1038 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
1041 if (Flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1042 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1043 if (Flags
& NV_TX2_UNDERFLOW
)
1044 np
->stats
.tx_fifo_errors
++;
1045 if (Flags
& NV_TX2_CARRIERLOST
)
1046 np
->stats
.tx_carrier_errors
++;
1047 np
->stats
.tx_errors
++;
1049 np
->stats
.tx_packets
++;
1050 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
1053 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
1054 np
->tx_skbuff
[i
]->len
,
1056 dev_kfree_skb_irq(np
->tx_skbuff
[i
]);
1057 np
->tx_skbuff
[i
] = NULL
;
1060 if (np
->next_tx
- np
->nic_tx
< TX_LIMIT_START
)
1061 netif_wake_queue(dev
);
1065 * nv_tx_timeout: dev->tx_timeout function
1066 * Called with dev->xmit_lock held.
1068 static void nv_tx_timeout(struct net_device
*dev
)
1070 struct fe_priv
*np
= get_nvpriv(dev
);
1071 u8 __iomem
*base
= get_hwbase(dev
);
1073 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
,
1074 readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
);
1079 printk(KERN_INFO
"%s: Ring at %lx: next %d nic %d\n",
1080 dev
->name
, (unsigned long)np
->ring_addr
,
1081 np
->next_tx
, np
->nic_tx
);
1082 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
1083 for (i
=0;i
<0x400;i
+= 32) {
1084 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1086 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
1087 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
1088 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
1089 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
1091 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
1092 for (i
=0;i
<TX_RING
;i
+= 4) {
1093 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1094 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1096 le32_to_cpu(np
->tx_ring
.orig
[i
].PacketBuffer
),
1097 le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
),
1098 le32_to_cpu(np
->tx_ring
.orig
[i
+1].PacketBuffer
),
1099 le32_to_cpu(np
->tx_ring
.orig
[i
+1].FlagLen
),
1100 le32_to_cpu(np
->tx_ring
.orig
[i
+2].PacketBuffer
),
1101 le32_to_cpu(np
->tx_ring
.orig
[i
+2].FlagLen
),
1102 le32_to_cpu(np
->tx_ring
.orig
[i
+3].PacketBuffer
),
1103 le32_to_cpu(np
->tx_ring
.orig
[i
+3].FlagLen
));
1105 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1107 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferHigh
),
1108 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferLow
),
1109 le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
),
1110 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferHigh
),
1111 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferLow
),
1112 le32_to_cpu(np
->tx_ring
.ex
[i
+1].FlagLen
),
1113 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferHigh
),
1114 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferLow
),
1115 le32_to_cpu(np
->tx_ring
.ex
[i
+2].FlagLen
),
1116 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferHigh
),
1117 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferLow
),
1118 le32_to_cpu(np
->tx_ring
.ex
[i
+3].FlagLen
));
1123 spin_lock_irq(&np
->lock
);
1125 /* 1) stop tx engine */
1128 /* 2) check that the packets were not sent already: */
1131 /* 3) if there are dead entries: clear everything */
1132 if (np
->next_tx
!= np
->nic_tx
) {
1133 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1135 np
->next_tx
= np
->nic_tx
= 0;
1136 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1137 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1139 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
1140 netif_wake_queue(dev
);
1143 /* 4) restart tx engine */
1145 spin_unlock_irq(&np
->lock
);
1149 * Called when the nic notices a mismatch between the actual data len on the
1150 * wire and the len indicated in the 802 header
1152 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1154 int hdrlen
; /* length of the 802 header */
1155 int protolen
; /* length as stored in the proto field */
1157 /* 1) calculate len according to header */
1158 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== __constant_htons(ETH_P_8021Q
)) {
1159 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1162 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1165 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1166 dev
->name
, datalen
, protolen
, hdrlen
);
1167 if (protolen
> ETH_DATA_LEN
)
1168 return datalen
; /* Value in proto field not a len, no checks possible */
1171 /* consistency checks: */
1172 if (datalen
> ETH_ZLEN
) {
1173 if (datalen
>= protolen
) {
1174 /* more data on wire than in 802 header, trim of
1177 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1178 dev
->name
, protolen
);
1181 /* less data on wire than mentioned in header.
1182 * Discard the packet.
1184 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1189 /* short packet. Accept only if 802 values are also short */
1190 if (protolen
> ETH_ZLEN
) {
1191 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1195 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1196 dev
->name
, datalen
);
1201 static void nv_rx_process(struct net_device
*dev
)
1203 struct fe_priv
*np
= get_nvpriv(dev
);
1207 struct sk_buff
*skb
;
1210 if (np
->cur_rx
- np
->refill_rx
>= RX_RING
)
1211 break; /* we scanned the whole ring - do not continue */
1213 i
= np
->cur_rx
% RX_RING
;
1214 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1215 Flags
= le32_to_cpu(np
->rx_ring
.orig
[i
].FlagLen
);
1216 len
= nv_descr_getlength(&np
->rx_ring
.orig
[i
], np
->desc_ver
);
1218 Flags
= le32_to_cpu(np
->rx_ring
.ex
[i
].FlagLen
);
1219 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[i
], np
->desc_ver
);
1222 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1223 dev
->name
, np
->cur_rx
, Flags
);
1225 if (Flags
& NV_RX_AVAIL
)
1226 break; /* still owned by hardware, */
1229 * the packet is for us - immediately tear down the pci mapping.
1230 * TODO: check if a prefetch of the first cacheline improves
1233 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1234 np
->rx_skbuff
[i
]->len
,
1235 PCI_DMA_FROMDEVICE
);
1239 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",Flags
);
1240 for (j
=0; j
<64; j
++) {
1242 dprintk("\n%03x:", j
);
1243 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1247 /* look at what we actually got: */
1248 if (np
->desc_ver
== DESC_VER_1
) {
1249 if (!(Flags
& NV_RX_DESCRIPTORVALID
))
1252 if (Flags
& NV_RX_MISSEDFRAME
) {
1253 np
->stats
.rx_missed_errors
++;
1254 np
->stats
.rx_errors
++;
1257 if (Flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1258 np
->stats
.rx_errors
++;
1261 if (Flags
& NV_RX_CRCERR
) {
1262 np
->stats
.rx_crc_errors
++;
1263 np
->stats
.rx_errors
++;
1266 if (Flags
& NV_RX_OVERFLOW
) {
1267 np
->stats
.rx_over_errors
++;
1268 np
->stats
.rx_errors
++;
1271 if (Flags
& NV_RX_ERROR4
) {
1272 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1274 np
->stats
.rx_errors
++;
1278 /* framing errors are soft errors. */
1279 if (Flags
& NV_RX_FRAMINGERR
) {
1280 if (Flags
& NV_RX_SUBSTRACT1
) {
1285 if (!(Flags
& NV_RX2_DESCRIPTORVALID
))
1288 if (Flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1289 np
->stats
.rx_errors
++;
1292 if (Flags
& NV_RX2_CRCERR
) {
1293 np
->stats
.rx_crc_errors
++;
1294 np
->stats
.rx_errors
++;
1297 if (Flags
& NV_RX2_OVERFLOW
) {
1298 np
->stats
.rx_over_errors
++;
1299 np
->stats
.rx_errors
++;
1302 if (Flags
& NV_RX2_ERROR4
) {
1303 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1305 np
->stats
.rx_errors
++;
1309 /* framing errors are soft errors */
1310 if (Flags
& NV_RX2_FRAMINGERR
) {
1311 if (Flags
& NV_RX2_SUBSTRACT1
) {
1315 Flags
&= NV_RX2_CHECKSUMMASK
;
1316 if (Flags
== NV_RX2_CHECKSUMOK1
||
1317 Flags
== NV_RX2_CHECKSUMOK2
||
1318 Flags
== NV_RX2_CHECKSUMOK3
) {
1319 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1320 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1322 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1325 /* got a valid packet - forward it to the network core */
1326 skb
= np
->rx_skbuff
[i
];
1327 np
->rx_skbuff
[i
] = NULL
;
1330 skb
->protocol
= eth_type_trans(skb
, dev
);
1331 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1332 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1334 dev
->last_rx
= jiffies
;
1335 np
->stats
.rx_packets
++;
1336 np
->stats
.rx_bytes
+= len
;
1342 static void set_bufsize(struct net_device
*dev
)
1344 struct fe_priv
*np
= netdev_priv(dev
);
1346 if (dev
->mtu
<= ETH_DATA_LEN
)
1347 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1349 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1353 * nv_change_mtu: dev->change_mtu function
1354 * Called with dev_base_lock held for read.
1356 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1358 struct fe_priv
*np
= get_nvpriv(dev
);
1361 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
1367 /* return early if the buffer sizes will not change */
1368 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1370 if (old_mtu
== new_mtu
)
1373 /* synchronized against open : rtnl_lock() held by caller */
1374 if (netif_running(dev
)) {
1375 u8 __iomem
*base
= get_hwbase(dev
);
1377 * It seems that the nic preloads valid ring entries into an
1378 * internal buffer. The procedure for flushing everything is
1379 * guessed, there is probably a simpler approach.
1380 * Changing the MTU is a rare event, it shouldn't matter.
1382 disable_irq(dev
->irq
);
1383 spin_lock_bh(&dev
->xmit_lock
);
1384 spin_lock(&np
->lock
);
1389 /* drain rx queue */
1392 /* reinit driver view of the rx queue */
1395 /* alloc new rx buffers */
1397 if (nv_alloc_rx(dev
)) {
1398 if (!np
->in_shutdown
)
1399 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1401 /* reinit nic view of the rx queue */
1402 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1403 writel((u32
) np
->ring_addr
, base
+ NvRegRxRingPhysAddr
);
1404 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1405 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1407 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
1408 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1409 base
+ NvRegRingSizes
);
1411 writel(NVREG_TXRXCTL_KICK
|np
->desc_ver
, get_hwbase(dev
) + NvRegTxRxControl
);
1414 /* restart rx engine */
1417 spin_unlock(&np
->lock
);
1418 spin_unlock_bh(&dev
->xmit_lock
);
1419 enable_irq(dev
->irq
);
1424 static void nv_copy_mac_to_hw(struct net_device
*dev
)
1426 u8 __iomem
*base
= get_hwbase(dev
);
1429 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1430 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1431 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1433 writel(mac
[0], base
+ NvRegMacAddrA
);
1434 writel(mac
[1], base
+ NvRegMacAddrB
);
1438 * nv_set_mac_address: dev->set_mac_address function
1439 * Called with rtnl_lock() held.
1441 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
1443 struct fe_priv
*np
= get_nvpriv(dev
);
1444 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
1446 if(!is_valid_ether_addr(macaddr
->sa_data
))
1447 return -EADDRNOTAVAIL
;
1449 /* synchronized against open : rtnl_lock() held by caller */
1450 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
1452 if (netif_running(dev
)) {
1453 spin_lock_bh(&dev
->xmit_lock
);
1454 spin_lock_irq(&np
->lock
);
1456 /* stop rx engine */
1459 /* set mac address */
1460 nv_copy_mac_to_hw(dev
);
1462 /* restart rx engine */
1464 spin_unlock_irq(&np
->lock
);
1465 spin_unlock_bh(&dev
->xmit_lock
);
1467 nv_copy_mac_to_hw(dev
);
1473 * nv_set_multicast: dev->set_multicast function
1474 * Called with dev->xmit_lock held.
1476 static void nv_set_multicast(struct net_device
*dev
)
1478 struct fe_priv
*np
= get_nvpriv(dev
);
1479 u8 __iomem
*base
= get_hwbase(dev
);
1484 memset(addr
, 0, sizeof(addr
));
1485 memset(mask
, 0, sizeof(mask
));
1487 if (dev
->flags
& IFF_PROMISC
) {
1488 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
1489 pff
= NVREG_PFF_PROMISC
;
1491 pff
= NVREG_PFF_MYADDR
;
1493 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
1497 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
1498 if (dev
->flags
& IFF_ALLMULTI
) {
1499 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
1501 struct dev_mc_list
*walk
;
1503 walk
= dev
->mc_list
;
1504 while (walk
!= NULL
) {
1506 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
1507 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
1515 addr
[0] = alwaysOn
[0];
1516 addr
[1] = alwaysOn
[1];
1517 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
1518 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
1521 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
1522 pff
|= NVREG_PFF_ALWAYS
;
1523 spin_lock_irq(&np
->lock
);
1525 writel(addr
[0], base
+ NvRegMulticastAddrA
);
1526 writel(addr
[1], base
+ NvRegMulticastAddrB
);
1527 writel(mask
[0], base
+ NvRegMulticastMaskA
);
1528 writel(mask
[1], base
+ NvRegMulticastMaskB
);
1529 writel(pff
, base
+ NvRegPacketFilterFlags
);
1530 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
1533 spin_unlock_irq(&np
->lock
);
1536 static int nv_update_linkspeed(struct net_device
*dev
)
1538 struct fe_priv
*np
= get_nvpriv(dev
);
1539 u8 __iomem
*base
= get_hwbase(dev
);
1541 int newls
= np
->linkspeed
;
1542 int newdup
= np
->duplex
;
1545 u32 control_1000
, status_1000
, phyreg
;
1547 /* BMSR_LSTATUS is latched, read it twice:
1548 * we want the current value.
1550 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1551 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1553 if (!(mii_status
& BMSR_LSTATUS
)) {
1554 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
1556 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1562 if (np
->autoneg
== 0) {
1563 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1564 dev
->name
, np
->fixed_mode
);
1565 if (np
->fixed_mode
& LPA_100FULL
) {
1566 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1568 } else if (np
->fixed_mode
& LPA_100HALF
) {
1569 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1571 } else if (np
->fixed_mode
& LPA_10FULL
) {
1572 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1575 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1581 /* check auto negotiation is complete */
1582 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
1583 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1584 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1587 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
1592 if (np
->gigabit
== PHY_GIGABIT
) {
1593 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1594 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_SR
, MII_READ
);
1596 if ((control_1000
& ADVERTISE_1000FULL
) &&
1597 (status_1000
& LPA_1000FULL
)) {
1598 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
1600 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
1606 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1607 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
1608 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1609 dev
->name
, adv
, lpa
);
1611 /* FIXME: handle parallel detection properly */
1613 if (lpa
& LPA_100FULL
) {
1614 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1616 } else if (lpa
& LPA_100HALF
) {
1617 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1619 } else if (lpa
& LPA_10FULL
) {
1620 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1622 } else if (lpa
& LPA_10HALF
) {
1623 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1626 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, lpa
);
1627 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1632 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
1635 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
1636 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
1638 np
->duplex
= newdup
;
1639 np
->linkspeed
= newls
;
1641 if (np
->gigabit
== PHY_GIGABIT
) {
1642 phyreg
= readl(base
+ NvRegRandomSeed
);
1643 phyreg
&= ~(0x3FF00);
1644 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
1645 phyreg
|= NVREG_RNDSEED_FORCE3
;
1646 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1647 phyreg
|= NVREG_RNDSEED_FORCE2
;
1648 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1649 phyreg
|= NVREG_RNDSEED_FORCE
;
1650 writel(phyreg
, base
+ NvRegRandomSeed
);
1653 phyreg
= readl(base
+ NvRegPhyInterface
);
1654 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
1655 if (np
->duplex
== 0)
1657 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
1659 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
1661 writel(phyreg
, base
+ NvRegPhyInterface
);
1663 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
1666 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1672 static void nv_linkchange(struct net_device
*dev
)
1674 if (nv_update_linkspeed(dev
)) {
1675 if (netif_carrier_ok(dev
)) {
1678 netif_carrier_on(dev
);
1679 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
1683 if (netif_carrier_ok(dev
)) {
1684 netif_carrier_off(dev
);
1685 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
1691 static void nv_link_irq(struct net_device
*dev
)
1693 u8 __iomem
*base
= get_hwbase(dev
);
1696 miistat
= readl(base
+ NvRegMIIStatus
);
1697 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1698 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
1700 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
1702 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
1705 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
1707 struct net_device
*dev
= (struct net_device
*) data
;
1708 struct fe_priv
*np
= get_nvpriv(dev
);
1709 u8 __iomem
*base
= get_hwbase(dev
);
1713 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
1716 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1717 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1719 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
1720 if (!(events
& np
->irqmask
))
1723 if (events
& (NVREG_IRQ_TX1
|NVREG_IRQ_TX_OK
|NVREG_IRQ_TX_ERROR
|NVREG_IRQ_TX_ERR
)) {
1724 spin_lock(&np
->lock
);
1726 spin_unlock(&np
->lock
);
1729 if (events
& (NVREG_IRQ_RX_ERROR
|NVREG_IRQ_RX
|NVREG_IRQ_RX_NOBUF
)) {
1731 if (nv_alloc_rx(dev
)) {
1732 spin_lock(&np
->lock
);
1733 if (!np
->in_shutdown
)
1734 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1735 spin_unlock(&np
->lock
);
1739 if (events
& NVREG_IRQ_LINK
) {
1740 spin_lock(&np
->lock
);
1742 spin_unlock(&np
->lock
);
1744 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
1745 spin_lock(&np
->lock
);
1747 spin_unlock(&np
->lock
);
1748 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
1750 if (events
& (NVREG_IRQ_TX_ERR
)) {
1751 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
1754 if (events
& (NVREG_IRQ_UNKNOWN
)) {
1755 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
1758 if (i
> max_interrupt_work
) {
1759 spin_lock(&np
->lock
);
1760 /* disable interrupts on the nic */
1761 writel(0, base
+ NvRegIrqMask
);
1764 if (!np
->in_shutdown
)
1765 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
1766 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
1767 spin_unlock(&np
->lock
);
1772 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
1774 return IRQ_RETVAL(i
);
1777 static void nv_do_nic_poll(unsigned long data
)
1779 struct net_device
*dev
= (struct net_device
*) data
;
1780 struct fe_priv
*np
= get_nvpriv(dev
);
1781 u8 __iomem
*base
= get_hwbase(dev
);
1783 disable_irq(dev
->irq
);
1784 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1786 * reenable interrupts on the nic, we have to do this before calling
1787 * nv_nic_irq because that may decide to do otherwise
1789 writel(np
->irqmask
, base
+ NvRegIrqMask
);
1791 nv_nic_irq((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
1792 enable_irq(dev
->irq
);
1795 #ifdef CONFIG_NET_POLL_CONTROLLER
1796 static void nv_poll_controller(struct net_device
*dev
)
1798 nv_do_nic_poll((unsigned long) dev
);
1802 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1804 struct fe_priv
*np
= get_nvpriv(dev
);
1805 strcpy(info
->driver
, "forcedeth");
1806 strcpy(info
->version
, FORCEDETH_VERSION
);
1807 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
1810 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
1812 struct fe_priv
*np
= get_nvpriv(dev
);
1813 wolinfo
->supported
= WAKE_MAGIC
;
1815 spin_lock_irq(&np
->lock
);
1817 wolinfo
->wolopts
= WAKE_MAGIC
;
1818 spin_unlock_irq(&np
->lock
);
1821 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
1823 struct fe_priv
*np
= get_nvpriv(dev
);
1824 u8 __iomem
*base
= get_hwbase(dev
);
1826 spin_lock_irq(&np
->lock
);
1827 if (wolinfo
->wolopts
== 0) {
1828 writel(0, base
+ NvRegWakeUpFlags
);
1831 if (wolinfo
->wolopts
& WAKE_MAGIC
) {
1832 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
1835 spin_unlock_irq(&np
->lock
);
1839 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1841 struct fe_priv
*np
= netdev_priv(dev
);
1844 spin_lock_irq(&np
->lock
);
1845 ecmd
->port
= PORT_MII
;
1846 if (!netif_running(dev
)) {
1847 /* We do not track link speed / duplex setting if the
1848 * interface is disabled. Force a link check */
1849 nv_update_linkspeed(dev
);
1851 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
1852 case NVREG_LINKSPEED_10
:
1853 ecmd
->speed
= SPEED_10
;
1855 case NVREG_LINKSPEED_100
:
1856 ecmd
->speed
= SPEED_100
;
1858 case NVREG_LINKSPEED_1000
:
1859 ecmd
->speed
= SPEED_1000
;
1862 ecmd
->duplex
= DUPLEX_HALF
;
1864 ecmd
->duplex
= DUPLEX_FULL
;
1866 ecmd
->autoneg
= np
->autoneg
;
1868 ecmd
->advertising
= ADVERTISED_MII
;
1870 ecmd
->advertising
|= ADVERTISED_Autoneg
;
1871 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1873 adv
= np
->fixed_mode
;
1875 if (adv
& ADVERTISE_10HALF
)
1876 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
1877 if (adv
& ADVERTISE_10FULL
)
1878 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
1879 if (adv
& ADVERTISE_100HALF
)
1880 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
1881 if (adv
& ADVERTISE_100FULL
)
1882 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
1883 if (np
->autoneg
&& np
->gigabit
== PHY_GIGABIT
) {
1884 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1885 if (adv
& ADVERTISE_1000FULL
)
1886 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
1889 ecmd
->supported
= (SUPPORTED_Autoneg
|
1890 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
1891 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
1893 if (np
->gigabit
== PHY_GIGABIT
)
1894 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
1896 ecmd
->phy_address
= np
->phyaddr
;
1897 ecmd
->transceiver
= XCVR_EXTERNAL
;
1899 /* ignore maxtxpkt, maxrxpkt for now */
1900 spin_unlock_irq(&np
->lock
);
1904 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1906 struct fe_priv
*np
= netdev_priv(dev
);
1908 if (ecmd
->port
!= PORT_MII
)
1910 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
1912 if (ecmd
->phy_address
!= np
->phyaddr
) {
1913 /* TODO: support switching between multiple phys. Should be
1914 * trivial, but not enabled due to lack of test hardware. */
1917 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
1920 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
1921 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
1922 if (np
->gigabit
== PHY_GIGABIT
)
1923 mask
|= ADVERTISED_1000baseT_Full
;
1925 if ((ecmd
->advertising
& mask
) == 0)
1928 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
1929 /* Note: autonegotiation disable, speed 1000 intentionally
1930 * forbidden - noone should need that. */
1932 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
1934 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
1940 spin_lock_irq(&np
->lock
);
1941 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
1946 /* advertise only what has been requested */
1947 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1948 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
1949 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
1950 adv
|= ADVERTISE_10HALF
;
1951 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
1952 adv
|= ADVERTISE_10FULL
;
1953 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
1954 adv
|= ADVERTISE_100HALF
;
1955 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
1956 adv
|= ADVERTISE_100FULL
;
1957 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
1959 if (np
->gigabit
== PHY_GIGABIT
) {
1960 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1961 adv
&= ~ADVERTISE_1000FULL
;
1962 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
1963 adv
|= ADVERTISE_1000FULL
;
1964 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
1967 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1968 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1969 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
1976 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1977 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
1978 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
1979 adv
|= ADVERTISE_10HALF
;
1980 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
1981 adv
|= ADVERTISE_10FULL
;
1982 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
1983 adv
|= ADVERTISE_100HALF
;
1984 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
1985 adv
|= ADVERTISE_100FULL
;
1986 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
1987 np
->fixed_mode
= adv
;
1989 if (np
->gigabit
== PHY_GIGABIT
) {
1990 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1991 adv
&= ~ADVERTISE_1000FULL
;
1992 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
1995 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1996 bmcr
|= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_FULLDPLX
);
1997 if (adv
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
1998 bmcr
|= BMCR_FULLDPLX
;
1999 if (adv
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
2000 bmcr
|= BMCR_SPEED100
;
2001 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2003 if (netif_running(dev
)) {
2004 /* Wait a bit and then reconfigure the nic. */
2009 spin_unlock_irq(&np
->lock
);
2014 #define FORCEDETH_REGS_VER 1
2015 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2017 static int nv_get_regs_len(struct net_device
*dev
)
2019 return FORCEDETH_REGS_SIZE
;
2022 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
2024 struct fe_priv
*np
= get_nvpriv(dev
);
2025 u8 __iomem
*base
= get_hwbase(dev
);
2029 regs
->version
= FORCEDETH_REGS_VER
;
2030 spin_lock_irq(&np
->lock
);
2031 for (i
=0;i
<FORCEDETH_REGS_SIZE
/sizeof(u32
);i
++)
2032 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
2033 spin_unlock_irq(&np
->lock
);
2036 static int nv_nway_reset(struct net_device
*dev
)
2038 struct fe_priv
*np
= get_nvpriv(dev
);
2041 spin_lock_irq(&np
->lock
);
2045 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2046 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
2047 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2053 spin_unlock_irq(&np
->lock
);
2058 static struct ethtool_ops ops
= {
2059 .get_drvinfo
= nv_get_drvinfo
,
2060 .get_link
= ethtool_op_get_link
,
2061 .get_wol
= nv_get_wol
,
2062 .set_wol
= nv_set_wol
,
2063 .get_settings
= nv_get_settings
,
2064 .set_settings
= nv_set_settings
,
2065 .get_regs_len
= nv_get_regs_len
,
2066 .get_regs
= nv_get_regs
,
2067 .nway_reset
= nv_nway_reset
,
2070 static int nv_open(struct net_device
*dev
)
2072 struct fe_priv
*np
= get_nvpriv(dev
);
2073 u8 __iomem
*base
= get_hwbase(dev
);
2076 dprintk(KERN_DEBUG
"nv_open: begin\n");
2078 /* 1) erase previous misconfiguration */
2079 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2080 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2081 writel(0, base
+ NvRegMulticastAddrB
);
2082 writel(0, base
+ NvRegMulticastMaskA
);
2083 writel(0, base
+ NvRegMulticastMaskB
);
2084 writel(0, base
+ NvRegPacketFilterFlags
);
2086 writel(0, base
+ NvRegTransmitterControl
);
2087 writel(0, base
+ NvRegReceiverControl
);
2089 writel(0, base
+ NvRegAdapterControl
);
2091 /* 2) initialize descriptor rings */
2093 oom
= nv_init_ring(dev
);
2095 writel(0, base
+ NvRegLinkSpeed
);
2096 writel(0, base
+ NvRegUnknownTransmitterReg
);
2098 writel(0, base
+ NvRegUnknownSetupReg6
);
2100 np
->in_shutdown
= 0;
2102 /* 3) set mac address */
2103 nv_copy_mac_to_hw(dev
);
2105 /* 4) give hw rings */
2106 writel((u32
) np
->ring_addr
, base
+ NvRegRxRingPhysAddr
);
2107 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
2108 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
2110 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
2111 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
2112 base
+ NvRegRingSizes
);
2114 /* 5) continue setup */
2115 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
2116 writel(NVREG_UNKSETUP3_VAL1
, base
+ NvRegUnknownSetupReg3
);
2117 writel(np
->desc_ver
, base
+ NvRegTxRxControl
);
2119 writel(NVREG_TXRXCTL_BIT1
|np
->desc_ver
, base
+ NvRegTxRxControl
);
2120 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
2121 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
2122 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
2124 writel(0, base
+ NvRegUnknownSetupReg4
);
2125 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2126 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2128 /* 6) continue setup */
2129 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
2130 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
2131 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
2132 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2134 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
2135 get_random_bytes(&i
, sizeof(i
));
2136 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
2137 writel(NVREG_UNKSETUP1_VAL
, base
+ NvRegUnknownSetupReg1
);
2138 writel(NVREG_UNKSETUP2_VAL
, base
+ NvRegUnknownSetupReg2
);
2139 writel(NVREG_POLL_DEFAULT
, base
+ NvRegPollingInterval
);
2140 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
2141 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
2142 base
+ NvRegAdapterControl
);
2143 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
2144 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
2145 writel(NVREG_WAKEUPFLAGS_VAL
, base
+ NvRegWakeUpFlags
);
2147 i
= readl(base
+ NvRegPowerState
);
2148 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
2149 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
2153 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
2155 writel(0, base
+ NvRegIrqMask
);
2157 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2158 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2161 ret
= request_irq(dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
);
2165 /* ask for interrupts */
2166 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2168 spin_lock_irq(&np
->lock
);
2169 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2170 writel(0, base
+ NvRegMulticastAddrB
);
2171 writel(0, base
+ NvRegMulticastMaskA
);
2172 writel(0, base
+ NvRegMulticastMaskB
);
2173 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
2174 /* One manual link speed update: Interrupts are enabled, future link
2175 * speed changes cause interrupts and are handled by nv_link_irq().
2179 miistat
= readl(base
+ NvRegMIIStatus
);
2180 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2181 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
2183 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2186 ret
= nv_update_linkspeed(dev
);
2189 netif_start_queue(dev
);
2191 netif_carrier_on(dev
);
2193 printk("%s: no link during initialization.\n", dev
->name
);
2194 netif_carrier_off(dev
);
2197 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2198 spin_unlock_irq(&np
->lock
);
2206 static int nv_close(struct net_device
*dev
)
2208 struct fe_priv
*np
= get_nvpriv(dev
);
2211 spin_lock_irq(&np
->lock
);
2212 np
->in_shutdown
= 1;
2213 spin_unlock_irq(&np
->lock
);
2214 synchronize_irq(dev
->irq
);
2216 del_timer_sync(&np
->oom_kick
);
2217 del_timer_sync(&np
->nic_poll
);
2219 netif_stop_queue(dev
);
2220 spin_lock_irq(&np
->lock
);
2225 /* disable interrupts on the nic or we will lock up */
2226 base
= get_hwbase(dev
);
2227 writel(0, base
+ NvRegIrqMask
);
2229 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
2231 spin_unlock_irq(&np
->lock
);
2233 free_irq(dev
->irq
, dev
);
2240 /* special op: write back the misordered MAC address - otherwise
2241 * the next nv_probe would see a wrong address.
2243 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
2244 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
2246 /* FIXME: power down nic */
2251 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
2253 struct net_device
*dev
;
2259 dev
= alloc_etherdev(sizeof(struct fe_priv
));
2264 np
= get_nvpriv(dev
);
2265 np
->pci_dev
= pci_dev
;
2266 spin_lock_init(&np
->lock
);
2267 SET_MODULE_OWNER(dev
);
2268 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
2270 init_timer(&np
->oom_kick
);
2271 np
->oom_kick
.data
= (unsigned long) dev
;
2272 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
2273 init_timer(&np
->nic_poll
);
2274 np
->nic_poll
.data
= (unsigned long) dev
;
2275 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
2277 err
= pci_enable_device(pci_dev
);
2279 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
2280 err
, pci_name(pci_dev
));
2284 pci_set_master(pci_dev
);
2286 err
= pci_request_regions(pci_dev
, DRV_NAME
);
2292 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2293 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
2294 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
2295 pci_resource_len(pci_dev
, i
),
2296 pci_resource_flags(pci_dev
, i
));
2297 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
2298 pci_resource_len(pci_dev
, i
) >= NV_PCI_REGSZ
) {
2299 addr
= pci_resource_start(pci_dev
, i
);
2303 if (i
== DEVICE_COUNT_RESOURCE
) {
2304 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
2309 /* handle different descriptor versions */
2310 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
2311 /* packet format 3: supports 40-bit addressing */
2312 np
->desc_ver
= DESC_VER_3
;
2313 if (pci_set_dma_mask(pci_dev
, 0x0000007fffffffffULL
)) {
2314 printk(KERN_INFO
"forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2317 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
2318 /* packet format 2: supports jumbo frames */
2319 np
->desc_ver
= DESC_VER_2
;
2321 /* original packet format */
2322 np
->desc_ver
= DESC_VER_1
;
2325 np
->pkt_limit
= NV_PKTLIMIT_1
;
2326 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
2327 np
->pkt_limit
= NV_PKTLIMIT_2
;
2330 np
->base
= ioremap(addr
, NV_PCI_REGSZ
);
2333 dev
->base_addr
= (unsigned long)np
->base
;
2335 dev
->irq
= pci_dev
->irq
;
2337 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
2338 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
2339 sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
2341 if (!np
->rx_ring
.orig
)
2343 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[RX_RING
];
2345 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
2346 sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
2348 if (!np
->rx_ring
.ex
)
2350 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[RX_RING
];
2353 dev
->open
= nv_open
;
2354 dev
->stop
= nv_close
;
2355 dev
->hard_start_xmit
= nv_start_xmit
;
2356 dev
->get_stats
= nv_get_stats
;
2357 dev
->change_mtu
= nv_change_mtu
;
2358 dev
->set_mac_address
= nv_set_mac_address
;
2359 dev
->set_multicast_list
= nv_set_multicast
;
2360 #ifdef CONFIG_NET_POLL_CONTROLLER
2361 dev
->poll_controller
= nv_poll_controller
;
2363 SET_ETHTOOL_OPS(dev
, &ops
);
2364 dev
->tx_timeout
= nv_tx_timeout
;
2365 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
2367 pci_set_drvdata(pci_dev
, dev
);
2369 /* read the mac address */
2370 base
= get_hwbase(dev
);
2371 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
2372 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
2374 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
2375 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
2376 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
2377 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
2378 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
2379 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
2381 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2383 * Bad mac address. At least one bios sets the mac address
2384 * to 01:23:45:67:89:ab
2386 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2388 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
2389 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
2390 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
2391 dev
->dev_addr
[0] = 0x00;
2392 dev
->dev_addr
[1] = 0x00;
2393 dev
->dev_addr
[2] = 0x6c;
2394 get_random_bytes(&dev
->dev_addr
[3], 3);
2397 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
2398 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
2399 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
2402 writel(0, base
+ NvRegWakeUpFlags
);
2405 if (np
->desc_ver
== DESC_VER_1
) {
2406 np
->tx_flags
= NV_TX_LASTPACKET
|NV_TX_VALID
;
2408 np
->tx_flags
= NV_TX2_LASTPACKET
|NV_TX2_VALID
;
2410 np
->irqmask
= NVREG_IRQMASK_WANTED
;
2411 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
2412 np
->irqmask
|= NVREG_IRQ_TIMER
;
2413 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
2414 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
2415 np
->need_linktimer
= 1;
2416 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2418 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
2419 np
->need_linktimer
= 0;
2422 /* find a suitable phy */
2423 for (i
= 1; i
< 32; i
++) {
2426 spin_lock_irq(&np
->lock
);
2427 id1
= mii_rw(dev
, i
, MII_PHYSID1
, MII_READ
);
2428 spin_unlock_irq(&np
->lock
);
2429 if (id1
< 0 || id1
== 0xffff)
2431 spin_lock_irq(&np
->lock
);
2432 id2
= mii_rw(dev
, i
, MII_PHYSID2
, MII_READ
);
2433 spin_unlock_irq(&np
->lock
);
2434 if (id2
< 0 || id2
== 0xffff)
2437 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
2438 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
2439 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
2440 pci_name(pci_dev
), id1
, id2
, i
);
2442 np
->phy_oui
= id1
| id2
;
2446 /* PHY in isolate mode? No phy attached and user wants to
2447 * test loopback? Very odd, but can be correct.
2449 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
2458 /* set default link speed settings */
2459 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2463 err
= register_netdev(dev
);
2465 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
2468 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2469 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
2475 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
2476 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
2477 np
->rx_ring
.orig
, np
->ring_addr
);
2479 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
2480 np
->rx_ring
.ex
, np
->ring_addr
);
2481 pci_set_drvdata(pci_dev
, NULL
);
2483 iounmap(get_hwbase(dev
));
2485 pci_release_regions(pci_dev
);
2487 pci_disable_device(pci_dev
);
2494 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
2496 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
2497 struct fe_priv
*np
= get_nvpriv(dev
);
2499 unregister_netdev(dev
);
2501 /* free all structures */
2502 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
2503 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
), np
->rx_ring
.orig
, np
->ring_addr
);
2505 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
), np
->rx_ring
.ex
, np
->ring_addr
);
2506 iounmap(get_hwbase(dev
));
2507 pci_release_regions(pci_dev
);
2508 pci_disable_device(pci_dev
);
2510 pci_set_drvdata(pci_dev
, NULL
);
2513 static struct pci_device_id pci_tbl
[] = {
2514 { /* nForce Ethernet Controller */
2515 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
2516 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2518 { /* nForce2 Ethernet Controller */
2519 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
2520 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2522 { /* nForce3 Ethernet Controller */
2523 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
2524 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2526 { /* nForce3 Ethernet Controller */
2527 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
2528 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2530 { /* nForce3 Ethernet Controller */
2531 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
2532 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2534 { /* nForce3 Ethernet Controller */
2535 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
2536 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2538 { /* nForce3 Ethernet Controller */
2539 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
2540 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2542 { /* CK804 Ethernet Controller */
2543 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
2544 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2546 { /* CK804 Ethernet Controller */
2547 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
2548 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2550 { /* MCP04 Ethernet Controller */
2551 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
2552 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2554 { /* MCP04 Ethernet Controller */
2555 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
2556 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2558 { /* MCP51 Ethernet Controller */
2559 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
2560 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
,
2562 { /* MCP51 Ethernet Controller */
2563 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
2564 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
,
2566 { /* MCP55 Ethernet Controller */
2567 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
2568 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2570 { /* MCP55 Ethernet Controller */
2571 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
2572 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
,
2577 static struct pci_driver driver
= {
2578 .name
= "forcedeth",
2579 .id_table
= pci_tbl
,
2581 .remove
= __devexit_p(nv_remove
),
2585 static int __init
init_nic(void)
2587 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
2588 return pci_module_init(&driver
);
2591 static void __exit
exit_nic(void)
2593 pci_unregister_driver(&driver
);
2596 module_param(max_interrupt_work
, int, 0);
2597 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
2599 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2600 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2601 MODULE_LICENSE("GPL");
2603 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
2605 module_init(init_nic
);
2606 module_exit(exit_nic
);