2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/completion.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/irq.h>
23 #include <linux/device.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
26 #include <linux/platform_device.h>
27 #include <linux/fsl_devices.h>
29 #include <linux/of_platform.h>
30 #include <linux/gpio.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_spi.h>
34 #include <sysdev/fsl_soc.h>
38 /* SPI Controller registers */
39 struct mpc83xx_spi_reg
{
49 /* SPI Controller mode register definitions */
50 #define SPMODE_LOOP (1 << 30)
51 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
52 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
53 #define SPMODE_DIV16 (1 << 27)
54 #define SPMODE_REV (1 << 26)
55 #define SPMODE_MS (1 << 25)
56 #define SPMODE_ENABLE (1 << 24)
57 #define SPMODE_LEN(x) ((x) << 20)
58 #define SPMODE_PM(x) ((x) << 16)
59 #define SPMODE_OP (1 << 14)
60 #define SPMODE_CG(x) ((x) << 7)
63 * Default for SPI Mode:
64 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
66 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
67 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
69 /* SPIE register values */
70 #define SPIE_NE 0x00000200 /* Not empty */
71 #define SPIE_NF 0x00000100 /* Not full */
73 /* SPIM register values */
74 #define SPIM_NE 0x00000200 /* Not empty */
75 #define SPIM_NF 0x00000100 /* Not full */
77 /* SPI Controller driver's private data. */
79 struct mpc83xx_spi_reg __iomem
*base
;
81 /* rx & tx bufs from the spi_transfer */
85 /* functions to deal with different sized buffers */
86 void (*get_rx
) (u32 rx_data
, struct mpc83xx_spi
*);
87 u32(*get_tx
) (struct mpc83xx_spi
*);
92 unsigned nsecs
; /* (clock cycle time)/2 */
94 u32 spibrg
; /* SPIBRG input clock */
95 u32 rx_shift
; /* RX data reg shift when in qe mode */
96 u32 tx_shift
; /* TX data reg shift when in qe mode */
102 struct workqueue_struct
*workqueue
;
103 struct work_struct work
;
105 struct list_head queue
;
108 struct completion done
;
111 struct spi_mpc83xx_cs
{
112 /* functions to deal with different sized buffers */
113 void (*get_rx
) (u32 rx_data
, struct mpc83xx_spi
*);
114 u32 (*get_tx
) (struct mpc83xx_spi
*);
115 u32 rx_shift
; /* RX data reg shift when in qe mode */
116 u32 tx_shift
; /* TX data reg shift when in qe mode */
117 u32 hw_mode
; /* Holds HW mode register settings */
120 static inline void mpc83xx_spi_write_reg(__be32 __iomem
* reg
, u32 val
)
125 static inline u32
mpc83xx_spi_read_reg(__be32 __iomem
* reg
)
130 #define MPC83XX_SPI_RX_BUF(type) \
132 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
134 type * rx = mpc83xx_spi->rx; \
135 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
136 mpc83xx_spi->rx = rx; \
139 #define MPC83XX_SPI_TX_BUF(type) \
141 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
144 const type * tx = mpc83xx_spi->tx; \
147 data = *tx++ << mpc83xx_spi->tx_shift; \
148 mpc83xx_spi->tx = tx; \
152 MPC83XX_SPI_RX_BUF(u8
)
153 MPC83XX_SPI_RX_BUF(u16
)
154 MPC83XX_SPI_RX_BUF(u32
)
155 MPC83XX_SPI_TX_BUF(u8
)
156 MPC83XX_SPI_TX_BUF(u16
)
157 MPC83XX_SPI_TX_BUF(u32
)
159 static void mpc83xx_spi_chipselect(struct spi_device
*spi
, int value
)
161 struct mpc83xx_spi
*mpc83xx_spi
= spi_master_get_devdata(spi
->master
);
162 struct fsl_spi_platform_data
*pdata
= spi
->dev
.parent
->platform_data
;
163 bool pol
= spi
->mode
& SPI_CS_HIGH
;
164 struct spi_mpc83xx_cs
*cs
= spi
->controller_state
;
166 if (value
== BITBANG_CS_INACTIVE
) {
167 if (pdata
->cs_control
)
168 pdata
->cs_control(spi
, !pol
);
171 if (value
== BITBANG_CS_ACTIVE
) {
172 u32 regval
= mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->mode
);
174 mpc83xx_spi
->rx_shift
= cs
->rx_shift
;
175 mpc83xx_spi
->tx_shift
= cs
->tx_shift
;
176 mpc83xx_spi
->get_rx
= cs
->get_rx
;
177 mpc83xx_spi
->get_tx
= cs
->get_tx
;
179 if (cs
->hw_mode
!= regval
) {
181 __be32 __iomem
*mode
= &mpc83xx_spi
->base
->mode
;
183 regval
= cs
->hw_mode
;
184 /* Turn off IRQs locally to minimize time that
187 local_irq_save(flags
);
188 /* Turn off SPI unit prior changing mode */
189 mpc83xx_spi_write_reg(mode
, regval
& ~SPMODE_ENABLE
);
190 mpc83xx_spi_write_reg(mode
, regval
);
191 local_irq_restore(flags
);
193 if (pdata
->cs_control
)
194 pdata
->cs_control(spi
, pol
);
199 int mpc83xx_spi_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
201 struct mpc83xx_spi
*mpc83xx_spi
;
203 u8 bits_per_word
, pm
;
205 struct spi_mpc83xx_cs
*cs
= spi
->controller_state
;
207 mpc83xx_spi
= spi_master_get_devdata(spi
->master
);
210 bits_per_word
= t
->bits_per_word
;
217 /* spi_transfer level calls that work per-word */
219 bits_per_word
= spi
->bits_per_word
;
221 /* Make sure its a bit width we support [4..16, 32] */
222 if ((bits_per_word
< 4)
223 || ((bits_per_word
> 16) && (bits_per_word
!= 32)))
227 hz
= spi
->max_speed_hz
;
231 if (bits_per_word
<= 8) {
232 cs
->get_rx
= mpc83xx_spi_rx_buf_u8
;
233 cs
->get_tx
= mpc83xx_spi_tx_buf_u8
;
234 if (mpc83xx_spi
->qe_mode
) {
238 } else if (bits_per_word
<= 16) {
239 cs
->get_rx
= mpc83xx_spi_rx_buf_u16
;
240 cs
->get_tx
= mpc83xx_spi_tx_buf_u16
;
241 if (mpc83xx_spi
->qe_mode
) {
245 } else if (bits_per_word
<= 32) {
246 cs
->get_rx
= mpc83xx_spi_rx_buf_u32
;
247 cs
->get_tx
= mpc83xx_spi_tx_buf_u32
;
251 if (mpc83xx_spi
->qe_mode
&& spi
->mode
& SPI_LSB_FIRST
) {
253 if (bits_per_word
<= 8)
259 mpc83xx_spi
->rx_shift
= cs
->rx_shift
;
260 mpc83xx_spi
->tx_shift
= cs
->tx_shift
;
261 mpc83xx_spi
->get_rx
= cs
->get_rx
;
262 mpc83xx_spi
->get_tx
= cs
->get_tx
;
264 if (bits_per_word
== 32)
267 bits_per_word
= bits_per_word
- 1;
269 /* mask out bits we are going to set */
270 cs
->hw_mode
&= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
273 cs
->hw_mode
|= SPMODE_LEN(bits_per_word
);
275 if ((mpc83xx_spi
->spibrg
/ hz
) > 64) {
276 cs
->hw_mode
|= SPMODE_DIV16
;
277 pm
= mpc83xx_spi
->spibrg
/ (hz
* 64);
279 dev_err(&spi
->dev
, "Requested speed is too "
280 "low: %d Hz. Will use %d Hz instead.\n",
281 hz
, mpc83xx_spi
->spibrg
/ 1024);
285 pm
= mpc83xx_spi
->spibrg
/ (hz
* 4);
289 cs
->hw_mode
|= SPMODE_PM(pm
);
290 regval
= mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->mode
);
291 if (cs
->hw_mode
!= regval
) {
293 __be32 __iomem
*mode
= &mpc83xx_spi
->base
->mode
;
295 regval
= cs
->hw_mode
;
296 /* Turn off IRQs locally to minimize time
297 * that SPI is disabled
299 local_irq_save(flags
);
300 /* Turn off SPI unit prior changing mode */
301 mpc83xx_spi_write_reg(mode
, regval
& ~SPMODE_ENABLE
);
302 mpc83xx_spi_write_reg(mode
, regval
);
303 local_irq_restore(flags
);
308 static int mpc83xx_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
310 struct mpc83xx_spi
*mpc83xx_spi
;
311 u32 word
, len
, bits_per_word
;
313 mpc83xx_spi
= spi_master_get_devdata(spi
->master
);
315 mpc83xx_spi
->tx
= t
->tx_buf
;
316 mpc83xx_spi
->rx
= t
->rx_buf
;
317 bits_per_word
= spi
->bits_per_word
;
318 if (t
->bits_per_word
)
319 bits_per_word
= t
->bits_per_word
;
321 if (bits_per_word
> 8) {
322 /* invalid length? */
327 if (bits_per_word
> 16) {
328 /* invalid length? */
333 mpc83xx_spi
->count
= len
;
335 INIT_COMPLETION(mpc83xx_spi
->done
);
338 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->mask
, SPIM_NE
);
341 word
= mpc83xx_spi
->get_tx(mpc83xx_spi
);
342 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->transmit
, word
);
344 wait_for_completion(&mpc83xx_spi
->done
);
346 /* disable rx ints */
347 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->mask
, 0);
349 return mpc83xx_spi
->count
;
352 static void mpc83xx_spi_work(struct work_struct
*work
)
354 struct mpc83xx_spi
*mpc83xx_spi
=
355 container_of(work
, struct mpc83xx_spi
, work
);
357 spin_lock_irq(&mpc83xx_spi
->lock
);
358 mpc83xx_spi
->busy
= 1;
359 while (!list_empty(&mpc83xx_spi
->queue
)) {
360 struct spi_message
*m
;
361 struct spi_device
*spi
;
362 struct spi_transfer
*t
= NULL
;
364 int status
, nsecs
= 50;
366 m
= container_of(mpc83xx_spi
->queue
.next
,
367 struct spi_message
, queue
);
368 list_del_init(&m
->queue
);
369 spin_unlock_irq(&mpc83xx_spi
->lock
);
374 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
375 if (t
->bits_per_word
|| t
->speed_hz
) {
376 /* Don't allow changes if CS is active */
380 status
= mpc83xx_spi_setup_transfer(spi
, t
);
386 mpc83xx_spi_chipselect(spi
, BITBANG_CS_ACTIVE
);
387 cs_change
= t
->cs_change
;
389 status
= mpc83xx_spi_bufs(spi
, t
);
394 m
->actual_length
+= t
->len
;
397 udelay(t
->delay_usecs
);
401 mpc83xx_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
407 m
->complete(m
->context
);
409 if (status
|| !cs_change
) {
411 mpc83xx_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
414 mpc83xx_spi_setup_transfer(spi
, NULL
);
416 spin_lock_irq(&mpc83xx_spi
->lock
);
418 mpc83xx_spi
->busy
= 0;
419 spin_unlock_irq(&mpc83xx_spi
->lock
);
422 /* the spi->mode bits understood by this driver: */
423 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
424 | SPI_LSB_FIRST | SPI_LOOP)
426 static int mpc83xx_spi_setup(struct spi_device
*spi
)
428 struct mpc83xx_spi
*mpc83xx_spi
;
431 struct spi_mpc83xx_cs
*cs
= spi
->controller_state
;
433 if (spi
->mode
& ~MODEBITS
) {
434 dev_dbg(&spi
->dev
, "setup: unsupported mode bits %x\n",
435 spi
->mode
& ~MODEBITS
);
439 if (!spi
->max_speed_hz
)
443 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
446 spi
->controller_state
= cs
;
448 mpc83xx_spi
= spi_master_get_devdata(spi
->master
);
450 hw_mode
= cs
->hw_mode
; /* Save orginal settings */
451 cs
->hw_mode
= mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->mode
);
452 /* mask out bits we are going to set */
453 cs
->hw_mode
&= ~(SPMODE_CP_BEGIN_EDGECLK
| SPMODE_CI_INACTIVEHIGH
454 | SPMODE_REV
| SPMODE_LOOP
);
456 if (spi
->mode
& SPI_CPHA
)
457 cs
->hw_mode
|= SPMODE_CP_BEGIN_EDGECLK
;
458 if (spi
->mode
& SPI_CPOL
)
459 cs
->hw_mode
|= SPMODE_CI_INACTIVEHIGH
;
460 if (!(spi
->mode
& SPI_LSB_FIRST
))
461 cs
->hw_mode
|= SPMODE_REV
;
462 if (spi
->mode
& SPI_LOOP
)
463 cs
->hw_mode
|= SPMODE_LOOP
;
465 retval
= mpc83xx_spi_setup_transfer(spi
, NULL
);
467 cs
->hw_mode
= hw_mode
; /* Restore settings */
471 #if 0 /* Don't think this is needed */
472 /* NOTE we _need_ to call chipselect() early, ideally with adapter
473 * setup, unless the hardware defaults cooperate to avoid confusion
474 * between normal (active low) and inverted chipselects.
477 /* deselect chip (low or high) */
478 spin_lock(&mpc83xx_spi
->lock
);
479 if (!mpc83xx_spi
->busy
)
480 mpc83xx_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
481 spin_unlock(&mpc83xx_spi
->lock
);
486 static irqreturn_t
mpc83xx_spi_irq(s32 irq
, void *context_data
)
488 struct mpc83xx_spi
*mpc83xx_spi
= context_data
;
490 irqreturn_t ret
= IRQ_NONE
;
492 /* Get interrupt events(tx/rx) */
493 event
= mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->event
);
495 /* We need handle RX first */
496 if (event
& SPIE_NE
) {
497 u32 rx_data
= mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->receive
);
500 mpc83xx_spi
->get_rx(rx_data
, mpc83xx_spi
);
505 if ((event
& SPIE_NF
) == 0)
506 /* spin until TX is done */
508 mpc83xx_spi_read_reg(&mpc83xx_spi
->base
->event
)) &
512 mpc83xx_spi
->count
-= 1;
513 if (mpc83xx_spi
->count
) {
514 u32 word
= mpc83xx_spi
->get_tx(mpc83xx_spi
);
515 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->transmit
, word
);
517 complete(&mpc83xx_spi
->done
);
520 /* Clear the events */
521 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->event
, event
);
525 static int mpc83xx_spi_transfer(struct spi_device
*spi
,
526 struct spi_message
*m
)
528 struct mpc83xx_spi
*mpc83xx_spi
= spi_master_get_devdata(spi
->master
);
531 m
->actual_length
= 0;
532 m
->status
= -EINPROGRESS
;
534 spin_lock_irqsave(&mpc83xx_spi
->lock
, flags
);
535 list_add_tail(&m
->queue
, &mpc83xx_spi
->queue
);
536 queue_work(mpc83xx_spi
->workqueue
, &mpc83xx_spi
->work
);
537 spin_unlock_irqrestore(&mpc83xx_spi
->lock
, flags
);
543 static void mpc83xx_spi_cleanup(struct spi_device
*spi
)
545 kfree(spi
->controller_state
);
548 static struct spi_master
* __devinit
549 mpc83xx_spi_probe(struct device
*dev
, struct resource
*mem
, unsigned int irq
)
551 struct fsl_spi_platform_data
*pdata
= dev
->platform_data
;
552 struct spi_master
*master
;
553 struct mpc83xx_spi
*mpc83xx_spi
;
557 master
= spi_alloc_master(dev
, sizeof(struct mpc83xx_spi
));
558 if (master
== NULL
) {
563 dev_set_drvdata(dev
, master
);
565 master
->setup
= mpc83xx_spi_setup
;
566 master
->transfer
= mpc83xx_spi_transfer
;
567 master
->cleanup
= mpc83xx_spi_cleanup
;
569 mpc83xx_spi
= spi_master_get_devdata(master
);
570 mpc83xx_spi
->qe_mode
= pdata
->qe_mode
;
571 mpc83xx_spi
->get_rx
= mpc83xx_spi_rx_buf_u8
;
572 mpc83xx_spi
->get_tx
= mpc83xx_spi_tx_buf_u8
;
573 mpc83xx_spi
->spibrg
= pdata
->sysclk
;
575 mpc83xx_spi
->rx_shift
= 0;
576 mpc83xx_spi
->tx_shift
= 0;
577 if (mpc83xx_spi
->qe_mode
) {
578 mpc83xx_spi
->rx_shift
= 16;
579 mpc83xx_spi
->tx_shift
= 24;
582 init_completion(&mpc83xx_spi
->done
);
584 mpc83xx_spi
->base
= ioremap(mem
->start
, mem
->end
- mem
->start
+ 1);
585 if (mpc83xx_spi
->base
== NULL
) {
590 mpc83xx_spi
->irq
= irq
;
592 /* Register for SPI Interrupt */
593 ret
= request_irq(mpc83xx_spi
->irq
, mpc83xx_spi_irq
,
594 0, "mpc83xx_spi", mpc83xx_spi
);
599 master
->bus_num
= pdata
->bus_num
;
600 master
->num_chipselect
= pdata
->max_chipselect
;
602 /* SPI controller initializations */
603 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->mode
, 0);
604 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->mask
, 0);
605 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->command
, 0);
606 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->event
, 0xffffffff);
608 /* Enable SPI interface */
609 regval
= pdata
->initial_spmode
| SPMODE_INIT_VAL
| SPMODE_ENABLE
;
613 mpc83xx_spi_write_reg(&mpc83xx_spi
->base
->mode
, regval
);
614 spin_lock_init(&mpc83xx_spi
->lock
);
615 init_completion(&mpc83xx_spi
->done
);
616 INIT_WORK(&mpc83xx_spi
->work
, mpc83xx_spi_work
);
617 INIT_LIST_HEAD(&mpc83xx_spi
->queue
);
619 mpc83xx_spi
->workqueue
= create_singlethread_workqueue(
620 dev_name(master
->dev
.parent
));
621 if (mpc83xx_spi
->workqueue
== NULL
) {
626 ret
= spi_register_master(master
);
631 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
632 dev_name(dev
), mpc83xx_spi
->base
, mpc83xx_spi
->irq
);
637 destroy_workqueue(mpc83xx_spi
->workqueue
);
639 free_irq(mpc83xx_spi
->irq
, mpc83xx_spi
);
641 iounmap(mpc83xx_spi
->base
);
643 spi_master_put(master
);
648 static int __devexit
mpc83xx_spi_remove(struct device
*dev
)
650 struct mpc83xx_spi
*mpc83xx_spi
;
651 struct spi_master
*master
;
653 master
= dev_get_drvdata(dev
);
654 mpc83xx_spi
= spi_master_get_devdata(master
);
656 flush_workqueue(mpc83xx_spi
->workqueue
);
657 destroy_workqueue(mpc83xx_spi
->workqueue
);
658 spi_unregister_master(master
);
660 free_irq(mpc83xx_spi
->irq
, mpc83xx_spi
);
661 iounmap(mpc83xx_spi
->base
);
666 struct mpc83xx_spi_probe_info
{
667 struct fsl_spi_platform_data pdata
;
672 static struct mpc83xx_spi_probe_info
*
673 to_of_pinfo(struct fsl_spi_platform_data
*pdata
)
675 return container_of(pdata
, struct mpc83xx_spi_probe_info
, pdata
);
678 static void mpc83xx_spi_cs_control(struct spi_device
*spi
, bool on
)
680 struct device
*dev
= spi
->dev
.parent
;
681 struct mpc83xx_spi_probe_info
*pinfo
= to_of_pinfo(dev
->platform_data
);
682 u16 cs
= spi
->chip_select
;
683 int gpio
= pinfo
->gpios
[cs
];
684 bool alow
= pinfo
->alow_flags
[cs
];
686 gpio_set_value(gpio
, on
^ alow
);
689 static int of_mpc83xx_spi_get_chipselects(struct device
*dev
)
691 struct device_node
*np
= dev_archdata_get_node(&dev
->archdata
);
692 struct fsl_spi_platform_data
*pdata
= dev
->platform_data
;
693 struct mpc83xx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
698 ngpios
= of_gpio_count(np
);
701 * SPI w/o chip-select line. One SPI device is still permitted
704 pdata
->max_chipselect
= 1;
708 pinfo
->gpios
= kmalloc(ngpios
* sizeof(*pinfo
->gpios
), GFP_KERNEL
);
711 memset(pinfo
->gpios
, -1, ngpios
* sizeof(*pinfo
->gpios
));
713 pinfo
->alow_flags
= kzalloc(ngpios
* sizeof(*pinfo
->alow_flags
),
715 if (!pinfo
->alow_flags
) {
717 goto err_alloc_flags
;
720 for (; i
< ngpios
; i
++) {
722 enum of_gpio_flags flags
;
724 gpio
= of_get_gpio_flags(np
, i
, &flags
);
725 if (!gpio_is_valid(gpio
)) {
726 dev_err(dev
, "invalid gpio #%d: %d\n", i
, gpio
);
730 ret
= gpio_request(gpio
, dev_name(dev
));
732 dev_err(dev
, "can't request gpio #%d: %d\n", i
, ret
);
736 pinfo
->gpios
[i
] = gpio
;
737 pinfo
->alow_flags
[i
] = flags
& OF_GPIO_ACTIVE_LOW
;
739 ret
= gpio_direction_output(pinfo
->gpios
[i
],
740 pinfo
->alow_flags
[i
]);
742 dev_err(dev
, "can't set output direction for gpio "
743 "#%d: %d\n", i
, ret
);
748 pdata
->max_chipselect
= ngpios
;
749 pdata
->cs_control
= mpc83xx_spi_cs_control
;
755 if (gpio_is_valid(pinfo
->gpios
[i
]))
756 gpio_free(pinfo
->gpios
[i
]);
760 kfree(pinfo
->alow_flags
);
761 pinfo
->alow_flags
= NULL
;
768 static int of_mpc83xx_spi_free_chipselects(struct device
*dev
)
770 struct fsl_spi_platform_data
*pdata
= dev
->platform_data
;
771 struct mpc83xx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
777 for (i
= 0; i
< pdata
->max_chipselect
; i
++) {
778 if (gpio_is_valid(pinfo
->gpios
[i
]))
779 gpio_free(pinfo
->gpios
[i
]);
783 kfree(pinfo
->alow_flags
);
787 static int __devinit
of_mpc83xx_spi_probe(struct of_device
*ofdev
,
788 const struct of_device_id
*ofid
)
790 struct device
*dev
= &ofdev
->dev
;
791 struct device_node
*np
= ofdev
->node
;
792 struct mpc83xx_spi_probe_info
*pinfo
;
793 struct fsl_spi_platform_data
*pdata
;
794 struct spi_master
*master
;
800 pinfo
= kzalloc(sizeof(*pinfo
), GFP_KERNEL
);
804 pdata
= &pinfo
->pdata
;
805 dev
->platform_data
= pdata
;
807 /* Allocate bus num dynamically. */
810 /* SPI controller is either clocked from QE or SoC clock. */
811 pdata
->sysclk
= get_brgfreq();
812 if (pdata
->sysclk
== -1) {
813 pdata
->sysclk
= fsl_get_sys_freq();
814 if (pdata
->sysclk
== -1) {
820 prop
= of_get_property(np
, "mode", NULL
);
821 if (prop
&& !strcmp(prop
, "cpu-qe"))
824 ret
= of_mpc83xx_spi_get_chipselects(dev
);
828 ret
= of_address_to_resource(np
, 0, &mem
);
832 ret
= of_irq_to_resource(np
, 0, &irq
);
838 master
= mpc83xx_spi_probe(dev
, &mem
, irq
.start
);
839 if (IS_ERR(master
)) {
840 ret
= PTR_ERR(master
);
844 of_register_spi_devices(master
, np
);
849 of_mpc83xx_spi_free_chipselects(dev
);
855 static int __devexit
of_mpc83xx_spi_remove(struct of_device
*ofdev
)
859 ret
= mpc83xx_spi_remove(&ofdev
->dev
);
862 of_mpc83xx_spi_free_chipselects(&ofdev
->dev
);
866 static const struct of_device_id of_mpc83xx_spi_match
[] = {
867 { .compatible
= "fsl,spi" },
870 MODULE_DEVICE_TABLE(of
, of_mpc83xx_spi_match
);
872 static struct of_platform_driver of_mpc83xx_spi_driver
= {
873 .name
= "mpc83xx_spi",
874 .match_table
= of_mpc83xx_spi_match
,
875 .probe
= of_mpc83xx_spi_probe
,
876 .remove
= __devexit_p(of_mpc83xx_spi_remove
),
879 #ifdef CONFIG_MPC832x_RDB
882 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
883 * only. The driver should go away soon, since newer MPC8323E-RDB's device
884 * tree can work with OpenFirmware driver. But for now we support old trees
887 static int __devinit
plat_mpc83xx_spi_probe(struct platform_device
*pdev
)
889 struct resource
*mem
;
891 struct spi_master
*master
;
893 if (!pdev
->dev
.platform_data
)
896 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
900 irq
= platform_get_irq(pdev
, 0);
904 master
= mpc83xx_spi_probe(&pdev
->dev
, mem
, irq
);
906 return PTR_ERR(master
);
910 static int __devexit
plat_mpc83xx_spi_remove(struct platform_device
*pdev
)
912 return mpc83xx_spi_remove(&pdev
->dev
);
915 MODULE_ALIAS("platform:mpc83xx_spi");
916 static struct platform_driver mpc83xx_spi_driver
= {
917 .probe
= plat_mpc83xx_spi_probe
,
918 .remove
= __exit_p(plat_mpc83xx_spi_remove
),
920 .name
= "mpc83xx_spi",
921 .owner
= THIS_MODULE
,
925 static bool legacy_driver_failed
;
927 static void __init
legacy_driver_register(void)
929 legacy_driver_failed
= platform_driver_register(&mpc83xx_spi_driver
);
932 static void __exit
legacy_driver_unregister(void)
934 if (legacy_driver_failed
)
936 platform_driver_unregister(&mpc83xx_spi_driver
);
939 static void __init
legacy_driver_register(void) {}
940 static void __exit
legacy_driver_unregister(void) {}
941 #endif /* CONFIG_MPC832x_RDB */
943 static int __init
mpc83xx_spi_init(void)
945 legacy_driver_register();
946 return of_register_platform_driver(&of_mpc83xx_spi_driver
);
949 static void __exit
mpc83xx_spi_exit(void)
951 of_unregister_platform_driver(&of_mpc83xx_spi_driver
);
952 legacy_driver_unregister();
955 module_init(mpc83xx_spi_init
);
956 module_exit(mpc83xx_spi_exit
);
958 MODULE_AUTHOR("Kumar Gala");
959 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
960 MODULE_LICENSE("GPL");