2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
45 #include <linux/cpufreq.h>
48 #include <asm/machvec.h>
50 #include <asm/meminit.h>
52 #include <asm/patch.h>
53 #include <asm/pgtable.h>
54 #include <asm/processor.h>
56 #include <asm/sections.h>
57 #include <asm/serial.h>
58 #include <asm/setup.h>
60 #include <asm/system.h>
61 #include <asm/unistd.h>
62 #include <asm/system.h>
64 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
65 # error "struct cpuinfo_ia64 too big!"
69 unsigned long __per_cpu_offset
[NR_CPUS
];
70 EXPORT_SYMBOL(__per_cpu_offset
);
73 extern void ia64_setup_printk_clock(void);
75 DEFINE_PER_CPU(struct cpuinfo_ia64
, cpu_info
);
76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset
);
77 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8
);
78 unsigned long ia64_cycles_per_usec
;
79 struct ia64_boot_param
*ia64_boot_param
;
80 struct screen_info screen_info
;
81 unsigned long vga_console_iobase
;
82 unsigned long vga_console_membase
;
84 static struct resource data_resource
= {
85 .name
= "Kernel data",
86 .flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
89 static struct resource code_resource
= {
90 .name
= "Kernel code",
91 .flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
93 extern void efi_initialize_iomem_resources(struct resource
*,
95 extern char _text
[], _end
[], _etext
[];
97 unsigned long ia64_max_cacheline_size
;
99 int dma_get_cache_alignment(void)
101 return ia64_max_cacheline_size
;
103 EXPORT_SYMBOL(dma_get_cache_alignment
);
105 unsigned long ia64_iobase
; /* virtual address for I/O accesses */
106 EXPORT_SYMBOL(ia64_iobase
);
107 struct io_space io_space
[MAX_IO_SPACES
];
108 EXPORT_SYMBOL(io_space
);
109 unsigned int num_io_spaces
;
112 * "flush_icache_range()" needs to know what processor dependent stride size to use
113 * when it makes i-cache(s) coherent with d-caches.
115 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
116 unsigned long ia64_i_cache_stride_shift
= ~0;
119 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
120 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
121 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
122 * address of the second buffer must be aligned to (merge_mask+1) in order to be
123 * mergeable). By default, we assume there is no I/O MMU which can merge physically
124 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
127 unsigned long ia64_max_iommu_merge_mask
= ~0UL;
128 EXPORT_SYMBOL(ia64_max_iommu_merge_mask
);
131 * We use a special marker for the end of memory and it uses the extra (+1) slot
133 struct rsvd_region rsvd_region
[IA64_MAX_RSVD_REGIONS
+ 1] __initdata
;
134 int num_rsvd_regions __initdata
;
138 * Filter incoming memory segments based on the primitive map created from the boot
139 * parameters. Segments contained in the map are removed from the memory ranges. A
140 * caller-specified function is called with the memory ranges that remain after filtering.
141 * This routine does not assume the incoming segments are sorted.
144 filter_rsvd_memory (unsigned long start
, unsigned long end
, void *arg
)
146 unsigned long range_start
, range_end
, prev_start
;
147 void (*func
)(unsigned long, unsigned long, int);
151 if (start
== PAGE_OFFSET
) {
152 printk(KERN_WARNING
"warning: skipping physical page 0\n");
154 if (start
>= end
) return 0;
158 * lowest possible address(walker uses virtual)
160 prev_start
= PAGE_OFFSET
;
163 for (i
= 0; i
< num_rsvd_regions
; ++i
) {
164 range_start
= max(start
, prev_start
);
165 range_end
= min(end
, rsvd_region
[i
].start
);
167 if (range_start
< range_end
)
168 call_pernode_memory(__pa(range_start
), range_end
- range_start
, func
);
170 /* nothing more available in this segment */
171 if (range_end
== end
) return 0;
173 prev_start
= rsvd_region
[i
].end
;
175 /* end of memory marker allows full processing inside loop body */
180 sort_regions (struct rsvd_region
*rsvd_region
, int max
)
184 /* simple bubble sorting */
186 for (j
= 0; j
< max
; ++j
) {
187 if (rsvd_region
[j
].start
> rsvd_region
[j
+1].start
) {
188 struct rsvd_region tmp
;
189 tmp
= rsvd_region
[j
];
190 rsvd_region
[j
] = rsvd_region
[j
+ 1];
191 rsvd_region
[j
+ 1] = tmp
;
198 * Request address space for all standard resources
200 static int __init
register_memory(void)
202 code_resource
.start
= ia64_tpa(_text
);
203 code_resource
.end
= ia64_tpa(_etext
) - 1;
204 data_resource
.start
= ia64_tpa(_etext
);
205 data_resource
.end
= ia64_tpa(_end
) - 1;
206 efi_initialize_iomem_resources(&code_resource
, &data_resource
);
211 __initcall(register_memory
);
214 * reserve_memory - setup reserved memory areas
216 * Setup the reserved memory areas set aside for the boot parameters,
217 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
218 * see include/asm-ia64/meminit.h if you need to define more.
221 reserve_memory (void)
226 * none of the entries in this table overlap
228 rsvd_region
[n
].start
= (unsigned long) ia64_boot_param
;
229 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ sizeof(*ia64_boot_param
);
232 rsvd_region
[n
].start
= (unsigned long) __va(ia64_boot_param
->efi_memmap
);
233 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ ia64_boot_param
->efi_memmap_size
;
236 rsvd_region
[n
].start
= (unsigned long) __va(ia64_boot_param
->command_line
);
237 rsvd_region
[n
].end
= (rsvd_region
[n
].start
238 + strlen(__va(ia64_boot_param
->command_line
)) + 1);
241 rsvd_region
[n
].start
= (unsigned long) ia64_imva((void *)KERNEL_START
);
242 rsvd_region
[n
].end
= (unsigned long) ia64_imva(_end
);
245 #ifdef CONFIG_BLK_DEV_INITRD
246 if (ia64_boot_param
->initrd_start
) {
247 rsvd_region
[n
].start
= (unsigned long)__va(ia64_boot_param
->initrd_start
);
248 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ ia64_boot_param
->initrd_size
;
253 efi_memmap_init(&rsvd_region
[n
].start
, &rsvd_region
[n
].end
);
256 /* end of memory marker */
257 rsvd_region
[n
].start
= ~0UL;
258 rsvd_region
[n
].end
= ~0UL;
261 num_rsvd_regions
= n
;
263 sort_regions(rsvd_region
, num_rsvd_regions
);
267 * find_initrd - get initrd parameters from the boot parameter structure
269 * Grab the initrd start and end from the boot parameter struct given us by
275 #ifdef CONFIG_BLK_DEV_INITRD
276 if (ia64_boot_param
->initrd_start
) {
277 initrd_start
= (unsigned long)__va(ia64_boot_param
->initrd_start
);
278 initrd_end
= initrd_start
+ia64_boot_param
->initrd_size
;
280 printk(KERN_INFO
"Initial ramdisk at: 0x%lx (%lu bytes)\n",
281 initrd_start
, ia64_boot_param
->initrd_size
);
289 unsigned long phys_iobase
;
292 * Set `iobase' based on the EFI memory map or, failing that, the
293 * value firmware left in ar.k0.
295 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
296 * the port's virtual address, so ia32_load_state() loads it with a
297 * user virtual address. But in ia64 mode, glibc uses the
298 * *physical* address in ar.k0 to mmap the appropriate area from
299 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
300 * cases, user-mode can only use the legacy 0-64K I/O port space.
302 * ar.k0 is not involved in kernel I/O port accesses, which can use
303 * any of the I/O port spaces and are done via MMIO using the
304 * virtual mmio_base from the appropriate io_space[].
306 phys_iobase
= efi_get_iobase();
308 phys_iobase
= ia64_get_kr(IA64_KR_IO_BASE
);
309 printk(KERN_INFO
"No I/O port range found in EFI memory map, "
310 "falling back to AR.KR0 (0x%lx)\n", phys_iobase
);
312 ia64_iobase
= (unsigned long) ioremap(phys_iobase
, 0);
313 ia64_set_kr(IA64_KR_IO_BASE
, __pa(ia64_iobase
));
315 /* setup legacy IO port space */
316 io_space
[0].mmio_base
= ia64_iobase
;
317 io_space
[0].sparse
= 1;
322 * early_console_setup - setup debugging console
324 * Consoles started here require little enough setup that we can start using
325 * them very early in the boot process, either right after the machine
326 * vector initialization, or even before if the drivers can detect their hw.
328 * Returns non-zero if a console couldn't be setup.
330 static inline int __init
331 early_console_setup (char *cmdline
)
335 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
337 extern int sn_serial_console_early_setup(void);
338 if (!sn_serial_console_early_setup())
342 #ifdef CONFIG_EFI_PCDP
343 if (!efi_setup_pcdp_console(cmdline
))
346 #ifdef CONFIG_SERIAL_8250_CONSOLE
347 if (!early_serial_console_init(cmdline
))
351 return (earlycons
) ? 0 : -1;
355 mark_bsp_online (void)
358 /* If we register an early console, allow CPU 0 to printk */
359 cpu_set(smp_processor_id(), cpu_online_map
);
365 check_for_logical_procs (void)
367 pal_logical_to_physical_t info
;
370 status
= ia64_pal_logical_to_phys(0, &info
);
372 printk(KERN_INFO
"No logical to physical processor mapping "
377 printk(KERN_ERR
"ia64_pal_logical_to_phys failed with %ld\n",
382 * Total number of siblings that BSP has. Though not all of them
383 * may have booted successfully. The correct number of siblings
384 * booted is in info.overview_num_log.
386 smp_num_siblings
= info
.overview_tpc
;
387 smp_num_cpucores
= info
.overview_cpp
;
391 static __initdata
int nomca
;
392 static __init
int setup_nomca(char *s
)
397 early_param("nomca", setup_nomca
);
400 setup_arch (char **cmdline_p
)
404 ia64_patch_vtop((u64
) __start___vtop_patchlist
, (u64
) __end___vtop_patchlist
);
406 *cmdline_p
= __va(ia64_boot_param
->command_line
);
407 strlcpy(saved_command_line
, *cmdline_p
, COMMAND_LINE_SIZE
);
414 #ifdef CONFIG_IA64_GENERIC
418 if (early_console_setup(*cmdline_p
) == 0)
422 /* Initialize the ACPI boot-time table parser */
424 # ifdef CONFIG_ACPI_NUMA
429 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
431 #endif /* CONFIG_APCI_BOOT */
435 /* process SAL system table: */
436 ia64_sal_init(efi
.sal_systab
);
438 ia64_setup_printk_clock();
441 cpu_physical_id(0) = hard_smp_processor_id();
443 cpu_set(0, cpu_sibling_map
[0]);
444 cpu_set(0, cpu_core_map
[0]);
446 check_for_logical_procs();
447 if (smp_num_cpucores
> 1)
449 "cpu package is Multi-Core capable: number of cores=%d\n",
451 if (smp_num_siblings
> 1)
453 "cpu package is Multi-Threading capable: number of siblings=%d\n",
457 cpu_init(); /* initialize the bootstrap CPU */
458 mmu_context_init(); /* initialize context_id bitmap */
466 # if defined(CONFIG_DUMMY_CONSOLE)
467 conswitchp
= &dummy_con
;
469 # if defined(CONFIG_VGA_CONSOLE)
471 * Non-legacy systems may route legacy VGA MMIO range to system
472 * memory. vga_con probes the MMIO hole, so memory looks like
473 * a VGA device to it. The EFI memory map can tell us if it's
474 * memory so we can avoid this problem.
476 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY
)
477 conswitchp
= &vga_con
;
482 /* enable IA-64 Machine Check Abort Handling unless disabled */
486 platform_setup(cmdline_p
);
491 * Display cpu info for all cpu's.
494 show_cpuinfo (struct seq_file
*m
, void *v
)
497 # define lpj c->loops_per_jiffy
498 # define cpunum c->cpu
500 # define lpj loops_per_jiffy
505 const char *feature_name
;
507 { 1UL << 0, "branchlong" },
508 { 1UL << 1, "spontaneous deferral"},
509 { 1UL << 2, "16-byte atomic ops" }
511 char family
[32], features
[128], *cp
, sep
;
512 struct cpuinfo_ia64
*c
= v
;
514 unsigned long proc_freq
;
520 case 0x07: memcpy(family
, "Itanium", 8); break;
521 case 0x1f: memcpy(family
, "Itanium 2", 10); break;
522 default: sprintf(family
, "%u", c
->family
); break;
525 /* build the feature string: */
526 memcpy(features
, " standard", 10);
529 for (i
= 0; i
< (int) ARRAY_SIZE(feature_bits
); ++i
) {
530 if (mask
& feature_bits
[i
].mask
) {
535 strcpy(cp
, feature_bits
[i
].feature_name
);
536 cp
+= strlen(feature_bits
[i
].feature_name
);
537 mask
&= ~feature_bits
[i
].mask
;
541 /* print unknown features as a hex value: */
544 sprintf(cp
, " 0x%lx", mask
);
547 proc_freq
= cpufreq_quick_get(cpunum
);
549 proc_freq
= c
->proc_freq
/ 1000;
559 "features :%s\n" /* don't change this---it _is_ right! */
562 "cpu MHz : %lu.%06lu\n"
563 "itc MHz : %lu.%06lu\n"
564 "BogoMIPS : %lu.%02lu\n",
565 cpunum
, c
->vendor
, family
, c
->model
, c
->revision
, c
->archrev
,
566 features
, c
->ppn
, c
->number
,
567 proc_freq
/ 1000, proc_freq
% 1000,
568 c
->itc_freq
/ 1000000, c
->itc_freq
% 1000000,
569 lpj
*HZ
/500000, (lpj
*HZ
/5000) % 100);
571 seq_printf(m
, "siblings : %u\n", cpus_weight(cpu_core_map
[cpunum
]));
572 if (c
->threads_per_core
> 1 || c
->cores_per_socket
> 1)
577 c
->socket_id
, c
->core_id
, c
->thread_id
);
585 c_start (struct seq_file
*m
, loff_t
*pos
)
588 while (*pos
< NR_CPUS
&& !cpu_isset(*pos
, cpu_online_map
))
591 return *pos
< NR_CPUS
? cpu_data(*pos
) : NULL
;
595 c_next (struct seq_file
*m
, void *v
, loff_t
*pos
)
598 return c_start(m
, pos
);
602 c_stop (struct seq_file
*m
, void *v
)
606 struct seq_operations cpuinfo_op
= {
613 static void __cpuinit
614 identify_cpu (struct cpuinfo_ia64
*c
)
617 unsigned long bits
[5];
623 u64 ppn
; /* processor serial number */
627 unsigned revision
: 8;
630 unsigned archrev
: 8;
631 unsigned reserved
: 24;
637 pal_vm_info_1_u_t vm1
;
638 pal_vm_info_2_u_t vm2
;
640 unsigned long impl_va_msb
= 50, phys_addr_size
= 44; /* Itanium defaults */
643 for (i
= 0; i
< 5; ++i
)
644 cpuid
.bits
[i
] = ia64_get_cpuid(i
);
646 memcpy(c
->vendor
, cpuid
.field
.vendor
, 16);
648 c
->cpu
= smp_processor_id();
650 /* below default values will be overwritten by identify_siblings()
651 * for Multi-Threading/Multi-Core capable cpu's
653 c
->threads_per_core
= c
->cores_per_socket
= c
->num_log
= 1;
656 identify_siblings(c
);
658 c
->ppn
= cpuid
.field
.ppn
;
659 c
->number
= cpuid
.field
.number
;
660 c
->revision
= cpuid
.field
.revision
;
661 c
->model
= cpuid
.field
.model
;
662 c
->family
= cpuid
.field
.family
;
663 c
->archrev
= cpuid
.field
.archrev
;
664 c
->features
= cpuid
.field
.features
;
666 status
= ia64_pal_vm_summary(&vm1
, &vm2
);
667 if (status
== PAL_STATUS_SUCCESS
) {
668 impl_va_msb
= vm2
.pal_vm_info_2_s
.impl_va_msb
;
669 phys_addr_size
= vm1
.pal_vm_info_1_s
.phys_add_size
;
671 c
->unimpl_va_mask
= ~((7L<<61) | ((1L << (impl_va_msb
+ 1)) - 1));
672 c
->unimpl_pa_mask
= ~((1L<<63) | ((1L << phys_addr_size
) - 1));
676 setup_per_cpu_areas (void)
678 /* start_kernel() requires this... */
679 #ifdef CONFIG_ACPI_HOTPLUG_CPU
680 prefill_possible_map();
685 * Calculate the max. cache line size.
687 * In addition, the minimum of the i-cache stride sizes is calculated for
688 * "flush_icache_range()".
690 static void __cpuinit
691 get_max_cacheline_size (void)
693 unsigned long line_size
, max
= 1;
694 unsigned int cache_size
= 0;
695 u64 l
, levels
, unique_caches
;
696 pal_cache_config_info_t cci
;
699 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
701 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed (status=%ld)\n",
702 __FUNCTION__
, status
);
703 max
= SMP_CACHE_BYTES
;
704 /* Safest setup for "flush_icache_range()" */
705 ia64_i_cache_stride_shift
= I_CACHE_STRIDE_SHIFT
;
709 for (l
= 0; l
< levels
; ++l
) {
710 status
= ia64_pal_cache_config_info(l
, /* cache_type (data_or_unified)= */ 2,
714 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
715 __FUNCTION__
, l
, status
);
716 max
= SMP_CACHE_BYTES
;
717 /* The safest setup for "flush_icache_range()" */
718 cci
.pcci_stride
= I_CACHE_STRIDE_SHIFT
;
719 cci
.pcci_unified
= 1;
721 line_size
= 1 << cci
.pcci_line_size
;
724 if (cache_size
< cci
.pcci_cache_size
)
725 cache_size
= cci
.pcci_cache_size
;
726 if (!cci
.pcci_unified
) {
727 status
= ia64_pal_cache_config_info(l
,
728 /* cache_type (instruction)= */ 1,
732 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
733 __FUNCTION__
, l
, status
);
734 /* The safest setup for "flush_icache_range()" */
735 cci
.pcci_stride
= I_CACHE_STRIDE_SHIFT
;
738 if (cci
.pcci_stride
< ia64_i_cache_stride_shift
)
739 ia64_i_cache_stride_shift
= cci
.pcci_stride
;
743 max_cache_size
= max(max_cache_size
, cache_size
);
745 if (max
> ia64_max_cacheline_size
)
746 ia64_max_cacheline_size
= max
;
750 * cpu_init() initializes state that is per-CPU. This function acts
751 * as a 'CPU state barrier', nothing should get across.
756 extern void __cpuinit
ia64_mmu_init (void *);
757 unsigned long num_phys_stacked
;
758 pal_vm_info_2_u_t vmi
;
759 unsigned int max_ctx
;
760 struct cpuinfo_ia64
*cpu_info
;
763 cpu_data
= per_cpu_init();
766 * We set ar.k3 so that assembly code in MCA handler can compute
767 * physical addresses of per cpu variables with a simple:
768 * phys = ar.k3 + &per_cpu_var
770 ia64_set_kr(IA64_KR_PER_CPU_DATA
,
771 ia64_tpa(cpu_data
) - (long) __per_cpu_start
);
773 get_max_cacheline_size();
776 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
777 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
778 * depends on the data returned by identify_cpu(). We break the dependency by
779 * accessing cpu_data() through the canonical per-CPU address.
781 cpu_info
= cpu_data
+ ((char *) &__ia64_per_cpu_var(cpu_info
) - __per_cpu_start
);
782 identify_cpu(cpu_info
);
784 #ifdef CONFIG_MCKINLEY
786 # define FEATURE_SET 16
787 struct ia64_pal_retval iprv
;
789 if (cpu_info
->family
== 0x1f) {
790 PAL_CALL_PHYS(iprv
, PAL_PROC_GET_FEATURES
, 0, FEATURE_SET
, 0);
791 if ((iprv
.status
== 0) && (iprv
.v0
& 0x80) && (iprv
.v2
& 0x80))
792 PAL_CALL_PHYS(iprv
, PAL_PROC_SET_FEATURES
,
793 (iprv
.v1
| 0x80), FEATURE_SET
, 0);
798 /* Clear the stack memory reserved for pt_regs: */
799 memset(task_pt_regs(current
), 0, sizeof(struct pt_regs
));
801 ia64_set_kr(IA64_KR_FPU_OWNER
, 0);
804 * Initialize the page-table base register to a global
805 * directory with all zeroes. This ensure that we can handle
806 * TLB-misses to user address-space even before we created the
807 * first user address-space. This may happen, e.g., due to
808 * aggressive use of lfetch.fault.
810 ia64_set_kr(IA64_KR_PT_BASE
, __pa(ia64_imva(empty_zero_page
)));
813 * Initialize default control register to defer speculative faults except
814 * for those arising from TLB misses, which are not deferred. The
815 * kernel MUST NOT depend on a particular setting of these bits (in other words,
816 * the kernel must have recovery code for all speculative accesses). Turn on
817 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
818 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
821 ia64_setreg(_IA64_REG_CR_DCR
, ( IA64_DCR_DP
| IA64_DCR_DK
| IA64_DCR_DX
| IA64_DCR_DR
822 | IA64_DCR_DA
| IA64_DCR_DD
| IA64_DCR_LC
));
823 atomic_inc(&init_mm
.mm_count
);
824 current
->active_mm
= &init_mm
;
828 ia64_mmu_init(ia64_imva(cpu_data
));
829 ia64_mca_cpu_init(ia64_imva(cpu_data
));
831 #ifdef CONFIG_IA32_SUPPORT
835 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
838 /* disable all local interrupt sources: */
839 ia64_set_itv(1 << 16);
840 ia64_set_lrr0(1 << 16);
841 ia64_set_lrr1(1 << 16);
842 ia64_setreg(_IA64_REG_CR_PMV
, 1 << 16);
843 ia64_setreg(_IA64_REG_CR_CMCV
, 1 << 16);
845 /* clear TPR & XTP to enable all interrupt classes: */
846 ia64_setreg(_IA64_REG_CR_TPR
, 0);
851 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
852 if (ia64_pal_vm_summary(NULL
, &vmi
) == 0)
853 max_ctx
= (1U << (vmi
.pal_vm_info_2_s
.rid_size
- 3)) - 1;
855 printk(KERN_WARNING
"cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
856 max_ctx
= (1U << 15) - 1; /* use architected minimum */
858 while (max_ctx
< ia64_ctx
.max_ctx
) {
859 unsigned int old
= ia64_ctx
.max_ctx
;
860 if (cmpxchg(&ia64_ctx
.max_ctx
, old
, max_ctx
) == old
)
864 if (ia64_pal_rse_info(&num_phys_stacked
, NULL
) != 0) {
865 printk(KERN_WARNING
"cpu_init: PAL RSE info failed; assuming 96 physical "
867 num_phys_stacked
= 96;
869 /* size of physical stacked register partition plus 8 bytes: */
870 __get_cpu_var(ia64_phys_stacked_size_p8
) = num_phys_stacked
*8 + 8;
872 pm_idle
= default_idle
;
876 * On SMP systems, when the scheduler does migration-cost autodetection,
877 * it needs a way to flush as much of the CPU's caches as possible.
879 void sched_cacheflush(void)
881 ia64_sal_cache_flush(3);
887 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles
,
888 (unsigned long) __end___mckinley_e9_bundles
);