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[IPX]: Fix build error in ipx_recvmsg()
[linux-2.6/verdex.git] / drivers / scsi / sata_promise.c
blob4d8201422a1232a3f0ff597f3bfb510c0ef221b1
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include "scsi.h"
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44 #include <asm/io.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "1.02"
49
50
51 enum {
52 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
53 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
54 PDC_TBG_MODE = 0x41, /* TBG mode */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_PCI_CTL = 0x48, /* PCI control and status register */
57 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
58 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
61
62 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
63 (1<<8) | (1<<9) | (1<<10),
64
65 board_2037x = 0, /* FastTrak S150 TX2plus */
66 board_20319 = 1, /* FastTrak S150 TX4 */
67 board_20619 = 2, /* FastTrak TX4000 */
68
69 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
70
71 PDC_RESET = (1 << 11), /* HDMA reset */
72 };
73
74
75 struct pdc_port_priv {
76 u8 *pkt;
77 dma_addr_t pkt_dma;
78 };
79
80 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
81 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
82 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
83 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
84 static void pdc_eng_timeout(struct ata_port *ap);
85 static int pdc_port_start(struct ata_port *ap);
86 static void pdc_port_stop(struct ata_port *ap);
87 static void pdc_phy_reset(struct ata_port *ap);
88 static void pdc_qc_prep(struct ata_queued_cmd *qc);
89 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
90 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
91 static void pdc_irq_clear(struct ata_port *ap);
92 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
93
94 static Scsi_Host_Template pdc_ata_sht = {
95 .module = THIS_MODULE,
96 .name = DRV_NAME,
97 .ioctl = ata_scsi_ioctl,
98 .queuecommand = ata_scsi_queuecmd,
99 .eh_strategy_handler = ata_scsi_error,
100 .can_queue = ATA_DEF_QUEUE,
101 .this_id = ATA_SHT_THIS_ID,
102 .sg_tablesize = LIBATA_MAX_PRD,
103 .max_sectors = ATA_MAX_SECTORS,
104 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
105 .emulated = ATA_SHT_EMULATED,
106 .use_clustering = ATA_SHT_USE_CLUSTERING,
107 .proc_name = DRV_NAME,
108 .dma_boundary = ATA_DMA_BOUNDARY,
109 .slave_configure = ata_scsi_slave_config,
110 .bios_param = ata_std_bios_param,
111 .ordered_flush = 1,
112 };
113
114 static struct ata_port_operations pdc_ata_ops = {
115 .port_disable = ata_port_disable,
116 .tf_load = pdc_tf_load_mmio,
117 .tf_read = ata_tf_read,
118 .check_status = ata_check_status,
119 .exec_command = pdc_exec_command_mmio,
120 .dev_select = ata_std_dev_select,
121 .phy_reset = pdc_phy_reset,
122 .qc_prep = pdc_qc_prep,
123 .qc_issue = pdc_qc_issue_prot,
124 .eng_timeout = pdc_eng_timeout,
125 .irq_handler = pdc_interrupt,
126 .irq_clear = pdc_irq_clear,
127 .scr_read = pdc_sata_scr_read,
128 .scr_write = pdc_sata_scr_write,
129 .port_start = pdc_port_start,
130 .port_stop = pdc_port_stop,
131 .host_stop = ata_host_stop,
132 };
133
134 static struct ata_port_info pdc_port_info[] = {
135 /* board_2037x */
136 {
137 .sht = &pdc_ata_sht,
138 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
139 ATA_FLAG_SRST | ATA_FLAG_MMIO,
140 .pio_mask = 0x1f, /* pio0-4 */
141 .mwdma_mask = 0x07, /* mwdma0-2 */
142 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
143 .port_ops = &pdc_ata_ops,
144 },
145
146 /* board_20319 */
147 {
148 .sht = &pdc_ata_sht,
149 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
150 ATA_FLAG_SRST | ATA_FLAG_MMIO,
151 .pio_mask = 0x1f, /* pio0-4 */
152 .mwdma_mask = 0x07, /* mwdma0-2 */
153 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
154 .port_ops = &pdc_ata_ops,
155 },
156
157 /* board_20619 */
158 {
159 .sht = &pdc_ata_sht,
160 .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
161 ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
162 .pio_mask = 0x1f, /* pio0-4 */
163 .mwdma_mask = 0x07, /* mwdma0-2 */
164 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
165 .port_ops = &pdc_ata_ops,
166 },
167 };
168
169 static struct pci_device_id pdc_ata_pci_tbl[] = {
170 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
171 board_2037x },
172 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
173 board_2037x },
174 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
175 board_2037x },
176 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
177 board_2037x },
178 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
179 board_2037x },
180 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
181 board_2037x },
182 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
183 board_2037x },
184
185 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
186 board_20319 },
187 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
188 board_20319 },
189 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
190 board_20319 },
191 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
192 board_20319 },
193 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
194 board_20319 },
195
196 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
197 board_20619 },
198
199 { } /* terminate list */
200 };
201
202
203 static struct pci_driver pdc_ata_pci_driver = {
204 .name = DRV_NAME,
205 .id_table = pdc_ata_pci_tbl,
206 .probe = pdc_ata_init_one,
207 .remove = ata_pci_remove_one,
208 };
209
210
211 static int pdc_port_start(struct ata_port *ap)
212 {
213 struct device *dev = ap->host_set->dev;
214 struct pdc_port_priv *pp;
215 int rc;
216
217 rc = ata_port_start(ap);
218 if (rc)
219 return rc;
220
221 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
222 if (!pp) {
223 rc = -ENOMEM;
224 goto err_out;
225 }
226 memset(pp, 0, sizeof(*pp));
227
228 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
229 if (!pp->pkt) {
230 rc = -ENOMEM;
231 goto err_out_kfree;
232 }
233
234 ap->private_data = pp;
235
236 return 0;
237
238 err_out_kfree:
239 kfree(pp);
240 err_out:
241 ata_port_stop(ap);
242 return rc;
243 }
244
245
246 static void pdc_port_stop(struct ata_port *ap)
247 {
248 struct device *dev = ap->host_set->dev;
249 struct pdc_port_priv *pp = ap->private_data;
250
251 ap->private_data = NULL;
252 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
253 kfree(pp);
254 ata_port_stop(ap);
255 }
256
257
258 static void pdc_reset_port(struct ata_port *ap)
259 {
260 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
261 unsigned int i;
262 u32 tmp;
263
264 for (i = 11; i > 0; i--) {
265 tmp = readl(mmio);
266 if (tmp & PDC_RESET)
267 break;
268
269 udelay(100);
270
271 tmp |= PDC_RESET;
272 writel(tmp, mmio);
273 }
274
275 tmp &= ~PDC_RESET;
276 writel(tmp, mmio);
277 readl(mmio); /* flush */
278 }
279
280 static void pdc_phy_reset(struct ata_port *ap)
281 {
282 pdc_reset_port(ap);
283 sata_phy_reset(ap);
284 }
285
286 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
287 {
288 if (sc_reg > SCR_CONTROL)
289 return 0xffffffffU;
290 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
291 }
292
293
294 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
295 u32 val)
296 {
297 if (sc_reg > SCR_CONTROL)
298 return;
299 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
300 }
301
302 static void pdc_qc_prep(struct ata_queued_cmd *qc)
303 {
304 struct pdc_port_priv *pp = qc->ap->private_data;
305 unsigned int i;
306
307 VPRINTK("ENTER\n");
308
309 switch (qc->tf.protocol) {
310 case ATA_PROT_DMA:
311 ata_qc_prep(qc);
312 /* fall through */
313
314 case ATA_PROT_NODATA:
315 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
316 qc->dev->devno, pp->pkt);
317
318 if (qc->tf.flags & ATA_TFLAG_LBA48)
319 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
320 else
321 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
322
323 pdc_pkt_footer(&qc->tf, pp->pkt, i);
324 break;
325
326 default:
327 break;
328 }
329 }
330
331 static void pdc_eng_timeout(struct ata_port *ap)
332 {
333 struct ata_host_set *host_set = ap->host_set;
334 u8 drv_stat;
335 struct ata_queued_cmd *qc;
336 unsigned long flags;
337
338 DPRINTK("ENTER\n");
339
340 spin_lock_irqsave(&host_set->lock, flags);
341
342 qc = ata_qc_from_tag(ap, ap->active_tag);
343 if (!qc) {
344 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
345 ap->id);
346 goto out;
347 }
348
349 /* hack alert! We cannot use the supplied completion
350 * function from inside the ->eh_strategy_handler() thread.
351 * libata is the only user of ->eh_strategy_handler() in
352 * any kernel, so the default scsi_done() assumes it is
353 * not being called from the SCSI EH.
354 */
355 qc->scsidone = scsi_finish_command;
356
357 switch (qc->tf.protocol) {
358 case ATA_PROT_DMA:
359 case ATA_PROT_NODATA:
360 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
361 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
362 break;
363
364 default:
365 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
366
367 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
368 ap->id, qc->tf.command, drv_stat);
369
370 ata_qc_complete(qc, drv_stat);
371 break;
372 }
373
374 out:
375 spin_unlock_irqrestore(&host_set->lock, flags);
376 DPRINTK("EXIT\n");
377 }
378
379 static inline unsigned int pdc_host_intr( struct ata_port *ap,
380 struct ata_queued_cmd *qc)
381 {
382 u8 status;
383 unsigned int handled = 0, have_err = 0;
384 u32 tmp;
385 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
386
387 tmp = readl(mmio);
388 if (tmp & PDC_ERR_MASK) {
389 have_err = 1;
390 pdc_reset_port(ap);
391 }
392
393 switch (qc->tf.protocol) {
394 case ATA_PROT_DMA:
395 case ATA_PROT_NODATA:
396 status = ata_wait_idle(ap);
397 if (have_err)
398 status |= ATA_ERR;
399 ata_qc_complete(qc, status);
400 handled = 1;
401 break;
402
403 default:
404 ap->stats.idle_irq++;
405 break;
406 }
407
408 return handled;
409 }
410
411 static void pdc_irq_clear(struct ata_port *ap)
412 {
413 struct ata_host_set *host_set = ap->host_set;
414 void *mmio = host_set->mmio_base;
415
416 readl(mmio + PDC_INT_SEQMASK);
417 }
418
419 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
420 {
421 struct ata_host_set *host_set = dev_instance;
422 struct ata_port *ap;
423 u32 mask = 0;
424 unsigned int i, tmp;
425 unsigned int handled = 0;
426 void *mmio_base;
427
428 VPRINTK("ENTER\n");
429
430 if (!host_set || !host_set->mmio_base) {
431 VPRINTK("QUICK EXIT\n");
432 return IRQ_NONE;
433 }
434
435 mmio_base = host_set->mmio_base;
436
437 /* reading should also clear interrupts */
438 mask = readl(mmio_base + PDC_INT_SEQMASK);
439
440 if (mask == 0xffffffff) {
441 VPRINTK("QUICK EXIT 2\n");
442 return IRQ_NONE;
443 }
444 mask &= 0xffff; /* only 16 tags possible */
445 if (!mask) {
446 VPRINTK("QUICK EXIT 3\n");
447 return IRQ_NONE;
448 }
449
450 spin_lock(&host_set->lock);
451
452 writel(mask, mmio_base + PDC_INT_SEQMASK);
453
454 for (i = 0; i < host_set->n_ports; i++) {
455 VPRINTK("port %u\n", i);
456 ap = host_set->ports[i];
457 tmp = mask & (1 << (i + 1));
458 if (tmp && ap &&
459 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
460 struct ata_queued_cmd *qc;
461
462 qc = ata_qc_from_tag(ap, ap->active_tag);
463 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
464 handled += pdc_host_intr(ap, qc);
465 }
466 }
467
468 spin_unlock(&host_set->lock);
469
470 VPRINTK("EXIT\n");
471
472 return IRQ_RETVAL(handled);
473 }
474
475 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
476 {
477 struct ata_port *ap = qc->ap;
478 struct pdc_port_priv *pp = ap->private_data;
479 unsigned int port_no = ap->port_no;
480 u8 seq = (u8) (port_no + 1);
481
482 VPRINTK("ENTER, ap %p\n", ap);
483
484 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
485 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
486
487 pp->pkt[2] = seq;
488 wmb(); /* flush PRD, pkt writes */
489 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
490 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
491 }
492
493 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
494 {
495 switch (qc->tf.protocol) {
496 case ATA_PROT_DMA:
497 case ATA_PROT_NODATA:
498 pdc_packet_start(qc);
499 return 0;
500
501 case ATA_PROT_ATAPI_DMA:
502 BUG();
503 break;
504
505 default:
506 break;
507 }
508
509 return ata_qc_issue_prot(qc);
510 }
511
512 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
513 {
514 WARN_ON (tf->protocol == ATA_PROT_DMA ||
515 tf->protocol == ATA_PROT_NODATA);
516 ata_tf_load(ap, tf);
517 }
518
519
520 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
521 {
522 WARN_ON (tf->protocol == ATA_PROT_DMA ||
523 tf->protocol == ATA_PROT_NODATA);
524 ata_exec_command(ap, tf);
525 }
526
527
528 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
529 {
530 port->cmd_addr = base;
531 port->data_addr = base;
532 port->feature_addr =
533 port->error_addr = base + 0x4;
534 port->nsect_addr = base + 0x8;
535 port->lbal_addr = base + 0xc;
536 port->lbam_addr = base + 0x10;
537 port->lbah_addr = base + 0x14;
538 port->device_addr = base + 0x18;
539 port->command_addr =
540 port->status_addr = base + 0x1c;
541 port->altstatus_addr =
542 port->ctl_addr = base + 0x38;
543 }
544
545
546 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
547 {
548 void *mmio = pe->mmio_base;
549 u32 tmp;
550
551 /*
552 * Except for the hotplug stuff, this is voodoo from the
553 * Promise driver. Label this entire section
554 * "TODO: figure out why we do this"
555 */
556
557 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
558 tmp = readl(mmio + PDC_FLASH_CTL);
559 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
560 writel(tmp, mmio + PDC_FLASH_CTL);
561
562 /* clear plug/unplug flags for all ports */
563 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
564 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
565
566 /* mask plug/unplug ints */
567 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
568 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
569
570 /* reduce TBG clock to 133 Mhz. */
571 tmp = readl(mmio + PDC_TBG_MODE);
572 tmp &= ~0x30000; /* clear bit 17, 16*/
573 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
574 writel(tmp, mmio + PDC_TBG_MODE);
575
576 readl(mmio + PDC_TBG_MODE); /* flush */
577 msleep(10);
578
579 /* adjust slew rate control register. */
580 tmp = readl(mmio + PDC_SLEW_CTL);
581 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
582 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
583 writel(tmp, mmio + PDC_SLEW_CTL);
584 }
585
586 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
587 {
588 static int printed_version;
589 struct ata_probe_ent *probe_ent = NULL;
590 unsigned long base;
591 void *mmio_base;
592 unsigned int board_idx = (unsigned int) ent->driver_data;
593 int pci_dev_busy = 0;
594 int rc;
595
596 if (!printed_version++)
597 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
598
599 /*
600 * If this driver happens to only be useful on Apple's K2, then
601 * we should check that here as it has a normal Serverworks ID
602 */
603 rc = pci_enable_device(pdev);
604 if (rc)
605 return rc;
606
607 rc = pci_request_regions(pdev, DRV_NAME);
608 if (rc) {
609 pci_dev_busy = 1;
610 goto err_out;
611 }
612
613 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
614 if (rc)
615 goto err_out_regions;
616 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
617 if (rc)
618 goto err_out_regions;
619
620 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
621 if (probe_ent == NULL) {
622 rc = -ENOMEM;
623 goto err_out_regions;
624 }
625
626 memset(probe_ent, 0, sizeof(*probe_ent));
627 probe_ent->dev = pci_dev_to_dev(pdev);
628 INIT_LIST_HEAD(&probe_ent->node);
629
630 mmio_base = ioremap(pci_resource_start(pdev, 3),
631 pci_resource_len(pdev, 3));
632 if (mmio_base == NULL) {
633 rc = -ENOMEM;
634 goto err_out_free_ent;
635 }
636 base = (unsigned long) mmio_base;
637
638 probe_ent->sht = pdc_port_info[board_idx].sht;
639 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
640 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
641 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
642 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
643 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
644
645 probe_ent->irq = pdev->irq;
646 probe_ent->irq_flags = SA_SHIRQ;
647 probe_ent->mmio_base = mmio_base;
648
649 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
650 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
651
652 probe_ent->port[0].scr_addr = base + 0x400;
653 probe_ent->port[1].scr_addr = base + 0x500;
654
655 /* notice 4-port boards */
656 switch (board_idx) {
657 case board_20319:
658 probe_ent->n_ports = 4;
659
660 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
661 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
662
663 probe_ent->port[2].scr_addr = base + 0x600;
664 probe_ent->port[3].scr_addr = base + 0x700;
665 break;
666 case board_2037x:
667 probe_ent->n_ports = 2;
668 break;
669 case board_20619:
670 probe_ent->n_ports = 4;
671
672 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
673 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
674
675 probe_ent->port[2].scr_addr = base + 0x600;
676 probe_ent->port[3].scr_addr = base + 0x700;
677 break;
678 default:
679 BUG();
680 break;
681 }
682
683 pci_set_master(pdev);
684
685 /* initialize adapter */
686 pdc_host_init(board_idx, probe_ent);
687
688 /* FIXME: check ata_device_add return value */
689 ata_device_add(probe_ent);
690 kfree(probe_ent);
691
692 return 0;
693
694 err_out_free_ent:
695 kfree(probe_ent);
696 err_out_regions:
697 pci_release_regions(pdev);
698 err_out:
699 if (!pci_dev_busy)
700 pci_disable_device(pdev);
701 return rc;
702 }
703
704
705 static int __init pdc_ata_init(void)
706 {
707 return pci_module_init(&pdc_ata_pci_driver);
708 }
709
710
711 static void __exit pdc_ata_exit(void)
712 {
713 pci_unregister_driver(&pdc_ata_pci_driver);
714 }
715
716
717 MODULE_AUTHOR("Jeff Garzik");
718 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
719 MODULE_LICENSE("GPL");
720 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
721 MODULE_VERSION(DRV_VERSION);
722
723 module_init(pdc_ata_init);
724 module_exit(pdc_ata_exit);
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