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[PATCH] dm: fix mapped device ref counting
[linux-2.6/verdex.git] / include / asm-x86_64 / system.h
blobf48e0dad8b3d3c5503a827a4bc3b5b8a73b0885f
1 #ifndef __ASM_SYSTEM_H
2 #define __ASM_SYSTEM_H
3
4 #include <linux/kernel.h>
5 #include <asm/segment.h>
6
7 #ifdef __KERNEL__
8
9 #ifdef CONFIG_SMP
10 #define LOCK_PREFIX "lock ; "
11 #else
12 #define LOCK_PREFIX ""
13 #endif
14
15 #define __STR(x) #x
16 #define STR(x) __STR(x)
17
18 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
19 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
20
21 /* frame pointer must be last for get_wchan */
22 #define SAVE_CONTEXT "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
23 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\n\t"
24
25 #define __EXTRA_CLOBBER \
26 ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
27
28 #define switch_to(prev,next,last) \
29 asm volatile(SAVE_CONTEXT \
30 "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
31 "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
32 "call __switch_to\n\t" \
33 ".globl thread_return\n" \
34 "thread_return:\n\t" \
35 "movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \
36 "movq %P[thread_info](%%rsi),%%r8\n\t" \
37 LOCK "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \
38 "movq %%rax,%%rdi\n\t" \
39 "jc ret_from_fork\n\t" \
40 RESTORE_CONTEXT \
41 : "=a" (last) \
42 : [next] "S" (next), [prev] "D" (prev), \
43 [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
44 [ti_flags] "i" (offsetof(struct thread_info, flags)),\
45 [tif_fork] "i" (TIF_FORK), \
46 [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
47 [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
48 : "memory", "cc" __EXTRA_CLOBBER)
49
50 extern void load_gs_index(unsigned);
51
52 /*
53 * Load a segment. Fall back on loading the zero
54 * segment if something goes wrong..
55 */
56 #define loadsegment(seg,value) \
57 asm volatile("\n" \
58 "1:\t" \
59 "movl %k0,%%" #seg "\n" \
60 "2:\n" \
61 ".section .fixup,\"ax\"\n" \
62 "3:\t" \
63 "movl %1,%%" #seg "\n\t" \
64 "jmp 2b\n" \
65 ".previous\n" \
66 ".section __ex_table,\"a\"\n\t" \
67 ".align 8\n\t" \
68 ".quad 1b,3b\n" \
69 ".previous" \
70 : :"r" (value), "r" (0))
71
72 #ifdef __KERNEL__
73 struct alt_instr {
74 __u8 *instr; /* original instruction */
75 __u8 *replacement;
76 __u8 cpuid; /* cpuid bit set for replacement */
77 __u8 instrlen; /* length of original instruction */
78 __u8 replacementlen; /* length of new instruction, <= instrlen */
79 __u8 pad[5];
80 };
81 #endif
82
83 /*
84 * Alternative instructions for different CPU types or capabilities.
85 *
86 * This allows to use optimized instructions even on generic binary
87 * kernels.
88 *
89 * length of oldinstr must be longer or equal the length of newinstr
90 * It can be padded with nops as needed.
91 *
92 * For non barrier like inlines please define new variants
93 * without volatile and memory clobber.
94 */
95 #define alternative(oldinstr, newinstr, feature) \
96 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
97 ".section .altinstructions,\"a\"\n" \
98 " .align 8\n" \
99 " .quad 661b\n" /* label */ \
100 " .quad 663f\n" /* new instruction */ \
101 " .byte %c0\n" /* feature bit */ \
102 " .byte 662b-661b\n" /* sourcelen */ \
103 " .byte 664f-663f\n" /* replacementlen */ \
104 ".previous\n" \
105 ".section .altinstr_replacement,\"ax\"\n" \
106 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
107 ".previous" :: "i" (feature) : "memory")
108
109 /*
110 * Alternative inline assembly with input.
111 *
112 * Peculiarities:
113 * No memory clobber here.
114 * Argument numbers start with 1.
115 * Best is to use constraints that are fixed size (like (%1) ... "r")
116 * If you use variable sized constraints like "m" or "g" in the
117 * replacement make sure to pad to the worst case length.
118 */
119 #define alternative_input(oldinstr, newinstr, feature, input...) \
120 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
121 ".section .altinstructions,\"a\"\n" \
122 " .align 8\n" \
123 " .quad 661b\n" /* label */ \
124 " .quad 663f\n" /* new instruction */ \
125 " .byte %c0\n" /* feature bit */ \
126 " .byte 662b-661b\n" /* sourcelen */ \
127 " .byte 664f-663f\n" /* replacementlen */ \
128 ".previous\n" \
129 ".section .altinstr_replacement,\"ax\"\n" \
130 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
131 ".previous" :: "i" (feature), ##input)
132
133 /* Like alternative_input, but with a single output argument */
134 #define alternative_io(oldinstr, newinstr, feature, output, input...) \
135 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
136 ".section .altinstructions,\"a\"\n" \
137 " .align 8\n" \
138 " .quad 661b\n" /* label */ \
139 " .quad 663f\n" /* new instruction */ \
140 " .byte %c[feat]\n" /* feature bit */ \
141 " .byte 662b-661b\n" /* sourcelen */ \
142 " .byte 664f-663f\n" /* replacementlen */ \
143 ".previous\n" \
144 ".section .altinstr_replacement,\"ax\"\n" \
145 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
146 ".previous" : output : [feat] "i" (feature), ##input)
147
148 /*
149 * Clear and set 'TS' bit respectively
150 */
151 #define clts() __asm__ __volatile__ ("clts")
152
153 static inline unsigned long read_cr0(void)
154 {
155 unsigned long cr0;
156 asm volatile("movq %%cr0,%0" : "=r" (cr0));
157 return cr0;
158 }
159
160 static inline void write_cr0(unsigned long val)
161 {
162 asm volatile("movq %0,%%cr0" :: "r" (val));
163 }
164
165 static inline unsigned long read_cr3(void)
166 {
167 unsigned long cr3;
168 asm("movq %%cr3,%0" : "=r" (cr3));
169 return cr3;
170 }
171
172 static inline unsigned long read_cr4(void)
173 {
174 unsigned long cr4;
175 asm("movq %%cr4,%0" : "=r" (cr4));
176 return cr4;
177 }
178
179 static inline void write_cr4(unsigned long val)
180 {
181 asm volatile("movq %0,%%cr4" :: "r" (val));
182 }
183
184 #define stts() write_cr0(8 | read_cr0())
185
186 #define wbinvd() \
187 __asm__ __volatile__ ("wbinvd": : :"memory");
188
189 /*
190 * On SMP systems, when the scheduler does migration-cost autodetection,
191 * it needs a way to flush as much of the CPU's caches as possible.
192 */
193 static inline void sched_cacheflush(void)
194 {
195 wbinvd();
196 }
197
198 #endif /* __KERNEL__ */
199
200 #define nop() __asm__ __volatile__ ("nop")
201
202 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
203
204 #define tas(ptr) (xchg((ptr),1))
205
206 #define __xg(x) ((volatile long *)(x))
207
208 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
209 {
210 *ptr = val;
211 }
212
213 #define _set_64bit set_64bit
214
215 /*
216 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
217 * Note 2: xchg has side effect, so that attribute volatile is necessary,
218 * but generally the primitive is invalid, *ptr is output argument. --ANK
219 */
220 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
221 {
222 switch (size) {
223 case 1:
224 __asm__ __volatile__("xchgb %b0,%1"
225 :"=q" (x)
226 :"m" (*__xg(ptr)), "0" (x)
227 :"memory");
228 break;
229 case 2:
230 __asm__ __volatile__("xchgw %w0,%1"
231 :"=r" (x)
232 :"m" (*__xg(ptr)), "0" (x)
233 :"memory");
234 break;
235 case 4:
236 __asm__ __volatile__("xchgl %k0,%1"
237 :"=r" (x)
238 :"m" (*__xg(ptr)), "0" (x)
239 :"memory");
240 break;
241 case 8:
242 __asm__ __volatile__("xchgq %0,%1"
243 :"=r" (x)
244 :"m" (*__xg(ptr)), "0" (x)
245 :"memory");
246 break;
247 }
248 return x;
249 }
250
251 /*
252 * Atomic compare and exchange. Compare OLD with MEM, if identical,
253 * store NEW in MEM. Return the initial value in MEM. Success is
254 * indicated by comparing RETURN with OLD.
255 */
256
257 #define __HAVE_ARCH_CMPXCHG 1
258
259 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
260 unsigned long new, int size)
261 {
262 unsigned long prev;
263 switch (size) {
264 case 1:
265 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
266 : "=a"(prev)
267 : "q"(new), "m"(*__xg(ptr)), "0"(old)
268 : "memory");
269 return prev;
270 case 2:
271 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
272 : "=a"(prev)
273 : "r"(new), "m"(*__xg(ptr)), "0"(old)
274 : "memory");
275 return prev;
276 case 4:
277 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
278 : "=a"(prev)
279 : "r"(new), "m"(*__xg(ptr)), "0"(old)
280 : "memory");
281 return prev;
282 case 8:
283 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
284 : "=a"(prev)
285 : "r"(new), "m"(*__xg(ptr)), "0"(old)
286 : "memory");
287 return prev;
288 }
289 return old;
290 }
291
292 #define cmpxchg(ptr,o,n)\
293 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
294 (unsigned long)(n),sizeof(*(ptr))))
295
296 #ifdef CONFIG_SMP
297 #define smp_mb() mb()
298 #define smp_rmb() rmb()
299 #define smp_wmb() wmb()
300 #define smp_read_barrier_depends() do {} while(0)
301 #else
302 #define smp_mb() barrier()
303 #define smp_rmb() barrier()
304 #define smp_wmb() barrier()
305 #define smp_read_barrier_depends() do {} while(0)
306 #endif
307
308
309 /*
310 * Force strict CPU ordering.
311 * And yes, this is required on UP too when we're talking
312 * to devices.
313 */
314 #define mb() asm volatile("mfence":::"memory")
315 #define rmb() asm volatile("lfence":::"memory")
316
317 #ifdef CONFIG_UNORDERED_IO
318 #define wmb() asm volatile("sfence" ::: "memory")
319 #else
320 #define wmb() asm volatile("" ::: "memory")
321 #endif
322 #define read_barrier_depends() do {} while(0)
323 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
324 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
325
326 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
327
328 /* interrupt control.. */
329 #define local_save_flags(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# save_flags \n\t pushfq ; popq %q0":"=g" (x): /* no input */ :"memory"); } while (0)
330 #define local_irq_restore(x) __asm__ __volatile__("# restore_flags \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory", "cc")
331
332 #ifdef CONFIG_X86_VSMP
333 /* Interrupt control for VSMP architecture */
334 #define local_irq_disable() do { unsigned long flags; local_save_flags(flags); local_irq_restore((flags & ~(1 << 9)) | (1 << 18)); } while (0)
335 #define local_irq_enable() do { unsigned long flags; local_save_flags(flags); local_irq_restore((flags | (1 << 9)) & ~(1 << 18)); } while (0)
336
337 #define irqs_disabled() \
338 ({ \
339 unsigned long flags; \
340 local_save_flags(flags); \
341 (flags & (1<<18)) || !(flags & (1<<9)); \
342 })
343
344 /* For spinlocks etc */
345 #define local_irq_save(x) do { local_save_flags(x); local_irq_restore((x & ~(1 << 9)) | (1 << 18)); } while (0)
346 #else /* CONFIG_X86_VSMP */
347 #define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
348 #define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
349
350 #define irqs_disabled() \
351 ({ \
352 unsigned long flags; \
353 local_save_flags(flags); \
354 !(flags & (1<<9)); \
355 })
356
357 /* For spinlocks etc */
358 #define local_irq_save(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
359 #endif
360
361 /* used in the idle loop; sti takes one instruction cycle to complete */
362 #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
363 /* used when interrupts are already enabled or to shutdown the processor */
364 #define halt() __asm__ __volatile__("hlt": : :"memory")
365
366 void cpu_idle_wait(void);
367
368 extern unsigned long arch_align_stack(unsigned long sp);
369
370 #endif
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