include/asm-arm/arch-s3c2410/regs-irq.h

   1 /* linux/include/asm/arch-s3c2410/regs-irq.h
   2  *
   3  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *
  11  *
  12  *  Changelog:
  13  *    19-06-2003     BJD     Created file
  14  *    12-03-2004     BJD     Updated include protection
  15  *    10-03-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA
  16  */
  17
  18
  19 #ifndef ___ASM_ARCH_REGS_IRQ_H
  20 #define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
  21
  22 /* interrupt controller */
  23
  24 #define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
  25 #define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
  26
  27 #define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
  28 #define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
  29 #define S3C2410_INTMSK         S3C2410_IRQREG(0x008)
  30 #define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
  31 #define S3C2410_INTPND         S3C2410_IRQREG(0x010)
  32 #define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
  33 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
  34 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
  35
  36 /* mask: 0=enable, 1=disable
  37  * 1 bit EINT, 4=EINT4, 23=EINT23
  38  * EINT0,1,2,3 are not handled here.
  39 */
  40
  41 #define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
  42 #define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
  43
  44 #endif /* ___ASM_ARCH_REGS_IRQ_H */