[PATCH] w1: hotplug support.
[linux-2.6/verdex.git] / include / asm-ppc / mv64x60.h
blob835930d6faa1bf54c2a4c71d5138a03730610183
1 /*
2 * include/asm-ppc/mv64x60.h
4 * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
13 #ifndef __ASMPPC_MV64x60_H
14 #define __ASMPPC_MV64x60_H
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/config.h>
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24 #include <asm/irq.h>
25 #include <asm/uaccess.h>
26 #include <asm/machdep.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/mv64x60_defs.h>
30 extern u8 mv64x60_pci_exclude_bridge;
32 extern spinlock_t mv64x60_lock;
34 /* 32-bit Window table entry defines */
35 #define MV64x60_CPU2MEM_0_WIN 0
36 #define MV64x60_CPU2MEM_1_WIN 1
37 #define MV64x60_CPU2MEM_2_WIN 2
38 #define MV64x60_CPU2MEM_3_WIN 3
39 #define MV64x60_CPU2DEV_0_WIN 4
40 #define MV64x60_CPU2DEV_1_WIN 5
41 #define MV64x60_CPU2DEV_2_WIN 6
42 #define MV64x60_CPU2DEV_3_WIN 7
43 #define MV64x60_CPU2BOOT_WIN 8
44 #define MV64x60_CPU2PCI0_IO_WIN 9
45 #define MV64x60_CPU2PCI0_MEM_0_WIN 10
46 #define MV64x60_CPU2PCI0_MEM_1_WIN 11
47 #define MV64x60_CPU2PCI0_MEM_2_WIN 12
48 #define MV64x60_CPU2PCI0_MEM_3_WIN 13
49 #define MV64x60_CPU2PCI1_IO_WIN 14
50 #define MV64x60_CPU2PCI1_MEM_0_WIN 15
51 #define MV64x60_CPU2PCI1_MEM_1_WIN 16
52 #define MV64x60_CPU2PCI1_MEM_2_WIN 17
53 #define MV64x60_CPU2PCI1_MEM_3_WIN 18
54 #define MV64x60_CPU2SRAM_WIN 19
55 #define MV64x60_CPU2PCI0_IO_REMAP_WIN 20
56 #define MV64x60_CPU2PCI1_IO_REMAP_WIN 21
57 #define MV64x60_CPU_PROT_0_WIN 22
58 #define MV64x60_CPU_PROT_1_WIN 23
59 #define MV64x60_CPU_PROT_2_WIN 24
60 #define MV64x60_CPU_PROT_3_WIN 25
61 #define MV64x60_CPU_SNOOP_0_WIN 26
62 #define MV64x60_CPU_SNOOP_1_WIN 27
63 #define MV64x60_CPU_SNOOP_2_WIN 28
64 #define MV64x60_CPU_SNOOP_3_WIN 29
65 #define MV64x60_PCI02MEM_REMAP_0_WIN 30
66 #define MV64x60_PCI02MEM_REMAP_1_WIN 31
67 #define MV64x60_PCI02MEM_REMAP_2_WIN 32
68 #define MV64x60_PCI02MEM_REMAP_3_WIN 33
69 #define MV64x60_PCI12MEM_REMAP_0_WIN 34
70 #define MV64x60_PCI12MEM_REMAP_1_WIN 35
71 #define MV64x60_PCI12MEM_REMAP_2_WIN 36
72 #define MV64x60_PCI12MEM_REMAP_3_WIN 37
73 #define MV64x60_ENET2MEM_0_WIN 38
74 #define MV64x60_ENET2MEM_1_WIN 39
75 #define MV64x60_ENET2MEM_2_WIN 40
76 #define MV64x60_ENET2MEM_3_WIN 41
77 #define MV64x60_ENET2MEM_4_WIN 42
78 #define MV64x60_ENET2MEM_5_WIN 43
79 #define MV64x60_MPSC2MEM_0_WIN 44
80 #define MV64x60_MPSC2MEM_1_WIN 45
81 #define MV64x60_MPSC2MEM_2_WIN 46
82 #define MV64x60_MPSC2MEM_3_WIN 47
83 #define MV64x60_IDMA2MEM_0_WIN 48
84 #define MV64x60_IDMA2MEM_1_WIN 49
85 #define MV64x60_IDMA2MEM_2_WIN 50
86 #define MV64x60_IDMA2MEM_3_WIN 51
87 #define MV64x60_IDMA2MEM_4_WIN 52
88 #define MV64x60_IDMA2MEM_5_WIN 53
89 #define MV64x60_IDMA2MEM_6_WIN 54
90 #define MV64x60_IDMA2MEM_7_WIN 55
92 #define MV64x60_32BIT_WIN_COUNT 56
94 /* 64-bit Window table entry defines */
95 #define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0
96 #define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1
97 #define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2
98 #define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3
99 #define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4
100 #define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5
101 #define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6
102 #define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7
103 #define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8
104 #define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9
105 #define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10
106 #define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11
107 #define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12
108 #define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13
109 #define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14
110 #define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15
111 #define MV64x60_PCI02MEM_SNOOP_0_WIN 16
112 #define MV64x60_PCI02MEM_SNOOP_1_WIN 17
113 #define MV64x60_PCI02MEM_SNOOP_2_WIN 18
114 #define MV64x60_PCI02MEM_SNOOP_3_WIN 19
115 #define MV64x60_PCI12MEM_SNOOP_0_WIN 20
116 #define MV64x60_PCI12MEM_SNOOP_1_WIN 21
117 #define MV64x60_PCI12MEM_SNOOP_2_WIN 22
118 #define MV64x60_PCI12MEM_SNOOP_3_WIN 23
120 #define MV64x60_64BIT_WIN_COUNT 24
123 * Define a structure that's used to pass in config information to the
124 * core routines.
126 struct mv64x60_pci_window {
127 u32 cpu_base;
128 u32 pci_base_hi;
129 u32 pci_base_lo;
130 u32 size;
131 u32 swap;
134 struct mv64x60_pci_info {
135 u8 enable_bus; /* allow access to this PCI bus? */
137 struct mv64x60_pci_window pci_io;
138 struct mv64x60_pci_window pci_mem[3];
140 u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
141 u32 snoop_options[MV64x60_CPU2MEM_WINDOWS];
142 u16 pci_cmd_bits;
143 u16 latency_timer;
146 struct mv64x60_setup_info {
147 u32 phys_reg_base;
148 u32 window_preserve_mask_32_hi;
149 u32 window_preserve_mask_32_lo;
150 u32 window_preserve_mask_64;
152 u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
153 u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
154 u32 enet_options[MV64x60_CPU2MEM_WINDOWS];
155 u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS];
156 u32 idma_options[MV64x60_CPU2MEM_WINDOWS];
158 struct mv64x60_pci_info pci_0;
159 struct mv64x60_pci_info pci_1;
162 /* Define what the top bits in the extra member of a window entry means. */
163 #define MV64x60_EXTRA_INVALID 0x00000000
164 #define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000
165 #define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000
166 #define MV64x60_EXTRA_ENET_ENAB 0x30000000
167 #define MV64x60_EXTRA_MPSC_ENAB 0x40000000
168 #define MV64x60_EXTRA_IDMA_ENAB 0x50000000
169 #define MV64x60_EXTRA_PCIACC_ENAB 0x60000000
171 #define MV64x60_EXTRA_MASK 0xf0000000
174 * Define the 'handle' struct that will be passed between the 64x60 core
175 * code and the platform-specific code that will use it. The handle
176 * will contain pointers to chip-specific routines & information.
178 struct mv64x60_32bit_window {
179 u32 base_reg;
180 u32 size_reg;
181 u8 base_bits;
182 u8 size_bits;
183 u32 (*get_from_field)(u32 val, u32 num_bits);
184 u32 (*map_to_field)(u32 val, u32 num_bits);
185 u32 extra;
188 struct mv64x60_64bit_window {
189 u32 base_hi_reg;
190 u32 base_lo_reg;
191 u32 size_reg;
192 u8 base_lo_bits;
193 u8 size_bits;
194 u32 (*get_from_field)(u32 val, u32 num_bits);
195 u32 (*map_to_field)(u32 val, u32 num_bits);
196 u32 extra;
199 typedef struct mv64x60_handle mv64x60_handle_t;
200 struct mv64x60_chip_info {
201 u32 (*translate_size)(u32 base, u32 size, u32 num_bits);
202 u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits);
203 void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
204 u32 window, u32 base);
205 void (*set_pci2regs_window)(struct mv64x60_handle *bh,
206 struct pci_controller *hose, u32 bus, u32 base);
207 u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
208 void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
209 void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
210 void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
211 void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
212 void (*disable_all_windows)(mv64x60_handle_t *bh,
213 struct mv64x60_setup_info *si);
214 void (*config_io2mem_windows)(mv64x60_handle_t *bh,
215 struct mv64x60_setup_info *si,
216 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
217 void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
218 void (*chip_specific_init)(mv64x60_handle_t *bh,
219 struct mv64x60_setup_info *si);
221 struct mv64x60_32bit_window *window_tab_32bit;
222 struct mv64x60_64bit_window *window_tab_64bit;
225 struct mv64x60_handle {
226 u32 type; /* type of bridge */
227 u32 rev; /* revision of bridge */
228 void *v_base; /* virtual base addr of bridge regs */
229 phys_addr_t p_base; /* physical base addr of bridge regs */
231 u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/
232 u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/
234 u32 io_base_a; /* vaddr of pci 0's I/O space */
235 u32 io_base_b; /* vaddr of pci 1's I/O space */
237 struct pci_controller *hose_a;
238 struct pci_controller *hose_b;
240 struct mv64x60_chip_info *ci; /* chip/bridge-specific info */
244 /* Define I/O routines for accessing registers on the 64x60 bridge. */
245 extern inline void
246 mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
247 ulong flags;
249 spin_lock_irqsave(&mv64x60_lock, flags);
250 out_le32(bh->v_base + offset, val);
251 spin_unlock_irqrestore(&mv64x60_lock, flags);
254 extern inline u32
255 mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
256 ulong flags;
257 u32 reg;
259 spin_lock_irqsave(&mv64x60_lock, flags);
260 reg = in_le32(bh->v_base + offset);
261 spin_unlock_irqrestore(&mv64x60_lock, flags);
262 return reg;
265 extern inline void
266 mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
268 u32 reg;
269 ulong flags;
271 spin_lock_irqsave(&mv64x60_lock, flags);
272 reg = in_le32(bh->v_base + offs) & (~mask);
273 reg |= data & mask;
274 out_le32(bh->v_base + offs, reg);
275 spin_unlock_irqrestore(&mv64x60_lock, flags);
278 #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
279 #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
281 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
282 #define MV64XXX_DEV_NAME "mv64xxx"
284 struct mv64xxx_pdata {
285 u32 hs_reg_valid;
287 #endif
289 /* Externally visible function prototypes */
290 int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
291 u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
292 void mv64x60_early_init(struct mv64x60_handle *bh,
293 struct mv64x60_setup_info *si);
294 void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
295 u32 cfg_data, struct pci_controller **hose);
296 int mv64x60_get_type(struct mv64x60_handle *bh);
297 int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
298 void *mv64x60_get_bridge_vbase(void);
299 u32 mv64x60_get_bridge_type(void);
300 u32 mv64x60_get_bridge_rev(void);
301 void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
302 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
303 void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
304 struct mv64x60_setup_info *si,
305 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
306 void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
307 struct mv64x60_pci_info *pi, u32 bus);
308 void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
309 struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
310 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
311 void mv64x60_config_resources(struct pci_controller *hose,
312 struct mv64x60_pci_info *pi, u32 io_base);
313 void mv64x60_config_pci_params(struct pci_controller *hose,
314 struct mv64x60_pci_info *pi);
315 void mv64x60_pd_fixup(struct mv64x60_handle *bh,
316 struct platform_device *pd_devs[], u32 entries);
317 void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
318 u32 *base, u32 *size);
319 void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
320 u32 size, u32 other_bits);
321 void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
322 u32 *base_hi, u32 *base_lo, u32 *size);
323 void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
324 u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
325 void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
326 int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
329 void gt64260_init_irq(void);
330 int gt64260_get_irq(struct pt_regs *regs);
331 void mv64360_init_irq(void);
332 int mv64360_get_irq(struct pt_regs *regs);
334 u32 mv64x60_mask(u32 val, u32 num_bits);
335 u32 mv64x60_shift_left(u32 val, u32 num_bits);
336 u32 mv64x60_shift_right(u32 val, u32 num_bits);
337 u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
338 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
340 void mv64x60_progress_init(u32 base);
341 void mv64x60_mpsc_progress(char *s, unsigned short hex);
343 extern struct mv64x60_32bit_window
344 gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
345 extern struct mv64x60_64bit_window
346 gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
347 extern struct mv64x60_32bit_window
348 mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
349 extern struct mv64x60_64bit_window
350 mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
352 #endif /* __ASMPPC_MV64x60_H */