[PATCH] w1: hotplug support.
[linux-2.6/verdex.git] / include / asm-x86_64 / apicdef.h
blob9388062c4f6e52fd409ef099395ca55be862c21d
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0xFFu)
16 #define APIC_LVR 0x30
17 #define APIC_LVR_MASK 0xFF00FF
18 #define GET_APIC_VERSION(x) ((x)&0xFFu)
19 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
20 #define APIC_INTEGRATED(x) ((x)&0xF0u)
21 #define APIC_TASKPRI 0x80
22 #define APIC_TPRI_MASK 0xFFu
23 #define APIC_ARBPRI 0x90
24 #define APIC_ARBPRI_MASK 0xFFu
25 #define APIC_PROCPRI 0xA0
26 #define APIC_EOI 0xB0
27 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
28 #define APIC_RRR 0xC0
29 #define APIC_LDR 0xD0
30 #define APIC_LDR_MASK (0xFFu<<24)
31 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
32 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
33 #define APIC_ALL_CPUS 0xFFu
34 #define APIC_DFR 0xE0
35 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
36 #define APIC_DFR_FLAT 0xFFFFFFFFul
37 #define APIC_SPIV 0xF0
38 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
39 #define APIC_SPIV_APIC_ENABLED (1<<8)
40 #define APIC_ISR 0x100
41 #define APIC_TMR 0x180
42 #define APIC_IRR 0x200
43 #define APIC_ESR 0x280
44 #define APIC_ESR_SEND_CS 0x00001
45 #define APIC_ESR_RECV_CS 0x00002
46 #define APIC_ESR_SEND_ACC 0x00004
47 #define APIC_ESR_RECV_ACC 0x00008
48 #define APIC_ESR_SENDILL 0x00020
49 #define APIC_ESR_RECVILL 0x00040
50 #define APIC_ESR_ILLREGA 0x00080
51 #define APIC_ICR 0x300
52 #define APIC_DEST_SELF 0x40000
53 #define APIC_DEST_ALLINC 0x80000
54 #define APIC_DEST_ALLBUT 0xC0000
55 #define APIC_ICR_RR_MASK 0x30000
56 #define APIC_ICR_RR_INVALID 0x00000
57 #define APIC_ICR_RR_INPROG 0x10000
58 #define APIC_ICR_RR_VALID 0x20000
59 #define APIC_INT_LEVELTRIG 0x08000
60 #define APIC_INT_ASSERT 0x04000
61 #define APIC_ICR_BUSY 0x01000
62 #define APIC_DEST_LOGICAL 0x00800
63 #define APIC_DEST_PHYSICAL 0x00000
64 #define APIC_DM_FIXED 0x00000
65 #define APIC_DM_LOWEST 0x00100
66 #define APIC_DM_SMI 0x00200
67 #define APIC_DM_REMRD 0x00300
68 #define APIC_DM_NMI 0x00400
69 #define APIC_DM_INIT 0x00500
70 #define APIC_DM_STARTUP 0x00600
71 #define APIC_DM_EXTINT 0x00700
72 #define APIC_VECTOR_MASK 0x000FF
73 #define APIC_ICR2 0x310
74 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
75 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
76 #define APIC_LVTT 0x320
77 #define APIC_LVTTHMR 0x330
78 #define APIC_LVTPC 0x340
79 #define APIC_LVT0 0x350
80 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
81 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
82 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
83 #define APIC_TIMER_BASE_CLKIN 0x0
84 #define APIC_TIMER_BASE_TMBASE 0x1
85 #define APIC_TIMER_BASE_DIV 0x2
86 #define APIC_LVT_TIMER_PERIODIC (1<<17)
87 #define APIC_LVT_MASKED (1<<16)
88 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
89 #define APIC_LVT_REMOTE_IRR (1<<14)
90 #define APIC_INPUT_POLARITY (1<<13)
91 #define APIC_SEND_PENDING (1<<12)
92 #define APIC_MODE_MASK 0x700
93 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
94 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
95 #define APIC_MODE_FIXED 0x0
96 #define APIC_MODE_NMI 0x4
97 #define APIC_MODE_EXTINT 0x7
98 #define APIC_LVT1 0x360
99 #define APIC_LVTERR 0x370
100 #define APIC_TMICT 0x380
101 #define APIC_TMCCT 0x390
102 #define APIC_TDCR 0x3E0
103 #define APIC_TDR_DIV_TMBASE (1<<2)
104 #define APIC_TDR_DIV_1 0xB
105 #define APIC_TDR_DIV_2 0x0
106 #define APIC_TDR_DIV_4 0x1
107 #define APIC_TDR_DIV_8 0x2
108 #define APIC_TDR_DIV_16 0x3
109 #define APIC_TDR_DIV_32 0x8
110 #define APIC_TDR_DIV_64 0x9
111 #define APIC_TDR_DIV_128 0xA
113 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
115 #define MAX_IO_APICS 128
118 * All x86-64 systems are xAPIC compatible.
119 * In the following, "apicid" is a physical APIC ID.
121 #define XAPIC_DEST_CPUS_SHIFT 4
122 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
123 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
124 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
125 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
126 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
127 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
130 * the local APIC register structure, memory mapped. Not terribly well
131 * tested, but we might eventually use this one in the future - the
132 * problem why we cannot use it right now is the P5 APIC, it has an
133 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
135 #define u32 unsigned int
137 #define lapic ((volatile struct local_apic *)APIC_BASE)
139 struct local_apic {
141 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
143 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
145 /*020*/ struct { /* APIC ID Register */
146 u32 __reserved_1 : 24,
147 phys_apic_id : 4,
148 __reserved_2 : 4;
149 u32 __reserved[3];
150 } id;
152 /*030*/ const
153 struct { /* APIC Version Register */
154 u32 version : 8,
155 __reserved_1 : 8,
156 max_lvt : 8,
157 __reserved_2 : 8;
158 u32 __reserved[3];
159 } version;
161 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
163 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
165 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
167 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
169 /*080*/ struct { /* Task Priority Register */
170 u32 priority : 8,
171 __reserved_1 : 24;
172 u32 __reserved_2[3];
173 } tpr;
175 /*090*/ const
176 struct { /* Arbitration Priority Register */
177 u32 priority : 8,
178 __reserved_1 : 24;
179 u32 __reserved_2[3];
180 } apr;
182 /*0A0*/ const
183 struct { /* Processor Priority Register */
184 u32 priority : 8,
185 __reserved_1 : 24;
186 u32 __reserved_2[3];
187 } ppr;
189 /*0B0*/ struct { /* End Of Interrupt Register */
190 u32 eoi;
191 u32 __reserved[3];
192 } eoi;
194 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
196 /*0D0*/ struct { /* Logical Destination Register */
197 u32 __reserved_1 : 24,
198 logical_dest : 8;
199 u32 __reserved_2[3];
200 } ldr;
202 /*0E0*/ struct { /* Destination Format Register */
203 u32 __reserved_1 : 28,
204 model : 4;
205 u32 __reserved_2[3];
206 } dfr;
208 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
209 u32 spurious_vector : 8,
210 apic_enabled : 1,
211 focus_cpu : 1,
212 __reserved_2 : 22;
213 u32 __reserved_3[3];
214 } svr;
216 /*100*/ struct { /* In Service Register */
217 /*170*/ u32 bitfield;
218 u32 __reserved[3];
219 } isr [8];
221 /*180*/ struct { /* Trigger Mode Register */
222 /*1F0*/ u32 bitfield;
223 u32 __reserved[3];
224 } tmr [8];
226 /*200*/ struct { /* Interrupt Request Register */
227 /*270*/ u32 bitfield;
228 u32 __reserved[3];
229 } irr [8];
231 /*280*/ union { /* Error Status Register */
232 struct {
233 u32 send_cs_error : 1,
234 receive_cs_error : 1,
235 send_accept_error : 1,
236 receive_accept_error : 1,
237 __reserved_1 : 1,
238 send_illegal_vector : 1,
239 receive_illegal_vector : 1,
240 illegal_register_address : 1,
241 __reserved_2 : 24;
242 u32 __reserved_3[3];
243 } error_bits;
244 struct {
245 u32 errors;
246 u32 __reserved_3[3];
247 } all_errors;
248 } esr;
250 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
252 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
254 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
256 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
258 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
260 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
262 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
264 /*300*/ struct { /* Interrupt Command Register 1 */
265 u32 vector : 8,
266 delivery_mode : 3,
267 destination_mode : 1,
268 delivery_status : 1,
269 __reserved_1 : 1,
270 level : 1,
271 trigger : 1,
272 __reserved_2 : 2,
273 shorthand : 2,
274 __reserved_3 : 12;
275 u32 __reserved_4[3];
276 } icr1;
278 /*310*/ struct { /* Interrupt Command Register 2 */
279 union {
280 u32 __reserved_1 : 24,
281 phys_dest : 4,
282 __reserved_2 : 4;
283 u32 __reserved_3 : 24,
284 logical_dest : 8;
285 } dest;
286 u32 __reserved_4[3];
287 } icr2;
289 /*320*/ struct { /* LVT - Timer */
290 u32 vector : 8,
291 __reserved_1 : 4,
292 delivery_status : 1,
293 __reserved_2 : 3,
294 mask : 1,
295 timer_mode : 1,
296 __reserved_3 : 14;
297 u32 __reserved_4[3];
298 } lvt_timer;
300 /*330*/ struct { /* LVT - Thermal Sensor */
301 u32 vector : 8,
302 delivery_mode : 3,
303 __reserved_1 : 1,
304 delivery_status : 1,
305 __reserved_2 : 3,
306 mask : 1,
307 __reserved_3 : 15;
308 u32 __reserved_4[3];
309 } lvt_thermal;
311 /*340*/ struct { /* LVT - Performance Counter */
312 u32 vector : 8,
313 delivery_mode : 3,
314 __reserved_1 : 1,
315 delivery_status : 1,
316 __reserved_2 : 3,
317 mask : 1,
318 __reserved_3 : 15;
319 u32 __reserved_4[3];
320 } lvt_pc;
322 /*350*/ struct { /* LVT - LINT0 */
323 u32 vector : 8,
324 delivery_mode : 3,
325 __reserved_1 : 1,
326 delivery_status : 1,
327 polarity : 1,
328 remote_irr : 1,
329 trigger : 1,
330 mask : 1,
331 __reserved_2 : 15;
332 u32 __reserved_3[3];
333 } lvt_lint0;
335 /*360*/ struct { /* LVT - LINT1 */
336 u32 vector : 8,
337 delivery_mode : 3,
338 __reserved_1 : 1,
339 delivery_status : 1,
340 polarity : 1,
341 remote_irr : 1,
342 trigger : 1,
343 mask : 1,
344 __reserved_2 : 15;
345 u32 __reserved_3[3];
346 } lvt_lint1;
348 /*370*/ struct { /* LVT - Error */
349 u32 vector : 8,
350 __reserved_1 : 4,
351 delivery_status : 1,
352 __reserved_2 : 3,
353 mask : 1,
354 __reserved_3 : 15;
355 u32 __reserved_4[3];
356 } lvt_error;
358 /*380*/ struct { /* Timer Initial Count Register */
359 u32 initial_count;
360 u32 __reserved_2[3];
361 } timer_icr;
363 /*390*/ const
364 struct { /* Timer Current Count Register */
365 u32 curr_count;
366 u32 __reserved_2[3];
367 } timer_ccr;
369 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
371 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
373 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
375 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
377 /*3E0*/ struct { /* Timer Divide Configuration Register */
378 u32 divisor : 4,
379 __reserved_1 : 28;
380 u32 __reserved_2[3];
381 } timer_dcr;
383 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
385 } __attribute__ ((packed));
387 #undef u32
389 #define BAD_APICID 0xFFu
391 #endif