2 * File: arch/blackfin/mach-common/ints-priority.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
67 unsigned long irq_flags
= 0x1f;
69 /* The number of spurious interrupts */
70 atomic_t num_spurious
;
73 unsigned long bfin_sic_iwr
[3]; /* Up to 3 SIC_IWRx registers */
78 /* irq number for request_irq, available in mach-bf5xx/irq.h */
80 /* corresponding bit in the SIC_ISR register */
82 } ivg_table
[NR_PERI_INTS
];
85 /* position of first irq in ivg_table for given ivg */
88 } ivg7_13
[IVG13
- IVG7
+ 1];
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
95 static void __init
search_IAR(void)
97 unsigned ivg
, irq_pos
= 0;
98 for (ivg
= 0; ivg
<= IVG13
- IVG7
; ivg
++) {
101 ivg7_13
[ivg
].istop
= ivg7_13
[ivg
].ifirst
= &ivg_table
[irq_pos
];
103 for (irqn
= 0; irqn
< NR_PERI_INTS
; irqn
++) {
104 int iar_shift
= (irqn
& 7) * 4;
107 bfin_read32((unsigned long *)SIC_IAR0
+
108 (irqn
>> 3)) >> iar_shift
)) {
110 bfin_read32((unsigned long *)SIC_IAR0
+
111 ((irqn
%32) >> 3) + ((irqn
/ 32) * 16)) >> iar_shift
)) {
113 ivg_table
[irq_pos
].irqno
= IVG7
+ irqn
;
114 ivg_table
[irq_pos
].isrflag
= 1 << (irqn
% 32);
115 ivg7_13
[ivg
].istop
++;
123 * This is for core internal IRQs
126 static void bfin_ack_noop(unsigned int irq
)
128 /* Dummy function. */
131 static void bfin_core_mask_irq(unsigned int irq
)
133 irq_flags
&= ~(1 << irq
);
134 if (!irqs_disabled())
138 static void bfin_core_unmask_irq(unsigned int irq
)
140 irq_flags
|= 1 << irq
;
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
150 if (!irqs_disabled())
155 static void bfin_internal_mask_irq(unsigned int irq
)
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << SIC_SYSIRQ(irq
)));
161 unsigned mask_bank
, mask_bit
;
162 mask_bank
= SIC_SYSIRQ(irq
) / 32;
163 mask_bit
= SIC_SYSIRQ(irq
) % 32;
164 bfin_write_SIC_IMASK(mask_bank
, bfin_read_SIC_IMASK(mask_bank
) &
170 static void bfin_internal_unmask_irq(unsigned int irq
)
173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << SIC_SYSIRQ(irq
)));
176 unsigned mask_bank
, mask_bit
;
177 mask_bank
= SIC_SYSIRQ(irq
) / 32;
178 mask_bit
= SIC_SYSIRQ(irq
) % 32;
179 bfin_write_SIC_IMASK(mask_bank
, bfin_read_SIC_IMASK(mask_bank
) |
186 int bfin_internal_set_wake(unsigned int irq
, unsigned int state
)
188 unsigned bank
, bit
, wakeup
= 0;
190 bank
= SIC_SYSIRQ(irq
) / 32;
191 bit
= SIC_SYSIRQ(irq
) % 32;
228 local_irq_save(flags
);
231 bfin_sic_iwr
[bank
] |= (1 << bit
);
235 bfin_sic_iwr
[bank
] &= ~(1 << bit
);
236 vr_wakeup
&= ~wakeup
;
239 local_irq_restore(flags
);
245 static struct irq_chip bfin_core_irqchip
= {
247 .ack
= bfin_ack_noop
,
248 .mask
= bfin_core_mask_irq
,
249 .unmask
= bfin_core_unmask_irq
,
252 static struct irq_chip bfin_internal_irqchip
= {
254 .ack
= bfin_ack_noop
,
255 .mask
= bfin_internal_mask_irq
,
256 .unmask
= bfin_internal_unmask_irq
,
257 .mask_ack
= bfin_internal_mask_irq
,
258 .disable
= bfin_internal_mask_irq
,
259 .enable
= bfin_internal_unmask_irq
,
261 .set_wake
= bfin_internal_set_wake
,
265 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
266 static int error_int_mask
;
268 static void bfin_generic_error_mask_irq(unsigned int irq
)
270 error_int_mask
&= ~(1L << (irq
- IRQ_PPI_ERROR
));
273 bfin_internal_mask_irq(IRQ_GENERIC_ERROR
);
276 static void bfin_generic_error_unmask_irq(unsigned int irq
)
278 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR
);
279 error_int_mask
|= 1L << (irq
- IRQ_PPI_ERROR
);
282 static struct irq_chip bfin_generic_error_irqchip
= {
284 .ack
= bfin_ack_noop
,
285 .mask_ack
= bfin_generic_error_mask_irq
,
286 .mask
= bfin_generic_error_mask_irq
,
287 .unmask
= bfin_generic_error_unmask_irq
,
290 static void bfin_demux_error_irq(unsigned int int_err_irq
,
291 struct irq_desc
*inta_desc
)
297 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
298 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK
)
302 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK
)
303 irq
= IRQ_SPORT0_ERROR
;
304 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK
)
305 irq
= IRQ_SPORT1_ERROR
;
306 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK
)
308 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK
)
310 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK
)
312 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1
) &&
313 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0
))
314 irq
= IRQ_UART0_ERROR
;
315 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1
) &&
316 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0
))
317 irq
= IRQ_UART1_ERROR
;
320 if (error_int_mask
& (1L << (irq
- IRQ_PPI_ERROR
))) {
321 struct irq_desc
*desc
= irq_desc
+ irq
;
322 desc
->handle_irq(irq
, desc
);
327 bfin_write_PPI_STATUS(PPI_ERR_MASK
);
329 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
331 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK
);
334 case IRQ_SPORT0_ERROR
:
335 bfin_write_SPORT0_STAT(SPORT_ERR_MASK
);
338 case IRQ_SPORT1_ERROR
:
339 bfin_write_SPORT1_STAT(SPORT_ERR_MASK
);
343 bfin_write_CAN_GIS(CAN_ERR_MASK
);
347 bfin_write_SPI_STAT(SPI_ERR_MASK
);
355 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
360 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
361 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
362 __func__
, __FILE__
, __LINE__
);
365 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
367 static inline void bfin_set_irq_handler(unsigned irq
, irq_flow_handler_t handle
)
369 struct irq_desc
*desc
= irq_desc
+ irq
;
370 /* May not call generic set_irq_handler() due to spinlock
372 desc
->handle_irq
= handle
;
375 #if !defined(CONFIG_BF54x)
377 static unsigned short gpio_enabled
[gpio_bank(MAX_BLACKFIN_GPIOS
)];
378 static unsigned short gpio_edge_triggered
[gpio_bank(MAX_BLACKFIN_GPIOS
)];
380 extern void bfin_gpio_irq_prepare(unsigned gpio
);
382 static void bfin_gpio_ack_irq(unsigned int irq
)
384 u16 gpionr
= irq
- IRQ_PF0
;
386 if (gpio_edge_triggered
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)) {
387 set_gpio_data(gpionr
, 0);
392 static void bfin_gpio_mask_ack_irq(unsigned int irq
)
394 u16 gpionr
= irq
- IRQ_PF0
;
396 if (gpio_edge_triggered
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)) {
397 set_gpio_data(gpionr
, 0);
401 set_gpio_maska(gpionr
, 0);
405 static void bfin_gpio_mask_irq(unsigned int irq
)
407 set_gpio_maska(irq
- IRQ_PF0
, 0);
411 static void bfin_gpio_unmask_irq(unsigned int irq
)
413 set_gpio_maska(irq
- IRQ_PF0
, 1);
417 static unsigned int bfin_gpio_irq_startup(unsigned int irq
)
419 u16 gpionr
= irq
- IRQ_PF0
;
421 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)))
422 bfin_gpio_irq_prepare(gpionr
);
424 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
425 bfin_gpio_unmask_irq(irq
);
430 static void bfin_gpio_irq_shutdown(unsigned int irq
)
432 bfin_gpio_mask_irq(irq
);
433 gpio_enabled
[gpio_bank(irq
- IRQ_PF0
)] &= ~gpio_bit(irq
- IRQ_PF0
);
436 static int bfin_gpio_irq_type(unsigned int irq
, unsigned int type
)
438 u16 gpionr
= irq
- IRQ_PF0
;
440 if (type
== IRQ_TYPE_PROBE
) {
441 /* only probe unenabled GPIO interrupt lines */
442 if (gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
))
444 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
447 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
448 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
449 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)))
450 bfin_gpio_irq_prepare(gpionr
);
452 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
454 gpio_enabled
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
458 set_gpio_inen(gpionr
, 0);
459 set_gpio_dir(gpionr
, 0);
461 if ((type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
462 == (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
463 set_gpio_both(gpionr
, 1);
465 set_gpio_both(gpionr
, 0);
467 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
468 set_gpio_polar(gpionr
, 1); /* low or falling edge denoted by one */
470 set_gpio_polar(gpionr
, 0); /* high or rising edge denoted by zero */
472 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
473 set_gpio_edge(gpionr
, 1);
474 set_gpio_inen(gpionr
, 1);
475 gpio_edge_triggered
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
476 set_gpio_data(gpionr
, 0);
479 set_gpio_edge(gpionr
, 0);
480 gpio_edge_triggered
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
481 set_gpio_inen(gpionr
, 1);
486 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
487 bfin_set_irq_handler(irq
, handle_edge_irq
);
489 bfin_set_irq_handler(irq
, handle_level_irq
);
495 int bfin_gpio_set_wake(unsigned int irq
, unsigned int state
)
497 unsigned gpio
= irq_to_gpio(irq
);
500 gpio_pm_wakeup_request(gpio
, PM_WAKE_IGNORE
);
502 gpio_pm_wakeup_free(gpio
);
508 static struct irq_chip bfin_gpio_irqchip
= {
510 .ack
= bfin_gpio_ack_irq
,
511 .mask
= bfin_gpio_mask_irq
,
512 .mask_ack
= bfin_gpio_mask_ack_irq
,
513 .unmask
= bfin_gpio_unmask_irq
,
514 .disable
= bfin_gpio_mask_irq
,
515 .enable
= bfin_gpio_unmask_irq
,
516 .set_type
= bfin_gpio_irq_type
,
517 .startup
= bfin_gpio_irq_startup
,
518 .shutdown
= bfin_gpio_irq_shutdown
,
520 .set_wake
= bfin_gpio_set_wake
,
524 static void bfin_demux_gpio_irq(unsigned int inta_irq
,
525 struct irq_desc
*desc
)
527 unsigned int i
, gpio
, mask
, irq
, search
= 0;
530 #if defined(CONFIG_BF53x)
535 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
540 #elif defined(CONFIG_BF52x)
550 #elif defined(CONFIG_BF561)
567 for (i
= 0; i
< MAX_BLACKFIN_GPIOS
; i
+= GPIO_BANKSIZE
) {
570 mask
= get_gpiop_data(i
) &
571 (gpio_enabled
[gpio_bank(i
)] &
576 desc
= irq_desc
+ irq
;
577 desc
->handle_irq(irq
, desc
);
584 gpio
= irq_to_gpio(irq
);
585 mask
= get_gpiop_data(gpio
) &
586 (gpio_enabled
[gpio_bank(gpio
)] &
587 get_gpiop_maska(gpio
));
591 desc
= irq_desc
+ irq
;
592 desc
->handle_irq(irq
, desc
);
601 #else /* CONFIG_BF54x */
603 #define NR_PINT_SYS_IRQS 4
604 #define NR_PINT_BITS 32
606 #define IRQ_NOT_AVAIL 0xFF
608 #define PINT_2_BANK(x) ((x) >> 5)
609 #define PINT_2_BIT(x) ((x) & 0x1F)
610 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
612 static unsigned char irq2pint_lut
[NR_PINTS
];
613 static unsigned char pint2irq_lut
[NR_PINT_SYS_IRQS
* NR_PINT_BITS
];
615 static unsigned int gpio_both_edge_triggered
[NR_PINT_SYS_IRQS
];
616 static unsigned short gpio_enabled
[gpio_bank(MAX_BLACKFIN_GPIOS
)];
620 unsigned int mask_set
;
621 unsigned int mask_clear
;
622 unsigned int request
;
624 unsigned int edge_set
;
625 unsigned int edge_clear
;
626 unsigned int invert_set
;
627 unsigned int invert_clear
;
628 unsigned int pinstate
;
632 static struct pin_int_t
*pint
[NR_PINT_SYS_IRQS
] = {
633 (struct pin_int_t
*)PINT0_MASK_SET
,
634 (struct pin_int_t
*)PINT1_MASK_SET
,
635 (struct pin_int_t
*)PINT2_MASK_SET
,
636 (struct pin_int_t
*)PINT3_MASK_SET
,
639 extern void bfin_gpio_irq_prepare(unsigned gpio
);
641 inline unsigned short get_irq_base(u8 bank
, u8 bmap
)
646 if (bank
< 2) { /*PA-PB */
647 irq_base
= IRQ_PA0
+ bmap
* 16;
649 irq_base
= IRQ_PC0
+ bmap
* 16;
656 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
657 void init_pint_lut(void)
659 u16 bank
, bit
, irq_base
, bit_pos
;
663 memset(irq2pint_lut
, IRQ_NOT_AVAIL
, sizeof(irq2pint_lut
));
665 for (bank
= 0; bank
< NR_PINT_SYS_IRQS
; bank
++) {
667 pint_assign
= pint
[bank
]->assign
;
669 for (bit
= 0; bit
< NR_PINT_BITS
; bit
++) {
671 bmap
= (pint_assign
>> ((bit
/ 8) * 8)) & 0xFF;
673 irq_base
= get_irq_base(bank
, bmap
);
675 irq_base
+= (bit
% 8) + ((bit
/ 8) & 1 ? 8 : 0);
676 bit_pos
= bit
+ bank
* NR_PINT_BITS
;
678 pint2irq_lut
[bit_pos
] = irq_base
- SYS_IRQS
;
679 irq2pint_lut
[irq_base
- SYS_IRQS
] = bit_pos
;
687 static void bfin_gpio_ack_irq(unsigned int irq
)
689 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
690 u32 pintbit
= PINT_BIT(pint_val
);
691 u8 bank
= PINT_2_BANK(pint_val
);
693 if (unlikely(gpio_both_edge_triggered
[bank
] & pintbit
)) {
694 if (pint
[bank
]->invert_set
& pintbit
)
695 pint
[bank
]->invert_clear
= pintbit
;
697 pint
[bank
]->invert_set
= pintbit
;
699 pint
[bank
]->request
= pintbit
;
704 static void bfin_gpio_mask_ack_irq(unsigned int irq
)
706 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
707 u32 pintbit
= PINT_BIT(pint_val
);
708 u8 bank
= PINT_2_BANK(pint_val
);
710 if (unlikely(gpio_both_edge_triggered
[bank
] & pintbit
)) {
711 if (pint
[bank
]->invert_set
& pintbit
)
712 pint
[bank
]->invert_clear
= pintbit
;
714 pint
[bank
]->invert_set
= pintbit
;
717 pint
[bank
]->request
= pintbit
;
718 pint
[bank
]->mask_clear
= pintbit
;
722 static void bfin_gpio_mask_irq(unsigned int irq
)
724 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
726 pint
[PINT_2_BANK(pint_val
)]->mask_clear
= PINT_BIT(pint_val
);
730 static void bfin_gpio_unmask_irq(unsigned int irq
)
732 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
733 u32 pintbit
= PINT_BIT(pint_val
);
734 u8 bank
= PINT_2_BANK(pint_val
);
736 pint
[bank
]->request
= pintbit
;
737 pint
[bank
]->mask_set
= pintbit
;
741 static unsigned int bfin_gpio_irq_startup(unsigned int irq
)
743 u16 gpionr
= irq_to_gpio(irq
);
744 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
746 if (pint_val
== IRQ_NOT_AVAIL
) {
748 "GPIO IRQ %d :Not in PINT Assign table "
749 "Reconfigure Interrupt to Port Assignemt\n", irq
);
753 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)))
754 bfin_gpio_irq_prepare(gpionr
);
756 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
757 bfin_gpio_unmask_irq(irq
);
762 static void bfin_gpio_irq_shutdown(unsigned int irq
)
764 u16 gpionr
= irq_to_gpio(irq
);
766 bfin_gpio_mask_irq(irq
);
767 gpio_enabled
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
770 static int bfin_gpio_irq_type(unsigned int irq
, unsigned int type
)
773 u16 gpionr
= irq_to_gpio(irq
);
774 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
775 u32 pintbit
= PINT_BIT(pint_val
);
776 u8 bank
= PINT_2_BANK(pint_val
);
778 if (pint_val
== IRQ_NOT_AVAIL
)
781 if (type
== IRQ_TYPE_PROBE
) {
782 /* only probe unenabled GPIO interrupt lines */
783 if (gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
))
785 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
788 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
789 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
790 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)))
791 bfin_gpio_irq_prepare(gpionr
);
793 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
795 gpio_enabled
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
799 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
800 pint
[bank
]->invert_set
= pintbit
; /* low or falling edge denoted by one */
802 pint
[bank
]->invert_clear
= pintbit
; /* high or rising edge denoted by zero */
804 if ((type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
805 == (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
807 gpio_both_edge_triggered
[bank
] |= pintbit
;
809 if (gpio_get_value(gpionr
))
810 pint
[bank
]->invert_set
= pintbit
;
812 pint
[bank
]->invert_clear
= pintbit
;
814 gpio_both_edge_triggered
[bank
] &= ~pintbit
;
817 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
818 pint
[bank
]->edge_set
= pintbit
;
819 bfin_set_irq_handler(irq
, handle_edge_irq
);
821 pint
[bank
]->edge_clear
= pintbit
;
822 bfin_set_irq_handler(irq
, handle_level_irq
);
831 u32 pint_saved_masks
[NR_PINT_SYS_IRQS
];
832 u32 pint_wakeup_masks
[NR_PINT_SYS_IRQS
];
834 int bfin_gpio_set_wake(unsigned int irq
, unsigned int state
)
837 u8 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
838 u32 bank
= PINT_2_BANK(pint_val
);
839 u32 pintbit
= PINT_BIT(pint_val
);
843 pint_irq
= IRQ_PINT0
;
846 pint_irq
= IRQ_PINT2
;
849 pint_irq
= IRQ_PINT3
;
852 pint_irq
= IRQ_PINT1
;
858 bfin_internal_set_wake(pint_irq
, state
);
861 pint_wakeup_masks
[bank
] |= pintbit
;
863 pint_wakeup_masks
[bank
] &= ~pintbit
;
868 u32
bfin_pm_setup(void)
872 for (i
= 0; i
< NR_PINT_SYS_IRQS
; i
++) {
873 val
= pint
[i
]->mask_clear
;
874 pint_saved_masks
[i
] = val
;
875 if (val
^ pint_wakeup_masks
[i
]) {
876 pint
[i
]->mask_clear
= val
;
877 pint
[i
]->mask_set
= pint_wakeup_masks
[i
];
884 void bfin_pm_restore(void)
888 for (i
= 0; i
< NR_PINT_SYS_IRQS
; i
++) {
889 val
= pint_saved_masks
[i
];
890 if (val
^ pint_wakeup_masks
[i
]) {
891 pint
[i
]->mask_clear
= pint
[i
]->mask_clear
;
892 pint
[i
]->mask_set
= val
;
898 static struct irq_chip bfin_gpio_irqchip
= {
900 .ack
= bfin_gpio_ack_irq
,
901 .mask
= bfin_gpio_mask_irq
,
902 .mask_ack
= bfin_gpio_mask_ack_irq
,
903 .unmask
= bfin_gpio_unmask_irq
,
904 .disable
= bfin_gpio_mask_irq
,
905 .enable
= bfin_gpio_unmask_irq
,
906 .set_type
= bfin_gpio_irq_type
,
907 .startup
= bfin_gpio_irq_startup
,
908 .shutdown
= bfin_gpio_irq_shutdown
,
910 .set_wake
= bfin_gpio_set_wake
,
914 static void bfin_demux_gpio_irq(unsigned int inta_irq
,
915 struct irq_desc
*desc
)
937 pint_val
= bank
* NR_PINT_BITS
;
939 request
= pint
[bank
]->request
;
943 irq
= pint2irq_lut
[pint_val
] + SYS_IRQS
;
944 desc
= irq_desc
+ irq
;
945 desc
->handle_irq(irq
, desc
);
954 void __init
init_exception_vectors(void)
958 /* cannot program in software:
959 * evt0 - emulation (jtag)
962 bfin_write_EVT2(evt_nmi
);
963 bfin_write_EVT3(trap
);
964 bfin_write_EVT5(evt_ivhw
);
965 bfin_write_EVT6(evt_timer
);
966 bfin_write_EVT7(evt_evt7
);
967 bfin_write_EVT8(evt_evt8
);
968 bfin_write_EVT9(evt_evt9
);
969 bfin_write_EVT10(evt_evt10
);
970 bfin_write_EVT11(evt_evt11
);
971 bfin_write_EVT12(evt_evt12
);
972 bfin_write_EVT13(evt_evt13
);
973 bfin_write_EVT14(evt14_softirq
);
974 bfin_write_EVT15(evt_system_call
);
979 * This function should be called during kernel startup to initialize
980 * the BFin IRQ handling routines.
982 int __init
init_arch_irq(void)
985 unsigned long ilat
= 0;
986 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
987 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
988 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL
);
989 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL
);
991 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL
);
994 bfin_write_SIC_IMASK(SIC_UNMASK_ALL
);
999 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1000 /* Clear EMAC Interrupt Status bits so we can demux it later */
1001 bfin_write_EMAC_SYSTAT(-1);
1005 # ifdef CONFIG_PINTx_REASSIGN
1006 pint
[0]->assign
= CONFIG_PINT0_ASSIGN
;
1007 pint
[1]->assign
= CONFIG_PINT1_ASSIGN
;
1008 pint
[2]->assign
= CONFIG_PINT2_ASSIGN
;
1009 pint
[3]->assign
= CONFIG_PINT3_ASSIGN
;
1011 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1015 for (irq
= 0; irq
<= SYS_IRQS
; irq
++) {
1016 if (irq
<= IRQ_CORETMR
)
1017 set_irq_chip(irq
, &bfin_core_irqchip
);
1019 set_irq_chip(irq
, &bfin_internal_irqchip
);
1022 #if defined(CONFIG_BF53x)
1024 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1027 #elif defined(CONFIG_BF54x)
1032 #elif defined(CONFIG_BF52x)
1033 case IRQ_PORTF_INTA
:
1034 case IRQ_PORTG_INTA
:
1035 case IRQ_PORTH_INTA
:
1036 #elif defined(CONFIG_BF561)
1037 case IRQ_PROG0_INTA
:
1038 case IRQ_PROG1_INTA
:
1039 case IRQ_PROG2_INTA
:
1041 set_irq_chained_handler(irq
,
1042 bfin_demux_gpio_irq
);
1044 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1045 case IRQ_GENERIC_ERROR
:
1046 set_irq_handler(irq
, bfin_demux_error_irq
);
1051 set_irq_handler(irq
, handle_simple_irq
);
1056 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1057 for (irq
= IRQ_PPI_ERROR
; irq
<= IRQ_UART1_ERROR
; irq
++)
1058 set_irq_chip_and_handler(irq
, &bfin_generic_error_irqchip
,
1062 /* if configured as edge, then will be changed to do_edge_IRQ */
1063 for (irq
= GPIO_IRQ_BASE
; irq
< NR_IRQS
; irq
++)
1064 set_irq_chip_and_handler(irq
, &bfin_gpio_irqchip
,
1068 bfin_write_IMASK(0);
1070 ilat
= bfin_read_ILAT();
1072 bfin_write_ILAT(ilat
);
1075 printk(KERN_INFO
"Configuring Blackfin Priority Driven Interrupts\n");
1076 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1077 * local_irq_enable()
1080 /* Therefore it's better to setup IARs before interrupts enabled */
1083 /* Enable interrupts IVG7-15 */
1084 irq_flags
= irq_flags
| IMASK_IVG15
|
1085 IMASK_IVG14
| IMASK_IVG13
| IMASK_IVG12
| IMASK_IVG11
|
1086 IMASK_IVG10
| IMASK_IVG9
| IMASK_IVG8
| IMASK_IVG7
| IMASK_IVGHW
;
1088 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1089 bfin_write_SIC_IWR0(IWR_DISABLE_ALL
);
1090 #if defined(CONFIG_BF52x)
1091 /* BF52x system reset does not properly reset SIC_IWR1 which
1092 * will screw up the bootrom as it relies on MDMA0/1 waking it
1093 * up from IDLE instructions. See this report for more info:
1094 * http://blackfin.uclinux.org/gf/tracker/4323
1096 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1098 bfin_write_SIC_IWR1(IWR_DISABLE_ALL
);
1100 # ifdef CONFIG_BF54x
1101 bfin_write_SIC_IWR2(IWR_DISABLE_ALL
);
1104 bfin_write_SIC_IWR(IWR_DISABLE_ALL
);
1110 #ifdef CONFIG_DO_IRQ_L1
1111 __attribute__((l1_text
))
1113 void do_irq(int vec
, struct pt_regs
*fp
)
1115 if (vec
== EVT_IVTMR_P
) {
1118 struct ivgx
*ivg
= ivg7_13
[vec
- IVG7
].ifirst
;
1119 struct ivgx
*ivg_stop
= ivg7_13
[vec
- IVG7
].istop
;
1120 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1121 unsigned long sic_status
[3];
1123 sic_status
[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1124 sic_status
[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1126 sic_status
[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1129 if (ivg
>= ivg_stop
) {
1130 atomic_inc(&num_spurious
);
1133 if (sic_status
[(ivg
->irqno
- IVG7
) / 32] & ivg
->isrflag
)
1137 unsigned long sic_status
;
1139 sic_status
= bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1142 if (ivg
>= ivg_stop
) {
1143 atomic_inc(&num_spurious
);
1145 } else if (sic_status
& ivg
->isrflag
)
1151 asm_do_IRQ(vec
, fp
);