1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw
*hw
);
36 static void e1000_phy_init_script(struct e1000_hw
*hw
);
37 static int32_t e1000_setup_copper_link(struct e1000_hw
*hw
);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw
*hw
);
42 static void e1000_raise_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
43 static void e1000_lower_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw
*hw
, uint32_t data
,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw
*hw
);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw
*hw
);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw
*hw
, uint16_t offset
,
49 uint16_t words
, uint16_t *data
);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
51 uint16_t offset
, uint16_t words
,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw
*hw
);
54 static void e1000_raise_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
55 static void e1000_lower_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
56 static void e1000_shift_out_ee_bits(struct e1000_hw
*hw
, uint16_t data
,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw
*hw
, uint32_t reg_addr
,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw
*hw
,uint32_t reg_addr
,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw
*hw
, uint16_t count
);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw
*hw
);
64 static void e1000_release_eeprom(struct e1000_hw
*hw
);
65 static void e1000_standby_eeprom(struct e1000_hw
*hw
);
66 static int32_t e1000_set_vco_speed(struct e1000_hw
*hw
);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw
*hw
);
68 static int32_t e1000_set_phy_mode(struct e1000_hw
*hw
);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw
*hw
, uint8_t *buffer
);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer
, uint32_t length
);
72 /* IGP cable length table */
74 uint16_t e1000_igp_cable_length_table
[IGP01E1000_AGC_LENGTH_TABLE_SIZE
] =
75 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
76 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
77 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
78 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
79 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
80 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
81 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
82 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
85 uint16_t e1000_igp_2_cable_length_table
[IGP02E1000_AGC_LENGTH_TABLE_SIZE
] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
96 /******************************************************************************
97 * Set the phy type member in the hw struct.
99 * hw - Struct containing variables accessed by shared code
100 *****************************************************************************/
102 e1000_set_phy_type(struct e1000_hw
*hw
)
104 DEBUGFUNC("e1000_set_phy_type");
106 if(hw
->mac_type
== e1000_undefined
)
107 return -E1000_ERR_PHY_TYPE
;
110 case M88E1000_E_PHY_ID
:
111 case M88E1000_I_PHY_ID
:
112 case M88E1011_I_PHY_ID
:
113 case M88E1111_I_PHY_ID
:
114 hw
->phy_type
= e1000_phy_m88
;
116 case IGP01E1000_I_PHY_ID
:
117 if(hw
->mac_type
== e1000_82541
||
118 hw
->mac_type
== e1000_82541_rev_2
||
119 hw
->mac_type
== e1000_82547
||
120 hw
->mac_type
== e1000_82547_rev_2
) {
121 hw
->phy_type
= e1000_phy_igp
;
126 /* Should never have loaded on this device */
127 hw
->phy_type
= e1000_phy_undefined
;
128 return -E1000_ERR_PHY_TYPE
;
131 return E1000_SUCCESS
;
134 /******************************************************************************
135 * IGP phy init script - initializes the GbE PHY
137 * hw - Struct containing variables accessed by shared code
138 *****************************************************************************/
140 e1000_phy_init_script(struct e1000_hw
*hw
)
143 uint16_t phy_saved_data
;
145 DEBUGFUNC("e1000_phy_init_script");
147 if(hw
->phy_init_script
) {
150 /* Save off the current value of register 0x2F5B to be restored at
151 * the end of this routine. */
152 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
154 /* Disabled the PHY transmitter */
155 e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
159 e1000_write_phy_reg(hw
,0x0000,0x0140);
163 switch(hw
->mac_type
) {
166 e1000_write_phy_reg(hw
, 0x1F95, 0x0001);
168 e1000_write_phy_reg(hw
, 0x1F71, 0xBD21);
170 e1000_write_phy_reg(hw
, 0x1F79, 0x0018);
172 e1000_write_phy_reg(hw
, 0x1F30, 0x1600);
174 e1000_write_phy_reg(hw
, 0x1F31, 0x0014);
176 e1000_write_phy_reg(hw
, 0x1F32, 0x161C);
178 e1000_write_phy_reg(hw
, 0x1F94, 0x0003);
180 e1000_write_phy_reg(hw
, 0x1F96, 0x003F);
182 e1000_write_phy_reg(hw
, 0x2010, 0x0008);
185 case e1000_82541_rev_2
:
186 case e1000_82547_rev_2
:
187 e1000_write_phy_reg(hw
, 0x1F73, 0x0099);
193 e1000_write_phy_reg(hw
, 0x0000, 0x3300);
197 /* Now enable the transmitter */
198 e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
200 if(hw
->mac_type
== e1000_82547
) {
201 uint16_t fused
, fine
, coarse
;
203 /* Move to analog registers page */
204 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_SPARE_FUSE_STATUS
, &fused
);
206 if(!(fused
& IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
)) {
207 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_STATUS
, &fused
);
209 fine
= fused
& IGP01E1000_ANALOG_FUSE_FINE_MASK
;
210 coarse
= fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
;
212 if(coarse
> IGP01E1000_ANALOG_FUSE_COARSE_THRESH
) {
213 coarse
-= IGP01E1000_ANALOG_FUSE_COARSE_10
;
214 fine
-= IGP01E1000_ANALOG_FUSE_FINE_1
;
215 } else if(coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH
)
216 fine
-= IGP01E1000_ANALOG_FUSE_FINE_10
;
218 fused
= (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK
) |
219 (fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK
) |
220 (coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
);
222 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_CONTROL
, fused
);
223 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_BYPASS
,
224 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
);
230 /******************************************************************************
231 * Set the mac type member in the hw struct.
233 * hw - Struct containing variables accessed by shared code
234 *****************************************************************************/
236 e1000_set_mac_type(struct e1000_hw
*hw
)
238 DEBUGFUNC("e1000_set_mac_type");
240 switch (hw
->device_id
) {
241 case E1000_DEV_ID_82542
:
242 switch (hw
->revision_id
) {
243 case E1000_82542_2_0_REV_ID
:
244 hw
->mac_type
= e1000_82542_rev2_0
;
246 case E1000_82542_2_1_REV_ID
:
247 hw
->mac_type
= e1000_82542_rev2_1
;
250 /* Invalid 82542 revision ID */
251 return -E1000_ERR_MAC_TYPE
;
254 case E1000_DEV_ID_82543GC_FIBER
:
255 case E1000_DEV_ID_82543GC_COPPER
:
256 hw
->mac_type
= e1000_82543
;
258 case E1000_DEV_ID_82544EI_COPPER
:
259 case E1000_DEV_ID_82544EI_FIBER
:
260 case E1000_DEV_ID_82544GC_COPPER
:
261 case E1000_DEV_ID_82544GC_LOM
:
262 hw
->mac_type
= e1000_82544
;
264 case E1000_DEV_ID_82540EM
:
265 case E1000_DEV_ID_82540EM_LOM
:
266 case E1000_DEV_ID_82540EP
:
267 case E1000_DEV_ID_82540EP_LOM
:
268 case E1000_DEV_ID_82540EP_LP
:
269 hw
->mac_type
= e1000_82540
;
271 case E1000_DEV_ID_82545EM_COPPER
:
272 case E1000_DEV_ID_82545EM_FIBER
:
273 hw
->mac_type
= e1000_82545
;
275 case E1000_DEV_ID_82545GM_COPPER
:
276 case E1000_DEV_ID_82545GM_FIBER
:
277 case E1000_DEV_ID_82545GM_SERDES
:
278 hw
->mac_type
= e1000_82545_rev_3
;
280 case E1000_DEV_ID_82546EB_COPPER
:
281 case E1000_DEV_ID_82546EB_FIBER
:
282 case E1000_DEV_ID_82546EB_QUAD_COPPER
:
283 hw
->mac_type
= e1000_82546
;
285 case E1000_DEV_ID_82546GB_COPPER
:
286 case E1000_DEV_ID_82546GB_FIBER
:
287 case E1000_DEV_ID_82546GB_SERDES
:
288 case E1000_DEV_ID_82546GB_PCIE
:
289 case E1000_DEV_ID_82546GB_QUAD_COPPER
:
290 hw
->mac_type
= e1000_82546_rev_3
;
292 case E1000_DEV_ID_82541EI
:
293 case E1000_DEV_ID_82541EI_MOBILE
:
294 hw
->mac_type
= e1000_82541
;
296 case E1000_DEV_ID_82541ER
:
297 case E1000_DEV_ID_82541GI
:
298 case E1000_DEV_ID_82541GI_LF
:
299 case E1000_DEV_ID_82541GI_MOBILE
:
300 hw
->mac_type
= e1000_82541_rev_2
;
302 case E1000_DEV_ID_82547EI
:
303 hw
->mac_type
= e1000_82547
;
305 case E1000_DEV_ID_82547GI
:
306 hw
->mac_type
= e1000_82547_rev_2
;
308 case E1000_DEV_ID_82573E
:
309 case E1000_DEV_ID_82573E_IAMT
:
310 hw
->mac_type
= e1000_82573
;
313 /* Should never have loaded on this device */
314 return -E1000_ERR_MAC_TYPE
;
317 switch(hw
->mac_type
) {
319 hw
->eeprom_semaphore_present
= TRUE
;
323 case e1000_82541_rev_2
:
324 case e1000_82547_rev_2
:
325 hw
->asf_firmware_present
= TRUE
;
331 return E1000_SUCCESS
;
334 /*****************************************************************************
335 * Set media type and TBI compatibility.
337 * hw - Struct containing variables accessed by shared code
338 * **************************************************************************/
340 e1000_set_media_type(struct e1000_hw
*hw
)
344 DEBUGFUNC("e1000_set_media_type");
346 if(hw
->mac_type
!= e1000_82543
) {
347 /* tbi_compatibility is only valid on 82543 */
348 hw
->tbi_compatibility_en
= FALSE
;
351 switch (hw
->device_id
) {
352 case E1000_DEV_ID_82545GM_SERDES
:
353 case E1000_DEV_ID_82546GB_SERDES
:
354 hw
->media_type
= e1000_media_type_internal_serdes
;
357 switch (hw
->mac_type
) {
358 case e1000_82542_rev2_0
:
359 case e1000_82542_rev2_1
:
360 hw
->media_type
= e1000_media_type_fiber
;
363 /* The STATUS_TBIMODE bit is reserved or reused for the this
366 hw
->media_type
= e1000_media_type_copper
;
369 status
= E1000_READ_REG(hw
, STATUS
);
370 if (status
& E1000_STATUS_TBIMODE
) {
371 hw
->media_type
= e1000_media_type_fiber
;
372 /* tbi_compatibility not valid on fiber */
373 hw
->tbi_compatibility_en
= FALSE
;
375 hw
->media_type
= e1000_media_type_copper
;
382 /******************************************************************************
383 * Reset the transmit and receive units; mask and clear all interrupts.
385 * hw - Struct containing variables accessed by shared code
386 *****************************************************************************/
388 e1000_reset_hw(struct e1000_hw
*hw
)
396 uint32_t extcnf_ctrl
;
399 DEBUGFUNC("e1000_reset_hw");
401 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
402 if(hw
->mac_type
== e1000_82542_rev2_0
) {
403 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
404 e1000_pci_clear_mwi(hw
);
407 if(hw
->bus_type
== e1000_bus_type_pci_express
) {
408 /* Prevent the PCI-E bus from sticking if there is no TLP connection
409 * on the last TLP read/write transaction when MAC is reset.
411 if(e1000_disable_pciex_master(hw
) != E1000_SUCCESS
) {
412 DEBUGOUT("PCI-E Master disable polling has failed.\n");
416 /* Clear interrupt mask to stop board from generating interrupts */
417 DEBUGOUT("Masking off all interrupts\n");
418 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
420 /* Disable the Transmit and Receive units. Then delay to allow
421 * any pending transactions to complete before we hit the MAC with
424 E1000_WRITE_REG(hw
, RCTL
, 0);
425 E1000_WRITE_REG(hw
, TCTL
, E1000_TCTL_PSP
);
426 E1000_WRITE_FLUSH(hw
);
428 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
429 hw
->tbi_compatibility_on
= FALSE
;
431 /* Delay to allow any outstanding PCI transactions to complete before
432 * resetting the device
436 ctrl
= E1000_READ_REG(hw
, CTRL
);
438 /* Must reset the PHY before resetting the MAC */
439 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
440 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_PHY_RST
));
444 /* Must acquire the MDIO ownership before MAC reset.
445 * Ownership defaults to firmware after a reset. */
446 if(hw
->mac_type
== e1000_82573
) {
449 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
450 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
453 E1000_WRITE_REG(hw
, EXTCNF_CTRL
, extcnf_ctrl
);
454 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
456 if(extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
459 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
466 /* Issue a global reset to the MAC. This will reset the chip's
467 * transmit, receive, DMA, and link units. It will not effect
468 * the current PCI configuration. The global reset bit is self-
469 * clearing, and should clear within a microsecond.
471 DEBUGOUT("Issuing a global reset to MAC\n");
473 switch(hw
->mac_type
) {
479 case e1000_82541_rev_2
:
480 /* These controllers can't ack the 64-bit write when issuing the
481 * reset, so use IO-mapping as a workaround to issue the reset */
482 E1000_WRITE_REG_IO(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
484 case e1000_82545_rev_3
:
485 case e1000_82546_rev_3
:
486 /* Reset is performed on a shadow of the control register */
487 E1000_WRITE_REG(hw
, CTRL_DUP
, (ctrl
| E1000_CTRL_RST
));
490 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
494 /* After MAC reset, force reload of EEPROM to restore power-on settings to
495 * device. Later controllers reload the EEPROM automatically, so just wait
496 * for reload to complete.
498 switch(hw
->mac_type
) {
499 case e1000_82542_rev2_0
:
500 case e1000_82542_rev2_1
:
503 /* Wait for reset to complete */
505 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
506 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
507 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
508 E1000_WRITE_FLUSH(hw
);
509 /* Wait for EEPROM reload */
513 case e1000_82541_rev_2
:
515 case e1000_82547_rev_2
:
516 /* Wait for EEPROM reload */
521 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
522 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
523 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
524 E1000_WRITE_FLUSH(hw
);
526 ret_val
= e1000_get_auto_rd_done(hw
);
528 /* We don't want to continue accessing MAC registers. */
532 /* Wait for EEPROM reload (it happens automatically) */
537 /* Disable HW ARPs on ASF enabled adapters */
538 if(hw
->mac_type
>= e1000_82540
&& hw
->mac_type
<= e1000_82547_rev_2
) {
539 manc
= E1000_READ_REG(hw
, MANC
);
540 manc
&= ~(E1000_MANC_ARP_EN
);
541 E1000_WRITE_REG(hw
, MANC
, manc
);
544 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
545 e1000_phy_init_script(hw
);
547 /* Configure activity LED after PHY reset */
548 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
549 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
550 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
551 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
554 /* Clear interrupt mask to stop board from generating interrupts */
555 DEBUGOUT("Masking off all interrupts\n");
556 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
558 /* Clear any pending interrupt events. */
559 icr
= E1000_READ_REG(hw
, ICR
);
561 /* If MWI was previously enabled, reenable it. */
562 if(hw
->mac_type
== e1000_82542_rev2_0
) {
563 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
564 e1000_pci_set_mwi(hw
);
567 return E1000_SUCCESS
;
570 /******************************************************************************
571 * Performs basic configuration of the adapter.
573 * hw - Struct containing variables accessed by shared code
575 * Assumes that the controller has previously been reset and is in a
576 * post-reset uninitialized state. Initializes the receive address registers,
577 * multicast table, and VLAN filter table. Calls routines to setup link
578 * configuration and flow control settings. Clears all on-chip counters. Leaves
579 * the transmit and receive units disabled and uninitialized.
580 *****************************************************************************/
582 e1000_init_hw(struct e1000_hw
*hw
)
587 uint16_t pcix_cmd_word
;
588 uint16_t pcix_stat_hi_word
;
593 DEBUGFUNC("e1000_init_hw");
595 /* Initialize Identification LED */
596 ret_val
= e1000_id_led_init(hw
);
598 DEBUGOUT("Error Initializing Identification LED\n");
602 /* Set the media type and TBI compatibility */
603 e1000_set_media_type(hw
);
605 /* Disabling VLAN filtering. */
606 DEBUGOUT("Initializing the IEEE VLAN\n");
607 if (hw
->mac_type
< e1000_82545_rev_3
)
608 E1000_WRITE_REG(hw
, VET
, 0);
609 e1000_clear_vfta(hw
);
611 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
612 if(hw
->mac_type
== e1000_82542_rev2_0
) {
613 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
614 e1000_pci_clear_mwi(hw
);
615 E1000_WRITE_REG(hw
, RCTL
, E1000_RCTL_RST
);
616 E1000_WRITE_FLUSH(hw
);
620 /* Setup the receive address. This involves initializing all of the Receive
621 * Address Registers (RARs 0 - 15).
623 e1000_init_rx_addrs(hw
);
625 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
626 if(hw
->mac_type
== e1000_82542_rev2_0
) {
627 E1000_WRITE_REG(hw
, RCTL
, 0);
628 E1000_WRITE_FLUSH(hw
);
630 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
631 e1000_pci_set_mwi(hw
);
634 /* Zero out the Multicast HASH table */
635 DEBUGOUT("Zeroing the MTA\n");
636 mta_size
= E1000_MC_TBL_SIZE
;
637 for(i
= 0; i
< mta_size
; i
++)
638 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
640 /* Set the PCI priority bit correctly in the CTRL register. This
641 * determines if the adapter gives priority to receives, or if it
642 * gives equal priority to transmits and receives. Valid only on
643 * 82542 and 82543 silicon.
645 if(hw
->dma_fairness
&& hw
->mac_type
<= e1000_82543
) {
646 ctrl
= E1000_READ_REG(hw
, CTRL
);
647 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PRIOR
);
650 switch(hw
->mac_type
) {
651 case e1000_82545_rev_3
:
652 case e1000_82546_rev_3
:
655 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
656 if(hw
->bus_type
== e1000_bus_type_pcix
) {
657 e1000_read_pci_cfg(hw
, PCIX_COMMAND_REGISTER
, &pcix_cmd_word
);
658 e1000_read_pci_cfg(hw
, PCIX_STATUS_REGISTER_HI
,
660 cmd_mmrbc
= (pcix_cmd_word
& PCIX_COMMAND_MMRBC_MASK
) >>
661 PCIX_COMMAND_MMRBC_SHIFT
;
662 stat_mmrbc
= (pcix_stat_hi_word
& PCIX_STATUS_HI_MMRBC_MASK
) >>
663 PCIX_STATUS_HI_MMRBC_SHIFT
;
664 if(stat_mmrbc
== PCIX_STATUS_HI_MMRBC_4K
)
665 stat_mmrbc
= PCIX_STATUS_HI_MMRBC_2K
;
666 if(cmd_mmrbc
> stat_mmrbc
) {
667 pcix_cmd_word
&= ~PCIX_COMMAND_MMRBC_MASK
;
668 pcix_cmd_word
|= stat_mmrbc
<< PCIX_COMMAND_MMRBC_SHIFT
;
669 e1000_write_pci_cfg(hw
, PCIX_COMMAND_REGISTER
,
676 /* Call a subroutine to configure the link and setup flow control. */
677 ret_val
= e1000_setup_link(hw
);
679 /* Set the transmit descriptor write-back policy */
680 if(hw
->mac_type
> e1000_82544
) {
681 ctrl
= E1000_READ_REG(hw
, TXDCTL
);
682 ctrl
= (ctrl
& ~E1000_TXDCTL_WTHRESH
) | E1000_TXDCTL_FULL_TX_DESC_WB
;
683 switch (hw
->mac_type
) {
687 ctrl
|= E1000_TXDCTL_COUNT_DESC
;
690 E1000_WRITE_REG(hw
, TXDCTL
, ctrl
);
693 if (hw
->mac_type
== e1000_82573
) {
694 e1000_enable_tx_pkt_filtering(hw
);
698 /* Clear all of the statistics registers (clear on read). It is
699 * important that we do this after we have tried to establish link
700 * because the symbol error count will increment wildly if there
703 e1000_clear_hw_cntrs(hw
);
708 /******************************************************************************
709 * Adjust SERDES output amplitude based on EEPROM setting.
711 * hw - Struct containing variables accessed by shared code.
712 *****************************************************************************/
714 e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
)
716 uint16_t eeprom_data
;
719 DEBUGFUNC("e1000_adjust_serdes_amplitude");
721 if(hw
->media_type
!= e1000_media_type_internal_serdes
)
722 return E1000_SUCCESS
;
724 switch(hw
->mac_type
) {
725 case e1000_82545_rev_3
:
726 case e1000_82546_rev_3
:
729 return E1000_SUCCESS
;
732 ret_val
= e1000_read_eeprom(hw
, EEPROM_SERDES_AMPLITUDE
, 1, &eeprom_data
);
737 if(eeprom_data
!= EEPROM_RESERVED_WORD
) {
738 /* Adjust SERDES output amplitude only. */
739 eeprom_data
&= EEPROM_SERDES_AMPLITUDE_MASK
;
740 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_EXT_CTRL
, eeprom_data
);
745 return E1000_SUCCESS
;
748 /******************************************************************************
749 * Configures flow control and link settings.
751 * hw - Struct containing variables accessed by shared code
753 * Determines which flow control settings to use. Calls the apropriate media-
754 * specific link configuration function. Configures the flow control settings.
755 * Assuming the adapter has a valid link partner, a valid link should be
756 * established. Assumes the hardware has previously been reset and the
757 * transmitter and receiver are not enabled.
758 *****************************************************************************/
760 e1000_setup_link(struct e1000_hw
*hw
)
764 uint16_t eeprom_data
;
766 DEBUGFUNC("e1000_setup_link");
768 /* Read and store word 0x0F of the EEPROM. This word contains bits
769 * that determine the hardware's default PAUSE (flow control) mode,
770 * a bit that determines whether the HW defaults to enabling or
771 * disabling auto-negotiation, and the direction of the
772 * SW defined pins. If there is no SW over-ride of the flow
773 * control setting, then the variable hw->fc will
774 * be initialized based on a value in the EEPROM.
776 if(e1000_read_eeprom(hw
, EEPROM_INIT_CONTROL2_REG
, 1, &eeprom_data
)) {
777 DEBUGOUT("EEPROM Read Error\n");
778 return -E1000_ERR_EEPROM
;
781 if(hw
->fc
== e1000_fc_default
) {
782 if((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) == 0)
783 hw
->fc
= e1000_fc_none
;
784 else if((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) ==
785 EEPROM_WORD0F_ASM_DIR
)
786 hw
->fc
= e1000_fc_tx_pause
;
788 hw
->fc
= e1000_fc_full
;
791 /* We want to save off the original Flow Control configuration just
792 * in case we get disconnected and then reconnected into a different
793 * hub or switch with different Flow Control capabilities.
795 if(hw
->mac_type
== e1000_82542_rev2_0
)
796 hw
->fc
&= (~e1000_fc_tx_pause
);
798 if((hw
->mac_type
< e1000_82543
) && (hw
->report_tx_early
== 1))
799 hw
->fc
&= (~e1000_fc_rx_pause
);
801 hw
->original_fc
= hw
->fc
;
803 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw
->fc
);
805 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
806 * polarity value for the SW controlled pins, and setup the
807 * Extended Device Control reg with that info.
808 * This is needed because one of the SW controlled pins is used for
809 * signal detection. So this should be done before e1000_setup_pcs_link()
810 * or e1000_phy_setup() is called.
812 if(hw
->mac_type
== e1000_82543
) {
813 ctrl_ext
= ((eeprom_data
& EEPROM_WORD0F_SWPDIO_EXT
) <<
815 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
818 /* Call the necessary subroutine to configure the link. */
819 ret_val
= (hw
->media_type
== e1000_media_type_copper
) ?
820 e1000_setup_copper_link(hw
) :
821 e1000_setup_fiber_serdes_link(hw
);
823 /* Initialize the flow control address, type, and PAUSE timer
824 * registers to their default values. This is done even if flow
825 * control is disabled, because it does not hurt anything to
826 * initialize these registers.
828 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
830 E1000_WRITE_REG(hw
, FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
831 E1000_WRITE_REG(hw
, FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
832 E1000_WRITE_REG(hw
, FCT
, FLOW_CONTROL_TYPE
);
834 E1000_WRITE_REG(hw
, FCTTV
, hw
->fc_pause_time
);
836 /* Set the flow control receive threshold registers. Normally,
837 * these registers will be set to a default threshold that may be
838 * adjusted later by the driver's runtime code. However, if the
839 * ability to transmit pause frames in not enabled, then these
840 * registers will be set to 0.
842 if(!(hw
->fc
& e1000_fc_tx_pause
)) {
843 E1000_WRITE_REG(hw
, FCRTL
, 0);
844 E1000_WRITE_REG(hw
, FCRTH
, 0);
846 /* We need to set up the Receive Threshold high and low water marks
847 * as well as (optionally) enabling the transmission of XON frames.
849 if(hw
->fc_send_xon
) {
850 E1000_WRITE_REG(hw
, FCRTL
, (hw
->fc_low_water
| E1000_FCRTL_XONE
));
851 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
853 E1000_WRITE_REG(hw
, FCRTL
, hw
->fc_low_water
);
854 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
860 /******************************************************************************
861 * Sets up link for a fiber based or serdes based adapter
863 * hw - Struct containing variables accessed by shared code
865 * Manipulates Physical Coding Sublayer functions in order to configure
866 * link. Assumes the hardware has been previously reset and the transmitter
867 * and receiver are not enabled.
868 *****************************************************************************/
870 e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
)
879 DEBUGFUNC("e1000_setup_fiber_serdes_link");
881 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
882 * set when the optics detect a signal. On older adapters, it will be
883 * cleared when there is a signal. This applies to fiber media only.
884 * If we're on serdes media, adjust the output amplitude to value set in
887 ctrl
= E1000_READ_REG(hw
, CTRL
);
888 if(hw
->media_type
== e1000_media_type_fiber
)
889 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
891 ret_val
= e1000_adjust_serdes_amplitude(hw
);
895 /* Take the link out of reset */
896 ctrl
&= ~(E1000_CTRL_LRST
);
898 /* Adjust VCO speed to improve BER performance */
899 ret_val
= e1000_set_vco_speed(hw
);
903 e1000_config_collision_dist(hw
);
905 /* Check for a software override of the flow control settings, and setup
906 * the device accordingly. If auto-negotiation is enabled, then software
907 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
908 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
909 * auto-negotiation is disabled, then software will have to manually
910 * configure the two flow control enable bits in the CTRL register.
912 * The possible values of the "fc" parameter are:
913 * 0: Flow control is completely disabled
914 * 1: Rx flow control is enabled (we can receive pause frames, but
915 * not send pause frames).
916 * 2: Tx flow control is enabled (we can send pause frames but we do
917 * not support receiving pause frames).
918 * 3: Both Rx and TX flow control (symmetric) are enabled.
922 /* Flow control is completely disabled by a software over-ride. */
923 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
925 case e1000_fc_rx_pause
:
926 /* RX Flow control is enabled and TX Flow control is disabled by a
927 * software over-ride. Since there really isn't a way to advertise
928 * that we are capable of RX Pause ONLY, we will advertise that we
929 * support both symmetric and asymmetric RX PAUSE. Later, we will
930 * disable the adapter's ability to send PAUSE frames.
932 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
934 case e1000_fc_tx_pause
:
935 /* TX Flow control is enabled, and RX Flow control is disabled, by a
936 * software over-ride.
938 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
941 /* Flow control (both RX and TX) is enabled by a software over-ride. */
942 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
945 DEBUGOUT("Flow control param set incorrectly\n");
946 return -E1000_ERR_CONFIG
;
950 /* Since auto-negotiation is enabled, take the link out of reset (the link
951 * will be in reset, because we previously reset the chip). This will
952 * restart auto-negotiation. If auto-neogtiation is successful then the
953 * link-up status bit will be set and the flow control enable bits (RFCE
954 * and TFCE) will be set according to their negotiated value.
956 DEBUGOUT("Auto-negotiation enabled\n");
958 E1000_WRITE_REG(hw
, TXCW
, txcw
);
959 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
960 E1000_WRITE_FLUSH(hw
);
965 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
966 * indication in the Device Status Register. Time-out if a link isn't
967 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
968 * less than 500 milliseconds even if the other end is doing it in SW).
969 * For internal serdes, we just assume a signal is present, then poll.
971 if(hw
->media_type
== e1000_media_type_internal_serdes
||
972 (E1000_READ_REG(hw
, CTRL
) & E1000_CTRL_SWDPIN1
) == signal
) {
973 DEBUGOUT("Looking for Link\n");
974 for(i
= 0; i
< (LINK_UP_TIMEOUT
/ 10); i
++) {
976 status
= E1000_READ_REG(hw
, STATUS
);
977 if(status
& E1000_STATUS_LU
) break;
979 if(i
== (LINK_UP_TIMEOUT
/ 10)) {
980 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
981 hw
->autoneg_failed
= 1;
982 /* AutoNeg failed to achieve a link, so we'll call
983 * e1000_check_for_link. This routine will force the link up if
984 * we detect a signal. This will allow us to communicate with
985 * non-autonegotiating link partners.
987 ret_val
= e1000_check_for_link(hw
);
989 DEBUGOUT("Error while checking for link\n");
992 hw
->autoneg_failed
= 0;
994 hw
->autoneg_failed
= 0;
995 DEBUGOUT("Valid Link Found\n");
998 DEBUGOUT("No Signal Detected\n");
1000 return E1000_SUCCESS
;
1003 /******************************************************************************
1004 * Make sure we have a valid PHY and change PHY mode before link setup.
1006 * hw - Struct containing variables accessed by shared code
1007 ******************************************************************************/
1009 e1000_copper_link_preconfig(struct e1000_hw
*hw
)
1015 DEBUGFUNC("e1000_copper_link_preconfig");
1017 ctrl
= E1000_READ_REG(hw
, CTRL
);
1018 /* With 82543, we need to force speed and duplex on the MAC equal to what
1019 * the PHY speed and duplex configuration is. In addition, we need to
1020 * perform a hardware reset on the PHY to take it out of reset.
1022 if(hw
->mac_type
> e1000_82543
) {
1023 ctrl
|= E1000_CTRL_SLU
;
1024 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1025 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1027 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
| E1000_CTRL_SLU
);
1028 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1029 ret_val
= e1000_phy_hw_reset(hw
);
1034 /* Make sure we have a valid PHY */
1035 ret_val
= e1000_detect_gig_phy(hw
);
1037 DEBUGOUT("Error, did not detect valid phy.\n");
1040 DEBUGOUT1("Phy ID = %x \n", hw
->phy_id
);
1042 /* Set PHY to class A mode (if necessary) */
1043 ret_val
= e1000_set_phy_mode(hw
);
1047 if((hw
->mac_type
== e1000_82545_rev_3
) ||
1048 (hw
->mac_type
== e1000_82546_rev_3
)) {
1049 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1050 phy_data
|= 0x00000008;
1051 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1054 if(hw
->mac_type
<= e1000_82543
||
1055 hw
->mac_type
== e1000_82541
|| hw
->mac_type
== e1000_82547
||
1056 hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
)
1057 hw
->phy_reset_disable
= FALSE
;
1059 return E1000_SUCCESS
;
1063 /********************************************************************
1064 * Copper link setup for e1000_phy_igp series.
1066 * hw - Struct containing variables accessed by shared code
1067 *********************************************************************/
1069 e1000_copper_link_igp_setup(struct e1000_hw
*hw
)
1075 DEBUGFUNC("e1000_copper_link_igp_setup");
1077 if (hw
->phy_reset_disable
)
1078 return E1000_SUCCESS
;
1080 ret_val
= e1000_phy_reset(hw
);
1082 DEBUGOUT("Error Resetting the PHY\n");
1086 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1089 /* Configure activity LED after PHY reset */
1090 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
1091 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1092 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1093 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
1095 /* disable lplu d3 during driver init */
1096 ret_val
= e1000_set_d3_lplu_state(hw
, FALSE
);
1098 DEBUGOUT("Error Disabling LPLU D3\n");
1102 /* disable lplu d0 during driver init */
1103 ret_val
= e1000_set_d0_lplu_state(hw
, FALSE
);
1105 DEBUGOUT("Error Disabling LPLU D0\n");
1108 /* Configure mdi-mdix settings */
1109 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1113 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
1114 hw
->dsp_config_state
= e1000_dsp_config_disabled
;
1115 /* Force MDI for earlier revs of the IGP PHY */
1116 phy_data
&= ~(IGP01E1000_PSCR_AUTO_MDIX
| IGP01E1000_PSCR_FORCE_MDI_MDIX
);
1120 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1121 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1125 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1128 phy_data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1132 phy_data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1136 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1140 /* set auto-master slave resolution settings */
1142 e1000_ms_type phy_ms_setting
= hw
->master_slave
;
1144 if(hw
->ffe_config_state
== e1000_ffe_config_active
)
1145 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
1147 if(hw
->dsp_config_state
== e1000_dsp_config_activated
)
1148 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1150 /* when autonegotiation advertisment is only 1000Mbps then we
1151 * should disable SmartSpeed and enable Auto MasterSlave
1152 * resolution as hardware default. */
1153 if(hw
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1154 /* Disable SmartSpeed */
1155 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
1158 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1159 ret_val
= e1000_write_phy_reg(hw
,
1160 IGP01E1000_PHY_PORT_CONFIG
,
1164 /* Set auto Master/Slave resolution process */
1165 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1168 phy_data
&= ~CR_1000T_MS_ENABLE
;
1169 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1174 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1178 /* load defaults for future use */
1179 hw
->original_master_slave
= (phy_data
& CR_1000T_MS_ENABLE
) ?
1180 ((phy_data
& CR_1000T_MS_VALUE
) ?
1181 e1000_ms_force_master
:
1182 e1000_ms_force_slave
) :
1185 switch (phy_ms_setting
) {
1186 case e1000_ms_force_master
:
1187 phy_data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1189 case e1000_ms_force_slave
:
1190 phy_data
|= CR_1000T_MS_ENABLE
;
1191 phy_data
&= ~(CR_1000T_MS_VALUE
);
1194 phy_data
&= ~CR_1000T_MS_ENABLE
;
1198 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1203 return E1000_SUCCESS
;
1207 /********************************************************************
1208 * Copper link setup for e1000_phy_m88 series.
1210 * hw - Struct containing variables accessed by shared code
1211 *********************************************************************/
1213 e1000_copper_link_mgp_setup(struct e1000_hw
*hw
)
1218 DEBUGFUNC("e1000_copper_link_mgp_setup");
1220 if(hw
->phy_reset_disable
)
1221 return E1000_SUCCESS
;
1223 /* Enable CRS on TX. This must be set for half-duplex operation. */
1224 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1228 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1231 * MDI/MDI-X = 0 (default)
1232 * 0 - Auto for all speeds
1235 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1237 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1241 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
1244 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
1247 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
1251 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
1256 * disable_polarity_correction = 0 (default)
1257 * Automatic Correction for Reversed Cable Polarity
1261 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
1262 if(hw
->disable_polarity_correction
== 1)
1263 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
1264 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1268 /* Force TX_CLK in the Extended PHY Specific Control Register
1271 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1275 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1277 if (hw
->phy_revision
< M88E1011_I_REV_4
) {
1278 /* Configure Master and Slave downshift values */
1279 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
1280 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
1281 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
1282 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
1283 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1288 /* SW Reset the PHY so all changes take effect */
1289 ret_val
= e1000_phy_reset(hw
);
1291 DEBUGOUT("Error Resetting the PHY\n");
1295 return E1000_SUCCESS
;
1298 /********************************************************************
1299 * Setup auto-negotiation and flow control advertisements,
1300 * and then perform auto-negotiation.
1302 * hw - Struct containing variables accessed by shared code
1303 *********************************************************************/
1305 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1310 DEBUGFUNC("e1000_copper_link_autoneg");
1312 /* Perform some bounds checking on the hw->autoneg_advertised
1313 * parameter. If this variable is zero, then set it to the default.
1315 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1317 /* If autoneg_advertised is zero, we assume it was not defaulted
1318 * by the calling code so we set to advertise full capability.
1320 if(hw
->autoneg_advertised
== 0)
1321 hw
->autoneg_advertised
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1323 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1324 ret_val
= e1000_phy_setup_autoneg(hw
);
1326 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1329 DEBUGOUT("Restarting Auto-Neg\n");
1331 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1332 * the Auto Neg Restart bit in the PHY control register.
1334 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
1338 phy_data
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1339 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
1343 /* Does the user want to wait for Auto-Neg to complete here, or
1344 * check at a later time (for example, callback routine).
1346 if(hw
->wait_autoneg_complete
) {
1347 ret_val
= e1000_wait_autoneg(hw
);
1349 DEBUGOUT("Error while waiting for autoneg to complete\n");
1354 hw
->get_link_status
= TRUE
;
1356 return E1000_SUCCESS
;
1360 /******************************************************************************
1361 * Config the MAC and the PHY after link is up.
1362 * 1) Set up the MAC to the current PHY speed/duplex
1363 * if we are on 82543. If we
1364 * are on newer silicon, we only need to configure
1365 * collision distance in the Transmit Control Register.
1366 * 2) Set up flow control on the MAC to that established with
1368 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1370 * hw - Struct containing variables accessed by shared code
1371 ******************************************************************************/
1373 e1000_copper_link_postconfig(struct e1000_hw
*hw
)
1376 DEBUGFUNC("e1000_copper_link_postconfig");
1378 if(hw
->mac_type
>= e1000_82544
) {
1379 e1000_config_collision_dist(hw
);
1381 ret_val
= e1000_config_mac_to_phy(hw
);
1383 DEBUGOUT("Error configuring MAC to PHY settings\n");
1387 ret_val
= e1000_config_fc_after_link_up(hw
);
1389 DEBUGOUT("Error Configuring Flow Control\n");
1393 /* Config DSP to improve Giga link quality */
1394 if(hw
->phy_type
== e1000_phy_igp
) {
1395 ret_val
= e1000_config_dsp_after_link_change(hw
, TRUE
);
1397 DEBUGOUT("Error Configuring DSP after link up\n");
1402 return E1000_SUCCESS
;
1405 /******************************************************************************
1406 * Detects which PHY is present and setup the speed and duplex
1408 * hw - Struct containing variables accessed by shared code
1409 ******************************************************************************/
1411 e1000_setup_copper_link(struct e1000_hw
*hw
)
1417 DEBUGFUNC("e1000_setup_copper_link");
1419 /* Check if it is a valid PHY and set PHY mode if necessary. */
1420 ret_val
= e1000_copper_link_preconfig(hw
);
1424 if (hw
->phy_type
== e1000_phy_igp
||
1425 hw
->phy_type
== e1000_phy_igp_2
) {
1426 ret_val
= e1000_copper_link_igp_setup(hw
);
1429 } else if (hw
->phy_type
== e1000_phy_m88
) {
1430 ret_val
= e1000_copper_link_mgp_setup(hw
);
1436 /* Setup autoneg and flow control advertisement
1437 * and perform autonegotiation */
1438 ret_val
= e1000_copper_link_autoneg(hw
);
1442 /* PHY will be set to 10H, 10F, 100H,or 100F
1443 * depending on value from forced_speed_duplex. */
1444 DEBUGOUT("Forcing speed and duplex\n");
1445 ret_val
= e1000_phy_force_speed_duplex(hw
);
1447 DEBUGOUT("Error Forcing Speed and Duplex\n");
1452 /* Check link status. Wait up to 100 microseconds for link to become
1455 for(i
= 0; i
< 10; i
++) {
1456 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1459 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1463 if(phy_data
& MII_SR_LINK_STATUS
) {
1464 /* Config the MAC and PHY after link is up */
1465 ret_val
= e1000_copper_link_postconfig(hw
);
1469 DEBUGOUT("Valid link established!!!\n");
1470 return E1000_SUCCESS
;
1475 DEBUGOUT("Unable to establish link!!!\n");
1476 return E1000_SUCCESS
;
1479 /******************************************************************************
1480 * Configures PHY autoneg and flow control advertisement settings
1482 * hw - Struct containing variables accessed by shared code
1483 ******************************************************************************/
1485 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1488 uint16_t mii_autoneg_adv_reg
;
1489 uint16_t mii_1000t_ctrl_reg
;
1491 DEBUGFUNC("e1000_phy_setup_autoneg");
1493 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1494 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1498 /* Read the MII 1000Base-T Control Register (Address 9). */
1499 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
1503 /* Need to parse both autoneg_advertised and fc and set up
1504 * the appropriate PHY registers. First we will parse for
1505 * autoneg_advertised software override. Since we can advertise
1506 * a plethora of combinations, we need to check each bit
1510 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1511 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1512 * the 1000Base-T Control Register (Address 9).
1514 mii_autoneg_adv_reg
&= ~REG4_SPEED_MASK
;
1515 mii_1000t_ctrl_reg
&= ~REG9_SPEED_MASK
;
1517 DEBUGOUT1("autoneg_advertised %x\n", hw
->autoneg_advertised
);
1519 /* Do we want to advertise 10 Mb Half Duplex? */
1520 if(hw
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1521 DEBUGOUT("Advertise 10mb Half duplex\n");
1522 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1525 /* Do we want to advertise 10 Mb Full Duplex? */
1526 if(hw
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1527 DEBUGOUT("Advertise 10mb Full duplex\n");
1528 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1531 /* Do we want to advertise 100 Mb Half Duplex? */
1532 if(hw
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1533 DEBUGOUT("Advertise 100mb Half duplex\n");
1534 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1537 /* Do we want to advertise 100 Mb Full Duplex? */
1538 if(hw
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1539 DEBUGOUT("Advertise 100mb Full duplex\n");
1540 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1543 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1544 if(hw
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
1545 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1548 /* Do we want to advertise 1000 Mb Full Duplex? */
1549 if(hw
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1550 DEBUGOUT("Advertise 1000mb Full duplex\n");
1551 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1554 /* Check for a software override of the flow control settings, and
1555 * setup the PHY advertisement registers accordingly. If
1556 * auto-negotiation is enabled, then software will have to set the
1557 * "PAUSE" bits to the correct value in the Auto-Negotiation
1558 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1560 * The possible values of the "fc" parameter are:
1561 * 0: Flow control is completely disabled
1562 * 1: Rx flow control is enabled (we can receive pause frames
1563 * but not send pause frames).
1564 * 2: Tx flow control is enabled (we can send pause frames
1565 * but we do not support receiving pause frames).
1566 * 3: Both Rx and TX flow control (symmetric) are enabled.
1567 * other: No software override. The flow control configuration
1568 * in the EEPROM is used.
1571 case e1000_fc_none
: /* 0 */
1572 /* Flow control (RX & TX) is completely disabled by a
1573 * software over-ride.
1575 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1577 case e1000_fc_rx_pause
: /* 1 */
1578 /* RX Flow control is enabled, and TX Flow control is
1579 * disabled, by a software over-ride.
1581 /* Since there really isn't a way to advertise that we are
1582 * capable of RX Pause ONLY, we will advertise that we
1583 * support both symmetric and asymmetric RX PAUSE. Later
1584 * (in e1000_config_fc_after_link_up) we will disable the
1585 *hw's ability to send PAUSE frames.
1587 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1589 case e1000_fc_tx_pause
: /* 2 */
1590 /* TX Flow control is enabled, and RX Flow control is
1591 * disabled, by a software over-ride.
1593 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1594 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1596 case e1000_fc_full
: /* 3 */
1597 /* Flow control (both RX and TX) is enabled by a software
1600 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1603 DEBUGOUT("Flow control param set incorrectly\n");
1604 return -E1000_ERR_CONFIG
;
1607 ret_val
= e1000_write_phy_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1611 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1613 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1617 return E1000_SUCCESS
;
1620 /******************************************************************************
1621 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1623 * hw - Struct containing variables accessed by shared code
1624 ******************************************************************************/
1626 e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1630 uint16_t mii_ctrl_reg
;
1631 uint16_t mii_status_reg
;
1635 DEBUGFUNC("e1000_phy_force_speed_duplex");
1637 /* Turn off Flow control if we are forcing speed and duplex. */
1638 hw
->fc
= e1000_fc_none
;
1640 DEBUGOUT1("hw->fc = %d\n", hw
->fc
);
1642 /* Read the Device Control Register. */
1643 ctrl
= E1000_READ_REG(hw
, CTRL
);
1645 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1646 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1647 ctrl
&= ~(DEVICE_SPEED_MASK
);
1649 /* Clear the Auto Speed Detect Enable bit. */
1650 ctrl
&= ~E1000_CTRL_ASDE
;
1652 /* Read the MII Control Register. */
1653 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &mii_ctrl_reg
);
1657 /* We need to disable autoneg in order to force link and duplex. */
1659 mii_ctrl_reg
&= ~MII_CR_AUTO_NEG_EN
;
1661 /* Are we forcing Full or Half Duplex? */
1662 if(hw
->forced_speed_duplex
== e1000_100_full
||
1663 hw
->forced_speed_duplex
== e1000_10_full
) {
1664 /* We want to force full duplex so we SET the full duplex bits in the
1665 * Device and MII Control Registers.
1667 ctrl
|= E1000_CTRL_FD
;
1668 mii_ctrl_reg
|= MII_CR_FULL_DUPLEX
;
1669 DEBUGOUT("Full Duplex\n");
1671 /* We want to force half duplex so we CLEAR the full duplex bits in
1672 * the Device and MII Control Registers.
1674 ctrl
&= ~E1000_CTRL_FD
;
1675 mii_ctrl_reg
&= ~MII_CR_FULL_DUPLEX
;
1676 DEBUGOUT("Half Duplex\n");
1679 /* Are we forcing 100Mbps??? */
1680 if(hw
->forced_speed_duplex
== e1000_100_full
||
1681 hw
->forced_speed_duplex
== e1000_100_half
) {
1682 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1683 ctrl
|= E1000_CTRL_SPD_100
;
1684 mii_ctrl_reg
|= MII_CR_SPEED_100
;
1685 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1686 DEBUGOUT("Forcing 100mb ");
1688 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1689 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1690 mii_ctrl_reg
|= MII_CR_SPEED_10
;
1691 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1692 DEBUGOUT("Forcing 10mb ");
1695 e1000_config_collision_dist(hw
);
1697 /* Write the configured values back to the Device Control Reg. */
1698 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1700 if (hw
->phy_type
== e1000_phy_m88
) {
1701 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1705 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1706 * forced whenever speed are duplex are forced.
1708 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1709 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1713 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data
);
1715 /* Need to reset the PHY or these changes will be ignored */
1716 mii_ctrl_reg
|= MII_CR_RESET
;
1718 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1719 * forced whenever speed or duplex are forced.
1721 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1725 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1726 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1728 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1733 /* Write back the modified PHY MII control register. */
1734 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, mii_ctrl_reg
);
1740 /* The wait_autoneg_complete flag may be a little misleading here.
1741 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1742 * But we do want to delay for a period while forcing only so we
1743 * don't generate false No Link messages. So we will wait here
1744 * only if the user has set wait_autoneg_complete to 1, which is
1747 if(hw
->wait_autoneg_complete
) {
1748 /* We will wait for autoneg to complete. */
1749 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1752 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1753 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1754 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1757 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1761 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1765 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1769 (hw
->phy_type
== e1000_phy_m88
)) {
1770 /* We didn't get link. Reset the DSP and wait again for link. */
1771 ret_val
= e1000_phy_reset_dsp(hw
);
1773 DEBUGOUT("Error Resetting PHY DSP\n");
1777 /* This loop will early-out if the link condition has been met. */
1778 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1779 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1781 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1784 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1788 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1794 if (hw
->phy_type
== e1000_phy_m88
) {
1795 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1796 * Extended PHY Specific Control Register to 25MHz clock. This value
1797 * defaults back to a 2.5MHz clock when the PHY is reset.
1799 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1803 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1804 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1808 /* In addition, because of the s/w reset above, we need to enable CRS on
1809 * TX. This must be set for both full and half duplex operation.
1811 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1815 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1816 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1820 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
1822 (hw
->forced_speed_duplex
== e1000_10_full
||
1823 hw
->forced_speed_duplex
== e1000_10_half
)) {
1824 ret_val
= e1000_polarity_reversal_workaround(hw
);
1829 return E1000_SUCCESS
;
1832 /******************************************************************************
1833 * Sets the collision distance in the Transmit Control register
1835 * hw - Struct containing variables accessed by shared code
1837 * Link should have been established previously. Reads the speed and duplex
1838 * information from the Device Status register.
1839 ******************************************************************************/
1841 e1000_config_collision_dist(struct e1000_hw
*hw
)
1845 DEBUGFUNC("e1000_config_collision_dist");
1847 tctl
= E1000_READ_REG(hw
, TCTL
);
1849 tctl
&= ~E1000_TCTL_COLD
;
1850 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
1852 E1000_WRITE_REG(hw
, TCTL
, tctl
);
1853 E1000_WRITE_FLUSH(hw
);
1856 /******************************************************************************
1857 * Sets MAC speed and duplex settings to reflect the those in the PHY
1859 * hw - Struct containing variables accessed by shared code
1860 * mii_reg - data to write to the MII control register
1862 * The contents of the PHY register containing the needed information need to
1864 ******************************************************************************/
1866 e1000_config_mac_to_phy(struct e1000_hw
*hw
)
1872 DEBUGFUNC("e1000_config_mac_to_phy");
1874 /* 82544 or newer MAC, Auto Speed Detection takes care of
1875 * MAC speed/duplex configuration.*/
1876 if (hw
->mac_type
>= e1000_82544
)
1877 return E1000_SUCCESS
;
1879 /* Read the Device Control Register and set the bits to Force Speed
1882 ctrl
= E1000_READ_REG(hw
, CTRL
);
1883 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1884 ctrl
&= ~(E1000_CTRL_SPD_SEL
| E1000_CTRL_ILOS
);
1886 /* Set up duplex in the Device Control and Transmit Control
1887 * registers depending on negotiated values.
1889 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1893 if(phy_data
& M88E1000_PSSR_DPLX
)
1894 ctrl
|= E1000_CTRL_FD
;
1896 ctrl
&= ~E1000_CTRL_FD
;
1898 e1000_config_collision_dist(hw
);
1900 /* Set up speed in the Device Control register depending on
1901 * negotiated values.
1903 if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
1904 ctrl
|= E1000_CTRL_SPD_1000
;
1905 else if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
1906 ctrl
|= E1000_CTRL_SPD_100
;
1908 /* Write the configured values back to the Device Control Reg. */
1909 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1910 return E1000_SUCCESS
;
1913 /******************************************************************************
1914 * Forces the MAC's flow control settings.
1916 * hw - Struct containing variables accessed by shared code
1918 * Sets the TFCE and RFCE bits in the device control register to reflect
1919 * the adapter settings. TFCE and RFCE need to be explicitly set by
1920 * software when a Copper PHY is used because autonegotiation is managed
1921 * by the PHY rather than the MAC. Software must also configure these
1922 * bits when link is forced on a fiber connection.
1923 *****************************************************************************/
1925 e1000_force_mac_fc(struct e1000_hw
*hw
)
1929 DEBUGFUNC("e1000_force_mac_fc");
1931 /* Get the current configuration of the Device Control Register */
1932 ctrl
= E1000_READ_REG(hw
, CTRL
);
1934 /* Because we didn't get link via the internal auto-negotiation
1935 * mechanism (we either forced link or we got link via PHY
1936 * auto-neg), we have to manually enable/disable transmit an
1937 * receive flow control.
1939 * The "Case" statement below enables/disable flow control
1940 * according to the "hw->fc" parameter.
1942 * The possible values of the "fc" parameter are:
1943 * 0: Flow control is completely disabled
1944 * 1: Rx flow control is enabled (we can receive pause
1945 * frames but not send pause frames).
1946 * 2: Tx flow control is enabled (we can send pause frames
1947 * frames but we do not receive pause frames).
1948 * 3: Both Rx and TX flow control (symmetric) is enabled.
1949 * other: No other values should be possible at this point.
1954 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
1956 case e1000_fc_rx_pause
:
1957 ctrl
&= (~E1000_CTRL_TFCE
);
1958 ctrl
|= E1000_CTRL_RFCE
;
1960 case e1000_fc_tx_pause
:
1961 ctrl
&= (~E1000_CTRL_RFCE
);
1962 ctrl
|= E1000_CTRL_TFCE
;
1965 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
1968 DEBUGOUT("Flow control param set incorrectly\n");
1969 return -E1000_ERR_CONFIG
;
1972 /* Disable TX Flow Control for 82542 (rev 2.0) */
1973 if(hw
->mac_type
== e1000_82542_rev2_0
)
1974 ctrl
&= (~E1000_CTRL_TFCE
);
1976 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1977 return E1000_SUCCESS
;
1980 /******************************************************************************
1981 * Configures flow control settings after link is established
1983 * hw - Struct containing variables accessed by shared code
1985 * Should be called immediately after a valid link has been established.
1986 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1987 * and autonegotiation is enabled, the MAC flow control settings will be set
1988 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1989 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1990 *****************************************************************************/
1992 e1000_config_fc_after_link_up(struct e1000_hw
*hw
)
1995 uint16_t mii_status_reg
;
1996 uint16_t mii_nway_adv_reg
;
1997 uint16_t mii_nway_lp_ability_reg
;
2001 DEBUGFUNC("e1000_config_fc_after_link_up");
2003 /* Check for the case where we have fiber media and auto-neg failed
2004 * so we had to force link. In this case, we need to force the
2005 * configuration of the MAC to match the "fc" parameter.
2007 if(((hw
->media_type
== e1000_media_type_fiber
) && (hw
->autoneg_failed
)) ||
2008 ((hw
->media_type
== e1000_media_type_internal_serdes
) && (hw
->autoneg_failed
)) ||
2009 ((hw
->media_type
== e1000_media_type_copper
) && (!hw
->autoneg
))) {
2010 ret_val
= e1000_force_mac_fc(hw
);
2012 DEBUGOUT("Error forcing flow control settings\n");
2017 /* Check for the case where we have copper media and auto-neg is
2018 * enabled. In this case, we need to check and see if Auto-Neg
2019 * has completed, and if so, how the PHY and link partner has
2020 * flow control configured.
2022 if((hw
->media_type
== e1000_media_type_copper
) && hw
->autoneg
) {
2023 /* Read the MII Status Register and check to see if AutoNeg
2024 * has completed. We read this twice because this reg has
2025 * some "sticky" (latched) bits.
2027 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2030 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2034 if(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
) {
2035 /* The AutoNeg process has completed, so we now need to
2036 * read both the Auto Negotiation Advertisement Register
2037 * (Address 4) and the Auto_Negotiation Base Page Ability
2038 * Register (Address 5) to determine how flow control was
2041 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
,
2045 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
,
2046 &mii_nway_lp_ability_reg
);
2050 /* Two bits in the Auto Negotiation Advertisement Register
2051 * (Address 4) and two bits in the Auto Negotiation Base
2052 * Page Ability Register (Address 5) determine flow control
2053 * for both the PHY and the link partner. The following
2054 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2055 * 1999, describes these PAUSE resolution bits and how flow
2056 * control is determined based upon these settings.
2057 * NOTE: DC = Don't Care
2059 * LOCAL DEVICE | LINK PARTNER
2060 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2061 *-------|---------|-------|---------|--------------------
2062 * 0 | 0 | DC | DC | e1000_fc_none
2063 * 0 | 1 | 0 | DC | e1000_fc_none
2064 * 0 | 1 | 1 | 0 | e1000_fc_none
2065 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2066 * 1 | 0 | 0 | DC | e1000_fc_none
2067 * 1 | DC | 1 | DC | e1000_fc_full
2068 * 1 | 1 | 0 | 0 | e1000_fc_none
2069 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2072 /* Are both PAUSE bits set to 1? If so, this implies
2073 * Symmetric Flow Control is enabled at both ends. The
2074 * ASM_DIR bits are irrelevant per the spec.
2076 * For Symmetric Flow Control:
2078 * LOCAL DEVICE | LINK PARTNER
2079 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2080 *-------|---------|-------|---------|--------------------
2081 * 1 | DC | 1 | DC | e1000_fc_full
2084 if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2085 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
2086 /* Now we need to check if the user selected RX ONLY
2087 * of pause frames. In this case, we had to advertise
2088 * FULL flow control because we could not advertise RX
2089 * ONLY. Hence, we must now check to see if we need to
2090 * turn OFF the TRANSMISSION of PAUSE frames.
2092 if(hw
->original_fc
== e1000_fc_full
) {
2093 hw
->fc
= e1000_fc_full
;
2094 DEBUGOUT("Flow Control = FULL.\r\n");
2096 hw
->fc
= e1000_fc_rx_pause
;
2097 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2100 /* For receiving PAUSE frames ONLY.
2102 * LOCAL DEVICE | LINK PARTNER
2103 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2104 *-------|---------|-------|---------|--------------------
2105 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2108 else if(!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2109 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2110 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2111 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2112 hw
->fc
= e1000_fc_tx_pause
;
2113 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2115 /* For transmitting PAUSE frames ONLY.
2117 * LOCAL DEVICE | LINK PARTNER
2118 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2119 *-------|---------|-------|---------|--------------------
2120 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2123 else if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2124 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2125 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2126 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2127 hw
->fc
= e1000_fc_rx_pause
;
2128 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2130 /* Per the IEEE spec, at this point flow control should be
2131 * disabled. However, we want to consider that we could
2132 * be connected to a legacy switch that doesn't advertise
2133 * desired flow control, but can be forced on the link
2134 * partner. So if we advertised no flow control, that is
2135 * what we will resolve to. If we advertised some kind of
2136 * receive capability (Rx Pause Only or Full Flow Control)
2137 * and the link partner advertised none, we will configure
2138 * ourselves to enable Rx Flow Control only. We can do
2139 * this safely for two reasons: If the link partner really
2140 * didn't want flow control enabled, and we enable Rx, no
2141 * harm done since we won't be receiving any PAUSE frames
2142 * anyway. If the intent on the link partner was to have
2143 * flow control enabled, then by us enabling RX only, we
2144 * can at least receive pause frames and process them.
2145 * This is a good idea because in most cases, since we are
2146 * predominantly a server NIC, more times than not we will
2147 * be asked to delay transmission of packets than asking
2148 * our link partner to pause transmission of frames.
2150 else if((hw
->original_fc
== e1000_fc_none
||
2151 hw
->original_fc
== e1000_fc_tx_pause
) ||
2152 hw
->fc_strict_ieee
) {
2153 hw
->fc
= e1000_fc_none
;
2154 DEBUGOUT("Flow Control = NONE.\r\n");
2156 hw
->fc
= e1000_fc_rx_pause
;
2157 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2160 /* Now we need to do one last check... If we auto-
2161 * negotiated to HALF DUPLEX, flow control should not be
2162 * enabled per IEEE 802.3 spec.
2164 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2166 DEBUGOUT("Error getting link speed and duplex\n");
2170 if(duplex
== HALF_DUPLEX
)
2171 hw
->fc
= e1000_fc_none
;
2173 /* Now we call a subroutine to actually force the MAC
2174 * controller to use the correct flow control settings.
2176 ret_val
= e1000_force_mac_fc(hw
);
2178 DEBUGOUT("Error forcing flow control settings\n");
2182 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2185 return E1000_SUCCESS
;
2188 /******************************************************************************
2189 * Checks to see if the link status of the hardware has changed.
2191 * hw - Struct containing variables accessed by shared code
2193 * Called by any function that needs to check the link status of the adapter.
2194 *****************************************************************************/
2196 e1000_check_for_link(struct e1000_hw
*hw
)
2203 uint32_t signal
= 0;
2207 DEBUGFUNC("e1000_check_for_link");
2209 ctrl
= E1000_READ_REG(hw
, CTRL
);
2210 status
= E1000_READ_REG(hw
, STATUS
);
2212 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2213 * set when the optics detect a signal. On older adapters, it will be
2214 * cleared when there is a signal. This applies to fiber media only.
2216 if((hw
->media_type
== e1000_media_type_fiber
) ||
2217 (hw
->media_type
== e1000_media_type_internal_serdes
)) {
2218 rxcw
= E1000_READ_REG(hw
, RXCW
);
2220 if(hw
->media_type
== e1000_media_type_fiber
) {
2221 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
2222 if(status
& E1000_STATUS_LU
)
2223 hw
->get_link_status
= FALSE
;
2227 /* If we have a copper PHY then we only want to go out to the PHY
2228 * registers to see if Auto-Neg has completed and/or if our link
2229 * status has changed. The get_link_status flag will be set if we
2230 * receive a Link Status Change interrupt or we have Rx Sequence
2233 if((hw
->media_type
== e1000_media_type_copper
) && hw
->get_link_status
) {
2234 /* First we want to see if the MII Status Register reports
2235 * link. If so, then we want to get the current speed/duplex
2237 * Read the register twice since the link bit is sticky.
2239 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2242 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2246 if(phy_data
& MII_SR_LINK_STATUS
) {
2247 hw
->get_link_status
= FALSE
;
2248 /* Check if there was DownShift, must be checked immediately after
2250 e1000_check_downshift(hw
);
2252 /* If we are on 82544 or 82543 silicon and speed/duplex
2253 * are forced to 10H or 10F, then we will implement the polarity
2254 * reversal workaround. We disable interrupts first, and upon
2255 * returning, place the devices interrupt state to its previous
2256 * value except for the link status change interrupt which will
2257 * happen due to the execution of this workaround.
2260 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
2262 (hw
->forced_speed_duplex
== e1000_10_full
||
2263 hw
->forced_speed_duplex
== e1000_10_half
)) {
2264 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
2265 ret_val
= e1000_polarity_reversal_workaround(hw
);
2266 icr
= E1000_READ_REG(hw
, ICR
);
2267 E1000_WRITE_REG(hw
, ICS
, (icr
& ~E1000_ICS_LSC
));
2268 E1000_WRITE_REG(hw
, IMS
, IMS_ENABLE_MASK
);
2272 /* No link detected */
2273 e1000_config_dsp_after_link_change(hw
, FALSE
);
2277 /* If we are forcing speed/duplex, then we simply return since
2278 * we have already determined whether we have link or not.
2280 if(!hw
->autoneg
) return -E1000_ERR_CONFIG
;
2282 /* optimize the dsp settings for the igp phy */
2283 e1000_config_dsp_after_link_change(hw
, TRUE
);
2285 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2286 * have Si on board that is 82544 or newer, Auto
2287 * Speed Detection takes care of MAC speed/duplex
2288 * configuration. So we only need to configure Collision
2289 * Distance in the MAC. Otherwise, we need to force
2290 * speed/duplex on the MAC to the current PHY speed/duplex
2293 if(hw
->mac_type
>= e1000_82544
)
2294 e1000_config_collision_dist(hw
);
2296 ret_val
= e1000_config_mac_to_phy(hw
);
2298 DEBUGOUT("Error configuring MAC to PHY settings\n");
2303 /* Configure Flow Control now that Auto-Neg has completed. First, we
2304 * need to restore the desired flow control settings because we may
2305 * have had to re-autoneg with a different link partner.
2307 ret_val
= e1000_config_fc_after_link_up(hw
);
2309 DEBUGOUT("Error configuring flow control\n");
2313 /* At this point we know that we are on copper and we have
2314 * auto-negotiated link. These are conditions for checking the link
2315 * partner capability register. We use the link speed to determine if
2316 * TBI compatibility needs to be turned on or off. If the link is not
2317 * at gigabit speed, then TBI compatibility is not needed. If we are
2318 * at gigabit speed, we turn on TBI compatibility.
2320 if(hw
->tbi_compatibility_en
) {
2321 uint16_t speed
, duplex
;
2322 e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2323 if(speed
!= SPEED_1000
) {
2324 /* If link speed is not set to gigabit speed, we do not need
2325 * to enable TBI compatibility.
2327 if(hw
->tbi_compatibility_on
) {
2328 /* If we previously were in the mode, turn it off. */
2329 rctl
= E1000_READ_REG(hw
, RCTL
);
2330 rctl
&= ~E1000_RCTL_SBP
;
2331 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2332 hw
->tbi_compatibility_on
= FALSE
;
2335 /* If TBI compatibility is was previously off, turn it on. For
2336 * compatibility with a TBI link partner, we will store bad
2337 * packets. Some frames have an additional byte on the end and
2338 * will look like CRC errors to to the hardware.
2340 if(!hw
->tbi_compatibility_on
) {
2341 hw
->tbi_compatibility_on
= TRUE
;
2342 rctl
= E1000_READ_REG(hw
, RCTL
);
2343 rctl
|= E1000_RCTL_SBP
;
2344 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2349 /* If we don't have link (auto-negotiation failed or link partner cannot
2350 * auto-negotiate), the cable is plugged in (we have signal), and our
2351 * link partner is not trying to auto-negotiate with us (we are receiving
2352 * idles or data), we need to force link up. We also need to give
2353 * auto-negotiation time to complete, in case the cable was just plugged
2354 * in. The autoneg_failed flag does this.
2356 else if((((hw
->media_type
== e1000_media_type_fiber
) &&
2357 ((ctrl
& E1000_CTRL_SWDPIN1
) == signal
)) ||
2358 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2359 (!(status
& E1000_STATUS_LU
)) &&
2360 (!(rxcw
& E1000_RXCW_C
))) {
2361 if(hw
->autoneg_failed
== 0) {
2362 hw
->autoneg_failed
= 1;
2365 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2367 /* Disable auto-negotiation in the TXCW register */
2368 E1000_WRITE_REG(hw
, TXCW
, (hw
->txcw
& ~E1000_TXCW_ANE
));
2370 /* Force link-up and also force full-duplex. */
2371 ctrl
= E1000_READ_REG(hw
, CTRL
);
2372 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
2373 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2375 /* Configure Flow Control after forcing link up. */
2376 ret_val
= e1000_config_fc_after_link_up(hw
);
2378 DEBUGOUT("Error configuring flow control\n");
2382 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2383 * auto-negotiation in the TXCW register and disable forced link in the
2384 * Device Control register in an attempt to auto-negotiate with our link
2387 else if(((hw
->media_type
== e1000_media_type_fiber
) ||
2388 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2389 (ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
2390 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2391 E1000_WRITE_REG(hw
, TXCW
, hw
->txcw
);
2392 E1000_WRITE_REG(hw
, CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
2394 hw
->serdes_link_down
= FALSE
;
2396 /* If we force link for non-auto-negotiation switch, check link status
2397 * based on MAC synchronization for internal serdes media type.
2399 else if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2400 !(E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2401 /* SYNCH bit and IV bit are sticky. */
2403 if(E1000_RXCW_SYNCH
& E1000_READ_REG(hw
, RXCW
)) {
2404 if(!(rxcw
& E1000_RXCW_IV
)) {
2405 hw
->serdes_link_down
= FALSE
;
2406 DEBUGOUT("SERDES: Link is up.\n");
2409 hw
->serdes_link_down
= TRUE
;
2410 DEBUGOUT("SERDES: Link is down.\n");
2413 if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2414 (E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2415 hw
->serdes_link_down
= !(E1000_STATUS_LU
& E1000_READ_REG(hw
, STATUS
));
2417 return E1000_SUCCESS
;
2420 /******************************************************************************
2421 * Detects the current speed and duplex settings of the hardware.
2423 * hw - Struct containing variables accessed by shared code
2424 * speed - Speed of the connection
2425 * duplex - Duplex setting of the connection
2426 *****************************************************************************/
2428 e1000_get_speed_and_duplex(struct e1000_hw
*hw
,
2436 DEBUGFUNC("e1000_get_speed_and_duplex");
2438 if(hw
->mac_type
>= e1000_82543
) {
2439 status
= E1000_READ_REG(hw
, STATUS
);
2440 if(status
& E1000_STATUS_SPEED_1000
) {
2441 *speed
= SPEED_1000
;
2442 DEBUGOUT("1000 Mbs, ");
2443 } else if(status
& E1000_STATUS_SPEED_100
) {
2445 DEBUGOUT("100 Mbs, ");
2448 DEBUGOUT("10 Mbs, ");
2451 if(status
& E1000_STATUS_FD
) {
2452 *duplex
= FULL_DUPLEX
;
2453 DEBUGOUT("Full Duplex\r\n");
2455 *duplex
= HALF_DUPLEX
;
2456 DEBUGOUT(" Half Duplex\r\n");
2459 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2460 *speed
= SPEED_1000
;
2461 *duplex
= FULL_DUPLEX
;
2464 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2465 * if it is operating at half duplex. Here we set the duplex settings to
2466 * match the duplex in the link partner's capabilities.
2468 if(hw
->phy_type
== e1000_phy_igp
&& hw
->speed_downgraded
) {
2469 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_EXP
, &phy_data
);
2473 if(!(phy_data
& NWAY_ER_LP_NWAY_CAPS
))
2474 *duplex
= HALF_DUPLEX
;
2476 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
, &phy_data
);
2479 if((*speed
== SPEED_100
&& !(phy_data
& NWAY_LPAR_100TX_FD_CAPS
)) ||
2480 (*speed
== SPEED_10
&& !(phy_data
& NWAY_LPAR_10T_FD_CAPS
)))
2481 *duplex
= HALF_DUPLEX
;
2485 return E1000_SUCCESS
;
2488 /******************************************************************************
2489 * Blocks until autoneg completes or times out (~4.5 seconds)
2491 * hw - Struct containing variables accessed by shared code
2492 ******************************************************************************/
2494 e1000_wait_autoneg(struct e1000_hw
*hw
)
2500 DEBUGFUNC("e1000_wait_autoneg");
2501 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2503 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2504 for(i
= PHY_AUTO_NEG_TIME
; i
> 0; i
--) {
2505 /* Read the MII Status Register and wait for Auto-Neg
2506 * Complete bit to be set.
2508 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2511 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2514 if(phy_data
& MII_SR_AUTONEG_COMPLETE
) {
2515 return E1000_SUCCESS
;
2519 return E1000_SUCCESS
;
2522 /******************************************************************************
2523 * Raises the Management Data Clock
2525 * hw - Struct containing variables accessed by shared code
2526 * ctrl - Device control register's current value
2527 ******************************************************************************/
2529 e1000_raise_mdi_clk(struct e1000_hw
*hw
,
2532 /* Raise the clock input to the Management Data Clock (by setting the MDC
2533 * bit), and then delay 10 microseconds.
2535 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
| E1000_CTRL_MDC
));
2536 E1000_WRITE_FLUSH(hw
);
2540 /******************************************************************************
2541 * Lowers the Management Data Clock
2543 * hw - Struct containing variables accessed by shared code
2544 * ctrl - Device control register's current value
2545 ******************************************************************************/
2547 e1000_lower_mdi_clk(struct e1000_hw
*hw
,
2550 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2551 * bit), and then delay 10 microseconds.
2553 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
2554 E1000_WRITE_FLUSH(hw
);
2558 /******************************************************************************
2559 * Shifts data bits out to the PHY
2561 * hw - Struct containing variables accessed by shared code
2562 * data - Data to send out to the PHY
2563 * count - Number of bits to shift out
2565 * Bits are shifted out in MSB to LSB order.
2566 ******************************************************************************/
2568 e1000_shift_out_mdi_bits(struct e1000_hw
*hw
,
2575 /* We need to shift "count" number of bits out to the PHY. So, the value
2576 * in the "data" parameter will be shifted out to the PHY one bit at a
2577 * time. In order to do this, "data" must be broken down into bits.
2580 mask
<<= (count
- 1);
2582 ctrl
= E1000_READ_REG(hw
, CTRL
);
2584 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2585 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
2588 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2589 * then raising and lowering the Management Data Clock. A "0" is
2590 * shifted out to the PHY by setting the MDIO bit to "0" and then
2591 * raising and lowering the clock.
2593 if(data
& mask
) ctrl
|= E1000_CTRL_MDIO
;
2594 else ctrl
&= ~E1000_CTRL_MDIO
;
2596 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2597 E1000_WRITE_FLUSH(hw
);
2601 e1000_raise_mdi_clk(hw
, &ctrl
);
2602 e1000_lower_mdi_clk(hw
, &ctrl
);
2608 /******************************************************************************
2609 * Shifts data bits in from the PHY
2611 * hw - Struct containing variables accessed by shared code
2613 * Bits are shifted in in MSB to LSB order.
2614 ******************************************************************************/
2616 e1000_shift_in_mdi_bits(struct e1000_hw
*hw
)
2622 /* In order to read a register from the PHY, we need to shift in a total
2623 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2624 * to avoid contention on the MDIO pin when a read operation is performed.
2625 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2626 * by raising the input to the Management Data Clock (setting the MDC bit),
2627 * and then reading the value of the MDIO bit.
2629 ctrl
= E1000_READ_REG(hw
, CTRL
);
2631 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2632 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
2633 ctrl
&= ~E1000_CTRL_MDIO
;
2635 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2636 E1000_WRITE_FLUSH(hw
);
2638 /* Raise and Lower the clock before reading in the data. This accounts for
2639 * the turnaround bits. The first clock occurred when we clocked out the
2640 * last bit of the Register Address.
2642 e1000_raise_mdi_clk(hw
, &ctrl
);
2643 e1000_lower_mdi_clk(hw
, &ctrl
);
2645 for(data
= 0, i
= 0; i
< 16; i
++) {
2647 e1000_raise_mdi_clk(hw
, &ctrl
);
2648 ctrl
= E1000_READ_REG(hw
, CTRL
);
2649 /* Check to see if we shifted in a "1". */
2650 if(ctrl
& E1000_CTRL_MDIO
) data
|= 1;
2651 e1000_lower_mdi_clk(hw
, &ctrl
);
2654 e1000_raise_mdi_clk(hw
, &ctrl
);
2655 e1000_lower_mdi_clk(hw
, &ctrl
);
2660 /*****************************************************************************
2661 * Reads the value from a PHY register, if the value is on a specific non zero
2662 * page, sets the page first.
2663 * hw - Struct containing variables accessed by shared code
2664 * reg_addr - address of the PHY register to read
2665 ******************************************************************************/
2667 e1000_read_phy_reg(struct e1000_hw
*hw
,
2673 DEBUGFUNC("e1000_read_phy_reg");
2675 if((hw
->phy_type
== e1000_phy_igp
||
2676 hw
->phy_type
== e1000_phy_igp_2
) &&
2677 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2678 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2679 (uint16_t)reg_addr
);
2685 ret_val
= e1000_read_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2692 e1000_read_phy_reg_ex(struct e1000_hw
*hw
,
2698 const uint32_t phy_addr
= 1;
2700 DEBUGFUNC("e1000_read_phy_reg_ex");
2702 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2703 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2704 return -E1000_ERR_PARAM
;
2707 if(hw
->mac_type
> e1000_82543
) {
2708 /* Set up Op-code, Phy Address, and register address in the MDI
2709 * Control register. The MAC will take care of interfacing with the
2710 * PHY to retrieve the desired data.
2712 mdic
= ((reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2713 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2714 (E1000_MDIC_OP_READ
));
2716 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2718 /* Poll the ready bit to see if the MDI read completed */
2719 for(i
= 0; i
< 64; i
++) {
2721 mdic
= E1000_READ_REG(hw
, MDIC
);
2722 if(mdic
& E1000_MDIC_READY
) break;
2724 if(!(mdic
& E1000_MDIC_READY
)) {
2725 DEBUGOUT("MDI Read did not complete\n");
2726 return -E1000_ERR_PHY
;
2728 if(mdic
& E1000_MDIC_ERROR
) {
2729 DEBUGOUT("MDI Error\n");
2730 return -E1000_ERR_PHY
;
2732 *phy_data
= (uint16_t) mdic
;
2734 /* We must first send a preamble through the MDIO pin to signal the
2735 * beginning of an MII instruction. This is done by sending 32
2736 * consecutive "1" bits.
2738 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2740 /* Now combine the next few fields that are required for a read
2741 * operation. We use this method instead of calling the
2742 * e1000_shift_out_mdi_bits routine five different times. The format of
2743 * a MII read instruction consists of a shift out of 14 bits and is
2744 * defined as follows:
2745 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2746 * followed by a shift in of 18 bits. This first two bits shifted in
2747 * are TurnAround bits used to avoid contention on the MDIO pin when a
2748 * READ operation is performed. These two bits are thrown away
2749 * followed by a shift in of 16 bits which contains the desired data.
2751 mdic
= ((reg_addr
) | (phy_addr
<< 5) |
2752 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
2754 e1000_shift_out_mdi_bits(hw
, mdic
, 14);
2756 /* Now that we've shifted out the read command to the MII, we need to
2757 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2760 *phy_data
= e1000_shift_in_mdi_bits(hw
);
2762 return E1000_SUCCESS
;
2765 /******************************************************************************
2766 * Writes a value to a PHY register
2768 * hw - Struct containing variables accessed by shared code
2769 * reg_addr - address of the PHY register to write
2770 * data - data to write to the PHY
2771 ******************************************************************************/
2773 e1000_write_phy_reg(struct e1000_hw
*hw
,
2779 DEBUGFUNC("e1000_write_phy_reg");
2781 if((hw
->phy_type
== e1000_phy_igp
||
2782 hw
->phy_type
== e1000_phy_igp_2
) &&
2783 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2784 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2785 (uint16_t)reg_addr
);
2791 ret_val
= e1000_write_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2798 e1000_write_phy_reg_ex(struct e1000_hw
*hw
,
2804 const uint32_t phy_addr
= 1;
2806 DEBUGFUNC("e1000_write_phy_reg_ex");
2808 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2809 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2810 return -E1000_ERR_PARAM
;
2813 if(hw
->mac_type
> e1000_82543
) {
2814 /* Set up Op-code, Phy Address, register address, and data intended
2815 * for the PHY register in the MDI Control register. The MAC will take
2816 * care of interfacing with the PHY to send the desired data.
2818 mdic
= (((uint32_t) phy_data
) |
2819 (reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2820 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2821 (E1000_MDIC_OP_WRITE
));
2823 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2825 /* Poll the ready bit to see if the MDI read completed */
2826 for(i
= 0; i
< 640; i
++) {
2828 mdic
= E1000_READ_REG(hw
, MDIC
);
2829 if(mdic
& E1000_MDIC_READY
) break;
2831 if(!(mdic
& E1000_MDIC_READY
)) {
2832 DEBUGOUT("MDI Write did not complete\n");
2833 return -E1000_ERR_PHY
;
2836 /* We'll need to use the SW defined pins to shift the write command
2837 * out to the PHY. We first send a preamble to the PHY to signal the
2838 * beginning of the MII instruction. This is done by sending 32
2839 * consecutive "1" bits.
2841 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2843 /* Now combine the remaining required fields that will indicate a
2844 * write operation. We use this method instead of calling the
2845 * e1000_shift_out_mdi_bits routine for each field in the command. The
2846 * format of a MII write instruction is as follows:
2847 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2849 mdic
= ((PHY_TURNAROUND
) | (reg_addr
<< 2) | (phy_addr
<< 7) |
2850 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
2852 mdic
|= (uint32_t) phy_data
;
2854 e1000_shift_out_mdi_bits(hw
, mdic
, 32);
2857 return E1000_SUCCESS
;
2861 /******************************************************************************
2862 * Returns the PHY to the power-on reset state
2864 * hw - Struct containing variables accessed by shared code
2865 ******************************************************************************/
2867 e1000_phy_hw_reset(struct e1000_hw
*hw
)
2869 uint32_t ctrl
, ctrl_ext
;
2873 DEBUGFUNC("e1000_phy_hw_reset");
2875 /* In the case of the phy reset being blocked, it's not an error, we
2876 * simply return success without performing the reset. */
2877 ret_val
= e1000_check_phy_reset_block(hw
);
2879 return E1000_SUCCESS
;
2881 DEBUGOUT("Resetting Phy...\n");
2883 if(hw
->mac_type
> e1000_82543
) {
2884 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2885 * bit. Then, take it out of reset.
2887 ctrl
= E1000_READ_REG(hw
, CTRL
);
2888 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2889 E1000_WRITE_FLUSH(hw
);
2891 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2892 E1000_WRITE_FLUSH(hw
);
2894 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2895 * bit to put the PHY into reset. Then, take it out of reset.
2897 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
2898 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
2899 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
2900 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
2901 E1000_WRITE_FLUSH(hw
);
2903 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
2904 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
2905 E1000_WRITE_FLUSH(hw
);
2909 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
2910 /* Configure activity LED after PHY reset */
2911 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
2912 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
2913 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
2914 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
2917 /* Wait for FW to finish PHY configuration. */
2918 ret_val
= e1000_get_phy_cfg_done(hw
);
2923 /******************************************************************************
2926 * hw - Struct containing variables accessed by shared code
2928 * Sets bit 15 of the MII Control regiser
2929 ******************************************************************************/
2931 e1000_phy_reset(struct e1000_hw
*hw
)
2936 DEBUGFUNC("e1000_phy_reset");
2938 /* In the case of the phy reset being blocked, it's not an error, we
2939 * simply return success without performing the reset. */
2940 ret_val
= e1000_check_phy_reset_block(hw
);
2942 return E1000_SUCCESS
;
2944 switch (hw
->mac_type
) {
2945 case e1000_82541_rev_2
:
2946 ret_val
= e1000_phy_hw_reset(hw
);
2951 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
2955 phy_data
|= MII_CR_RESET
;
2956 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
2964 if(hw
->phy_type
== e1000_phy_igp
|| hw
->phy_type
== e1000_phy_igp_2
)
2965 e1000_phy_init_script(hw
);
2967 return E1000_SUCCESS
;
2970 /******************************************************************************
2971 * Probes the expected PHY address for known PHY IDs
2973 * hw - Struct containing variables accessed by shared code
2974 ******************************************************************************/
2976 e1000_detect_gig_phy(struct e1000_hw
*hw
)
2978 int32_t phy_init_status
, ret_val
;
2979 uint16_t phy_id_high
, phy_id_low
;
2980 boolean_t match
= FALSE
;
2982 DEBUGFUNC("e1000_detect_gig_phy");
2984 /* Read the PHY ID Registers to identify which PHY is onboard. */
2985 ret_val
= e1000_read_phy_reg(hw
, PHY_ID1
, &phy_id_high
);
2989 hw
->phy_id
= (uint32_t) (phy_id_high
<< 16);
2991 ret_val
= e1000_read_phy_reg(hw
, PHY_ID2
, &phy_id_low
);
2995 hw
->phy_id
|= (uint32_t) (phy_id_low
& PHY_REVISION_MASK
);
2996 hw
->phy_revision
= (uint32_t) phy_id_low
& ~PHY_REVISION_MASK
;
2998 switch(hw
->mac_type
) {
3000 if(hw
->phy_id
== M88E1000_E_PHY_ID
) match
= TRUE
;
3003 if(hw
->phy_id
== M88E1000_I_PHY_ID
) match
= TRUE
;
3007 case e1000_82545_rev_3
:
3009 case e1000_82546_rev_3
:
3010 if(hw
->phy_id
== M88E1011_I_PHY_ID
) match
= TRUE
;
3013 case e1000_82541_rev_2
:
3015 case e1000_82547_rev_2
:
3016 if(hw
->phy_id
== IGP01E1000_I_PHY_ID
) match
= TRUE
;
3019 if(hw
->phy_id
== M88E1111_I_PHY_ID
) match
= TRUE
;
3022 DEBUGOUT1("Invalid MAC type %d\n", hw
->mac_type
);
3023 return -E1000_ERR_CONFIG
;
3025 phy_init_status
= e1000_set_phy_type(hw
);
3027 if ((match
) && (phy_init_status
== E1000_SUCCESS
)) {
3028 DEBUGOUT1("PHY ID 0x%X detected\n", hw
->phy_id
);
3029 return E1000_SUCCESS
;
3031 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw
->phy_id
);
3032 return -E1000_ERR_PHY
;
3035 /******************************************************************************
3036 * Resets the PHY's DSP
3038 * hw - Struct containing variables accessed by shared code
3039 ******************************************************************************/
3041 e1000_phy_reset_dsp(struct e1000_hw
*hw
)
3044 DEBUGFUNC("e1000_phy_reset_dsp");
3047 ret_val
= e1000_write_phy_reg(hw
, 29, 0x001d);
3049 ret_val
= e1000_write_phy_reg(hw
, 30, 0x00c1);
3051 ret_val
= e1000_write_phy_reg(hw
, 30, 0x0000);
3053 ret_val
= E1000_SUCCESS
;
3059 /******************************************************************************
3060 * Get PHY information from various PHY registers for igp PHY only.
3062 * hw - Struct containing variables accessed by shared code
3063 * phy_info - PHY information structure
3064 ******************************************************************************/
3066 e1000_phy_igp_get_info(struct e1000_hw
*hw
,
3067 struct e1000_phy_info
*phy_info
)
3070 uint16_t phy_data
, polarity
, min_length
, max_length
, average
;
3072 DEBUGFUNC("e1000_phy_igp_get_info");
3074 /* The downshift status is checked only once, after link is established,
3075 * and it stored in the hw->speed_downgraded parameter. */
3076 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3078 /* IGP01E1000 does not need to support it. */
3079 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_normal
;
3081 /* IGP01E1000 always correct polarity reversal */
3082 phy_info
->polarity_correction
= e1000_polarity_reversal_enabled
;
3084 /* Check polarity status */
3085 ret_val
= e1000_check_polarity(hw
, &polarity
);
3089 phy_info
->cable_polarity
= polarity
;
3091 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &phy_data
);
3095 phy_info
->mdix_mode
= (phy_data
& IGP01E1000_PSSR_MDIX
) >>
3096 IGP01E1000_PSSR_MDIX_SHIFT
;
3098 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
3099 IGP01E1000_PSSR_SPEED_1000MBPS
) {
3100 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3101 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3105 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3106 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3107 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3108 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3110 /* Get cable length */
3111 ret_val
= e1000_get_cable_length(hw
, &min_length
, &max_length
);
3115 /* Translate to old method */
3116 average
= (max_length
+ min_length
) / 2;
3118 if(average
<= e1000_igp_cable_length_50
)
3119 phy_info
->cable_length
= e1000_cable_length_50
;
3120 else if(average
<= e1000_igp_cable_length_80
)
3121 phy_info
->cable_length
= e1000_cable_length_50_80
;
3122 else if(average
<= e1000_igp_cable_length_110
)
3123 phy_info
->cable_length
= e1000_cable_length_80_110
;
3124 else if(average
<= e1000_igp_cable_length_140
)
3125 phy_info
->cable_length
= e1000_cable_length_110_140
;
3127 phy_info
->cable_length
= e1000_cable_length_140
;
3130 return E1000_SUCCESS
;
3133 /******************************************************************************
3134 * Get PHY information from various PHY registers fot m88 PHY only.
3136 * hw - Struct containing variables accessed by shared code
3137 * phy_info - PHY information structure
3138 ******************************************************************************/
3140 e1000_phy_m88_get_info(struct e1000_hw
*hw
,
3141 struct e1000_phy_info
*phy_info
)
3144 uint16_t phy_data
, polarity
;
3146 DEBUGFUNC("e1000_phy_m88_get_info");
3148 /* The downshift status is checked only once, after link is established,
3149 * and it stored in the hw->speed_downgraded parameter. */
3150 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3152 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
3156 phy_info
->extended_10bt_distance
=
3157 (phy_data
& M88E1000_PSCR_10BT_EXT_DIST_ENABLE
) >>
3158 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT
;
3159 phy_info
->polarity_correction
=
3160 (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
) >>
3161 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT
;
3163 /* Check polarity status */
3164 ret_val
= e1000_check_polarity(hw
, &polarity
);
3167 phy_info
->cable_polarity
= polarity
;
3169 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
3173 phy_info
->mdix_mode
= (phy_data
& M88E1000_PSSR_MDIX
) >>
3174 M88E1000_PSSR_MDIX_SHIFT
;
3176 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
3177 /* Cable Length Estimation and Local/Remote Receiver Information
3178 * are only valid at 1000 Mbps.
3180 phy_info
->cable_length
= ((phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
3181 M88E1000_PSSR_CABLE_LENGTH_SHIFT
);
3183 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3187 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3188 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3190 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3191 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3194 return E1000_SUCCESS
;
3197 /******************************************************************************
3198 * Get PHY information from various PHY registers
3200 * hw - Struct containing variables accessed by shared code
3201 * phy_info - PHY information structure
3202 ******************************************************************************/
3204 e1000_phy_get_info(struct e1000_hw
*hw
,
3205 struct e1000_phy_info
*phy_info
)
3210 DEBUGFUNC("e1000_phy_get_info");
3212 phy_info
->cable_length
= e1000_cable_length_undefined
;
3213 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_undefined
;
3214 phy_info
->cable_polarity
= e1000_rev_polarity_undefined
;
3215 phy_info
->downshift
= e1000_downshift_undefined
;
3216 phy_info
->polarity_correction
= e1000_polarity_reversal_undefined
;
3217 phy_info
->mdix_mode
= e1000_auto_x_mode_undefined
;
3218 phy_info
->local_rx
= e1000_1000t_rx_status_undefined
;
3219 phy_info
->remote_rx
= e1000_1000t_rx_status_undefined
;
3221 if(hw
->media_type
!= e1000_media_type_copper
) {
3222 DEBUGOUT("PHY info is only valid for copper media\n");
3223 return -E1000_ERR_CONFIG
;
3226 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3230 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3234 if((phy_data
& MII_SR_LINK_STATUS
) != MII_SR_LINK_STATUS
) {
3235 DEBUGOUT("PHY info is only valid if link is up\n");
3236 return -E1000_ERR_CONFIG
;
3239 if(hw
->phy_type
== e1000_phy_igp
||
3240 hw
->phy_type
== e1000_phy_igp_2
)
3241 return e1000_phy_igp_get_info(hw
, phy_info
);
3243 return e1000_phy_m88_get_info(hw
, phy_info
);
3247 e1000_validate_mdi_setting(struct e1000_hw
*hw
)
3249 DEBUGFUNC("e1000_validate_mdi_settings");
3251 if(!hw
->autoneg
&& (hw
->mdix
== 0 || hw
->mdix
== 3)) {
3252 DEBUGOUT("Invalid MDI setting detected\n");
3254 return -E1000_ERR_CONFIG
;
3256 return E1000_SUCCESS
;
3260 /******************************************************************************
3261 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3264 * hw - Struct containing variables accessed by shared code
3265 *****************************************************************************/
3267 e1000_init_eeprom_params(struct e1000_hw
*hw
)
3269 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3270 uint32_t eecd
= E1000_READ_REG(hw
, EECD
);
3271 int32_t ret_val
= E1000_SUCCESS
;
3272 uint16_t eeprom_size
;
3274 DEBUGFUNC("e1000_init_eeprom_params");
3276 switch (hw
->mac_type
) {
3277 case e1000_82542_rev2_0
:
3278 case e1000_82542_rev2_1
:
3281 eeprom
->type
= e1000_eeprom_microwire
;
3282 eeprom
->word_size
= 64;
3283 eeprom
->opcode_bits
= 3;
3284 eeprom
->address_bits
= 6;
3285 eeprom
->delay_usec
= 50;
3286 eeprom
->use_eerd
= FALSE
;
3287 eeprom
->use_eewr
= FALSE
;
3291 case e1000_82545_rev_3
:
3293 case e1000_82546_rev_3
:
3294 eeprom
->type
= e1000_eeprom_microwire
;
3295 eeprom
->opcode_bits
= 3;
3296 eeprom
->delay_usec
= 50;
3297 if(eecd
& E1000_EECD_SIZE
) {
3298 eeprom
->word_size
= 256;
3299 eeprom
->address_bits
= 8;
3301 eeprom
->word_size
= 64;
3302 eeprom
->address_bits
= 6;
3304 eeprom
->use_eerd
= FALSE
;
3305 eeprom
->use_eewr
= FALSE
;
3308 case e1000_82541_rev_2
:
3310 case e1000_82547_rev_2
:
3311 if (eecd
& E1000_EECD_TYPE
) {
3312 eeprom
->type
= e1000_eeprom_spi
;
3313 eeprom
->opcode_bits
= 8;
3314 eeprom
->delay_usec
= 1;
3315 if (eecd
& E1000_EECD_ADDR_BITS
) {
3316 eeprom
->page_size
= 32;
3317 eeprom
->address_bits
= 16;
3319 eeprom
->page_size
= 8;
3320 eeprom
->address_bits
= 8;
3323 eeprom
->type
= e1000_eeprom_microwire
;
3324 eeprom
->opcode_bits
= 3;
3325 eeprom
->delay_usec
= 50;
3326 if (eecd
& E1000_EECD_ADDR_BITS
) {
3327 eeprom
->word_size
= 256;
3328 eeprom
->address_bits
= 8;
3330 eeprom
->word_size
= 64;
3331 eeprom
->address_bits
= 6;
3334 eeprom
->use_eerd
= FALSE
;
3335 eeprom
->use_eewr
= FALSE
;
3338 eeprom
->type
= e1000_eeprom_spi
;
3339 eeprom
->opcode_bits
= 8;
3340 eeprom
->delay_usec
= 1;
3341 if (eecd
& E1000_EECD_ADDR_BITS
) {
3342 eeprom
->page_size
= 32;
3343 eeprom
->address_bits
= 16;
3345 eeprom
->page_size
= 8;
3346 eeprom
->address_bits
= 8;
3348 eeprom
->use_eerd
= TRUE
;
3349 eeprom
->use_eewr
= TRUE
;
3350 if(e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
3351 eeprom
->type
= e1000_eeprom_flash
;
3352 eeprom
->word_size
= 2048;
3354 /* Ensure that the Autonomous FLASH update bit is cleared due to
3355 * Flash update issue on parts which use a FLASH for NVM. */
3356 eecd
&= ~E1000_EECD_AUPDEN
;
3357 E1000_WRITE_REG(hw
, EECD
, eecd
);
3364 if (eeprom
->type
== e1000_eeprom_spi
) {
3365 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3366 * 32KB (incremented by powers of 2).
3368 if(hw
->mac_type
<= e1000_82547_rev_2
) {
3369 /* Set to default value for initial eeprom read. */
3370 eeprom
->word_size
= 64;
3371 ret_val
= e1000_read_eeprom(hw
, EEPROM_CFG
, 1, &eeprom_size
);
3374 eeprom_size
= (eeprom_size
& EEPROM_SIZE_MASK
) >> EEPROM_SIZE_SHIFT
;
3375 /* 256B eeprom size was not supported in earlier hardware, so we
3376 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3377 * is never the result used in the shifting logic below. */
3381 eeprom_size
= (uint16_t)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
3382 E1000_EECD_SIZE_EX_SHIFT
);
3385 eeprom
->word_size
= 1 << (eeprom_size
+ EEPROM_WORD_SIZE_SHIFT
);
3390 /******************************************************************************
3391 * Raises the EEPROM's clock input.
3393 * hw - Struct containing variables accessed by shared code
3394 * eecd - EECD's current value
3395 *****************************************************************************/
3397 e1000_raise_ee_clk(struct e1000_hw
*hw
,
3400 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3401 * wait <delay> microseconds.
3403 *eecd
= *eecd
| E1000_EECD_SK
;
3404 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3405 E1000_WRITE_FLUSH(hw
);
3406 udelay(hw
->eeprom
.delay_usec
);
3409 /******************************************************************************
3410 * Lowers the EEPROM's clock input.
3412 * hw - Struct containing variables accessed by shared code
3413 * eecd - EECD's current value
3414 *****************************************************************************/
3416 e1000_lower_ee_clk(struct e1000_hw
*hw
,
3419 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3420 * wait 50 microseconds.
3422 *eecd
= *eecd
& ~E1000_EECD_SK
;
3423 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3424 E1000_WRITE_FLUSH(hw
);
3425 udelay(hw
->eeprom
.delay_usec
);
3428 /******************************************************************************
3429 * Shift data bits out to the EEPROM.
3431 * hw - Struct containing variables accessed by shared code
3432 * data - data to send to the EEPROM
3433 * count - number of bits to shift out
3434 *****************************************************************************/
3436 e1000_shift_out_ee_bits(struct e1000_hw
*hw
,
3440 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3444 /* We need to shift "count" bits out to the EEPROM. So, value in the
3445 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3446 * In order to do this, "data" must be broken down into bits.
3448 mask
= 0x01 << (count
- 1);
3449 eecd
= E1000_READ_REG(hw
, EECD
);
3450 if (eeprom
->type
== e1000_eeprom_microwire
) {
3451 eecd
&= ~E1000_EECD_DO
;
3452 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3453 eecd
|= E1000_EECD_DO
;
3456 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3457 * and then raising and then lowering the clock (the SK bit controls
3458 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3459 * by setting "DI" to "0" and then raising and then lowering the clock.
3461 eecd
&= ~E1000_EECD_DI
;
3464 eecd
|= E1000_EECD_DI
;
3466 E1000_WRITE_REG(hw
, EECD
, eecd
);
3467 E1000_WRITE_FLUSH(hw
);
3469 udelay(eeprom
->delay_usec
);
3471 e1000_raise_ee_clk(hw
, &eecd
);
3472 e1000_lower_ee_clk(hw
, &eecd
);
3478 /* We leave the "DI" bit set to "0" when we leave this routine. */
3479 eecd
&= ~E1000_EECD_DI
;
3480 E1000_WRITE_REG(hw
, EECD
, eecd
);
3483 /******************************************************************************
3484 * Shift data bits in from the EEPROM
3486 * hw - Struct containing variables accessed by shared code
3487 *****************************************************************************/
3489 e1000_shift_in_ee_bits(struct e1000_hw
*hw
,
3496 /* In order to read a register from the EEPROM, we need to shift 'count'
3497 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3498 * input to the EEPROM (setting the SK bit), and then reading the value of
3499 * the "DO" bit. During this "shifting in" process the "DI" bit should
3503 eecd
= E1000_READ_REG(hw
, EECD
);
3505 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
3508 for(i
= 0; i
< count
; i
++) {
3510 e1000_raise_ee_clk(hw
, &eecd
);
3512 eecd
= E1000_READ_REG(hw
, EECD
);
3514 eecd
&= ~(E1000_EECD_DI
);
3515 if(eecd
& E1000_EECD_DO
)
3518 e1000_lower_ee_clk(hw
, &eecd
);
3524 /******************************************************************************
3525 * Prepares EEPROM for access
3527 * hw - Struct containing variables accessed by shared code
3529 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3530 * function should be called before issuing a command to the EEPROM.
3531 *****************************************************************************/
3533 e1000_acquire_eeprom(struct e1000_hw
*hw
)
3535 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3538 DEBUGFUNC("e1000_acquire_eeprom");
3540 if(e1000_get_hw_eeprom_semaphore(hw
))
3541 return -E1000_ERR_EEPROM
;
3543 eecd
= E1000_READ_REG(hw
, EECD
);
3545 if (hw
->mac_type
!= e1000_82573
) {
3546 /* Request EEPROM Access */
3547 if(hw
->mac_type
> e1000_82544
) {
3548 eecd
|= E1000_EECD_REQ
;
3549 E1000_WRITE_REG(hw
, EECD
, eecd
);
3550 eecd
= E1000_READ_REG(hw
, EECD
);
3551 while((!(eecd
& E1000_EECD_GNT
)) &&
3552 (i
< E1000_EEPROM_GRANT_ATTEMPTS
)) {
3555 eecd
= E1000_READ_REG(hw
, EECD
);
3557 if(!(eecd
& E1000_EECD_GNT
)) {
3558 eecd
&= ~E1000_EECD_REQ
;
3559 E1000_WRITE_REG(hw
, EECD
, eecd
);
3560 DEBUGOUT("Could not acquire EEPROM grant\n");
3561 return -E1000_ERR_EEPROM
;
3566 /* Setup EEPROM for Read/Write */
3568 if (eeprom
->type
== e1000_eeprom_microwire
) {
3569 /* Clear SK and DI */
3570 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
3571 E1000_WRITE_REG(hw
, EECD
, eecd
);
3574 eecd
|= E1000_EECD_CS
;
3575 E1000_WRITE_REG(hw
, EECD
, eecd
);
3576 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3577 /* Clear SK and CS */
3578 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3579 E1000_WRITE_REG(hw
, EECD
, eecd
);
3583 return E1000_SUCCESS
;
3586 /******************************************************************************
3587 * Returns EEPROM to a "standby" state
3589 * hw - Struct containing variables accessed by shared code
3590 *****************************************************************************/
3592 e1000_standby_eeprom(struct e1000_hw
*hw
)
3594 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3597 eecd
= E1000_READ_REG(hw
, EECD
);
3599 if(eeprom
->type
== e1000_eeprom_microwire
) {
3600 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3601 E1000_WRITE_REG(hw
, EECD
, eecd
);
3602 E1000_WRITE_FLUSH(hw
);
3603 udelay(eeprom
->delay_usec
);
3606 eecd
|= E1000_EECD_SK
;
3607 E1000_WRITE_REG(hw
, EECD
, eecd
);
3608 E1000_WRITE_FLUSH(hw
);
3609 udelay(eeprom
->delay_usec
);
3612 eecd
|= E1000_EECD_CS
;
3613 E1000_WRITE_REG(hw
, EECD
, eecd
);
3614 E1000_WRITE_FLUSH(hw
);
3615 udelay(eeprom
->delay_usec
);
3618 eecd
&= ~E1000_EECD_SK
;
3619 E1000_WRITE_REG(hw
, EECD
, eecd
);
3620 E1000_WRITE_FLUSH(hw
);
3621 udelay(eeprom
->delay_usec
);
3622 } else if(eeprom
->type
== e1000_eeprom_spi
) {
3623 /* Toggle CS to flush commands */
3624 eecd
|= E1000_EECD_CS
;
3625 E1000_WRITE_REG(hw
, EECD
, eecd
);
3626 E1000_WRITE_FLUSH(hw
);
3627 udelay(eeprom
->delay_usec
);
3628 eecd
&= ~E1000_EECD_CS
;
3629 E1000_WRITE_REG(hw
, EECD
, eecd
);
3630 E1000_WRITE_FLUSH(hw
);
3631 udelay(eeprom
->delay_usec
);
3635 /******************************************************************************
3636 * Terminates a command by inverting the EEPROM's chip select pin
3638 * hw - Struct containing variables accessed by shared code
3639 *****************************************************************************/
3641 e1000_release_eeprom(struct e1000_hw
*hw
)
3645 DEBUGFUNC("e1000_release_eeprom");
3647 eecd
= E1000_READ_REG(hw
, EECD
);
3649 if (hw
->eeprom
.type
== e1000_eeprom_spi
) {
3650 eecd
|= E1000_EECD_CS
; /* Pull CS high */
3651 eecd
&= ~E1000_EECD_SK
; /* Lower SCK */
3653 E1000_WRITE_REG(hw
, EECD
, eecd
);
3655 udelay(hw
->eeprom
.delay_usec
);
3656 } else if(hw
->eeprom
.type
== e1000_eeprom_microwire
) {
3657 /* cleanup eeprom */
3659 /* CS on Microwire is active-high */
3660 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
3662 E1000_WRITE_REG(hw
, EECD
, eecd
);
3664 /* Rising edge of clock */
3665 eecd
|= E1000_EECD_SK
;
3666 E1000_WRITE_REG(hw
, EECD
, eecd
);
3667 E1000_WRITE_FLUSH(hw
);
3668 udelay(hw
->eeprom
.delay_usec
);
3670 /* Falling edge of clock */
3671 eecd
&= ~E1000_EECD_SK
;
3672 E1000_WRITE_REG(hw
, EECD
, eecd
);
3673 E1000_WRITE_FLUSH(hw
);
3674 udelay(hw
->eeprom
.delay_usec
);
3677 /* Stop requesting EEPROM access */
3678 if(hw
->mac_type
> e1000_82544
) {
3679 eecd
&= ~E1000_EECD_REQ
;
3680 E1000_WRITE_REG(hw
, EECD
, eecd
);
3683 e1000_put_hw_eeprom_semaphore(hw
);
3686 /******************************************************************************
3687 * Reads a 16 bit word from the EEPROM.
3689 * hw - Struct containing variables accessed by shared code
3690 *****************************************************************************/
3692 e1000_spi_eeprom_ready(struct e1000_hw
*hw
)
3694 uint16_t retry_count
= 0;
3695 uint8_t spi_stat_reg
;
3697 DEBUGFUNC("e1000_spi_eeprom_ready");
3699 /* Read "Status Register" repeatedly until the LSB is cleared. The
3700 * EEPROM will signal that the command has been completed by clearing
3701 * bit 0 of the internal status register. If it's not cleared within
3702 * 5 milliseconds, then error out.
3706 e1000_shift_out_ee_bits(hw
, EEPROM_RDSR_OPCODE_SPI
,
3707 hw
->eeprom
.opcode_bits
);
3708 spi_stat_reg
= (uint8_t)e1000_shift_in_ee_bits(hw
, 8);
3709 if (!(spi_stat_reg
& EEPROM_STATUS_RDY_SPI
))
3715 e1000_standby_eeprom(hw
);
3716 } while(retry_count
< EEPROM_MAX_RETRY_SPI
);
3718 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3719 * only 0-5mSec on 5V devices)
3721 if(retry_count
>= EEPROM_MAX_RETRY_SPI
) {
3722 DEBUGOUT("SPI EEPROM Status error\n");
3723 return -E1000_ERR_EEPROM
;
3726 return E1000_SUCCESS
;
3729 /******************************************************************************
3730 * Reads a 16 bit word from the EEPROM.
3732 * hw - Struct containing variables accessed by shared code
3733 * offset - offset of word in the EEPROM to read
3734 * data - word read from the EEPROM
3735 * words - number of words to read
3736 *****************************************************************************/
3738 e1000_read_eeprom(struct e1000_hw
*hw
,
3743 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3747 DEBUGFUNC("e1000_read_eeprom");
3749 /* A check for invalid values: offset too large, too many words, and not
3752 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
3754 DEBUGOUT("\"words\" parameter out of bounds\n");
3755 return -E1000_ERR_EEPROM
;
3758 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3761 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3762 (hw
->mac_type
!= e1000_82573
)) {
3763 /* Prepare the EEPROM for reading */
3764 if(e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
3765 return -E1000_ERR_EEPROM
;
3768 if(eeprom
->use_eerd
== TRUE
) {
3769 ret_val
= e1000_read_eeprom_eerd(hw
, offset
, words
, data
);
3770 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3771 (hw
->mac_type
!= e1000_82573
))
3772 e1000_release_eeprom(hw
);
3776 if(eeprom
->type
== e1000_eeprom_spi
) {
3778 uint8_t read_opcode
= EEPROM_READ_OPCODE_SPI
;
3780 if(e1000_spi_eeprom_ready(hw
)) {
3781 e1000_release_eeprom(hw
);
3782 return -E1000_ERR_EEPROM
;
3785 e1000_standby_eeprom(hw
);
3787 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3788 if((eeprom
->address_bits
== 8) && (offset
>= 128))
3789 read_opcode
|= EEPROM_A8_OPCODE_SPI
;
3791 /* Send the READ command (opcode + addr) */
3792 e1000_shift_out_ee_bits(hw
, read_opcode
, eeprom
->opcode_bits
);
3793 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
*2), eeprom
->address_bits
);
3795 /* Read the data. The address of the eeprom internally increments with
3796 * each byte (spi) being read, saving on the overhead of eeprom setup
3797 * and tear-down. The address counter will roll over if reading beyond
3798 * the size of the eeprom, thus allowing the entire memory to be read
3799 * starting from any offset. */
3800 for (i
= 0; i
< words
; i
++) {
3801 word_in
= e1000_shift_in_ee_bits(hw
, 16);
3802 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
3804 } else if(eeprom
->type
== e1000_eeprom_microwire
) {
3805 for (i
= 0; i
< words
; i
++) {
3806 /* Send the READ command (opcode + addr) */
3807 e1000_shift_out_ee_bits(hw
, EEPROM_READ_OPCODE_MICROWIRE
,
3808 eeprom
->opcode_bits
);
3809 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ i
),
3810 eeprom
->address_bits
);
3812 /* Read the data. For microwire, each word requires the overhead
3813 * of eeprom setup and tear-down. */
3814 data
[i
] = e1000_shift_in_ee_bits(hw
, 16);
3815 e1000_standby_eeprom(hw
);
3819 /* End this read operation */
3820 e1000_release_eeprom(hw
);
3822 return E1000_SUCCESS
;
3825 /******************************************************************************
3826 * Reads a 16 bit word from the EEPROM using the EERD register.
3828 * hw - Struct containing variables accessed by shared code
3829 * offset - offset of word in the EEPROM to read
3830 * data - word read from the EEPROM
3831 * words - number of words to read
3832 *****************************************************************************/
3834 e1000_read_eeprom_eerd(struct e1000_hw
*hw
,
3839 uint32_t i
, eerd
= 0;
3842 for (i
= 0; i
< words
; i
++) {
3843 eerd
= ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) +
3844 E1000_EEPROM_RW_REG_START
;
3846 E1000_WRITE_REG(hw
, EERD
, eerd
);
3847 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_READ
);
3852 data
[i
] = (E1000_READ_REG(hw
, EERD
) >> E1000_EEPROM_RW_REG_DATA
);
3859 /******************************************************************************
3860 * Writes a 16 bit word from the EEPROM using the EEWR register.
3862 * hw - Struct containing variables accessed by shared code
3863 * offset - offset of word in the EEPROM to read
3864 * data - word read from the EEPROM
3865 * words - number of words to read
3866 *****************************************************************************/
3868 e1000_write_eeprom_eewr(struct e1000_hw
*hw
,
3873 uint32_t register_value
= 0;
3877 for (i
= 0; i
< words
; i
++) {
3878 register_value
= (data
[i
] << E1000_EEPROM_RW_REG_DATA
) |
3879 ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) |
3880 E1000_EEPROM_RW_REG_START
;
3882 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
3887 E1000_WRITE_REG(hw
, EEWR
, register_value
);
3889 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
3899 /******************************************************************************
3900 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3902 * hw - Struct containing variables accessed by shared code
3903 *****************************************************************************/
3905 e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
)
3907 uint32_t attempts
= 100000;
3908 uint32_t i
, reg
= 0;
3909 int32_t done
= E1000_ERR_EEPROM
;
3911 for(i
= 0; i
< attempts
; i
++) {
3912 if(eerd
== E1000_EEPROM_POLL_READ
)
3913 reg
= E1000_READ_REG(hw
, EERD
);
3915 reg
= E1000_READ_REG(hw
, EEWR
);
3917 if(reg
& E1000_EEPROM_RW_REG_DONE
) {
3918 done
= E1000_SUCCESS
;
3927 /***************************************************************************
3928 * Description: Determines if the onboard NVM is FLASH or EEPROM.
3930 * hw - Struct containing variables accessed by shared code
3931 ****************************************************************************/
3933 e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
)
3937 if(hw
->mac_type
== e1000_82573
) {
3938 eecd
= E1000_READ_REG(hw
, EECD
);
3940 /* Isolate bits 15 & 16 */
3941 eecd
= ((eecd
>> 15) & 0x03);
3943 /* If both bits are set, device is Flash type */
3951 /******************************************************************************
3952 * Verifies that the EEPROM has a valid checksum
3954 * hw - Struct containing variables accessed by shared code
3956 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3957 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3959 *****************************************************************************/
3961 e1000_validate_eeprom_checksum(struct e1000_hw
*hw
)
3963 uint16_t checksum
= 0;
3964 uint16_t i
, eeprom_data
;
3966 DEBUGFUNC("e1000_validate_eeprom_checksum");
3968 if ((hw
->mac_type
== e1000_82573
) &&
3969 (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
)) {
3970 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
3971 * 10h-12h. Checksum may need to be fixed. */
3972 e1000_read_eeprom(hw
, 0x10, 1, &eeprom_data
);
3973 if ((eeprom_data
& 0x10) == 0) {
3974 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
3975 * has already been fixed. If the checksum is still wrong and this
3976 * bit is a 1, we need to return bad checksum. Otherwise, we need
3977 * to set this bit to a 1 and update the checksum. */
3978 e1000_read_eeprom(hw
, 0x23, 1, &eeprom_data
);
3979 if ((eeprom_data
& 0x8000) == 0) {
3980 eeprom_data
|= 0x8000;
3981 e1000_write_eeprom(hw
, 0x23, 1, &eeprom_data
);
3982 e1000_update_eeprom_checksum(hw
);
3987 for(i
= 0; i
< (EEPROM_CHECKSUM_REG
+ 1); i
++) {
3988 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
3989 DEBUGOUT("EEPROM Read Error\n");
3990 return -E1000_ERR_EEPROM
;
3992 checksum
+= eeprom_data
;
3995 if(checksum
== (uint16_t) EEPROM_SUM
)
3996 return E1000_SUCCESS
;
3998 DEBUGOUT("EEPROM Checksum Invalid\n");
3999 return -E1000_ERR_EEPROM
;
4003 /******************************************************************************
4004 * Calculates the EEPROM checksum and writes it to the EEPROM
4006 * hw - Struct containing variables accessed by shared code
4008 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4009 * Writes the difference to word offset 63 of the EEPROM.
4010 *****************************************************************************/
4012 e1000_update_eeprom_checksum(struct e1000_hw
*hw
)
4014 uint16_t checksum
= 0;
4015 uint16_t i
, eeprom_data
;
4017 DEBUGFUNC("e1000_update_eeprom_checksum");
4019 for(i
= 0; i
< EEPROM_CHECKSUM_REG
; i
++) {
4020 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4021 DEBUGOUT("EEPROM Read Error\n");
4022 return -E1000_ERR_EEPROM
;
4024 checksum
+= eeprom_data
;
4026 checksum
= (uint16_t) EEPROM_SUM
- checksum
;
4027 if(e1000_write_eeprom(hw
, EEPROM_CHECKSUM_REG
, 1, &checksum
) < 0) {
4028 DEBUGOUT("EEPROM Write Error\n");
4029 return -E1000_ERR_EEPROM
;
4030 } else if (hw
->eeprom
.type
== e1000_eeprom_flash
) {
4031 e1000_commit_shadow_ram(hw
);
4033 return E1000_SUCCESS
;
4036 /******************************************************************************
4037 * Parent function for writing words to the different EEPROM types.
4039 * hw - Struct containing variables accessed by shared code
4040 * offset - offset within the EEPROM to be written to
4041 * words - number of words to write
4042 * data - 16 bit word to be written to the EEPROM
4044 * If e1000_update_eeprom_checksum is not called after this function, the
4045 * EEPROM will most likely contain an invalid checksum.
4046 *****************************************************************************/
4048 e1000_write_eeprom(struct e1000_hw
*hw
,
4053 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4056 DEBUGFUNC("e1000_write_eeprom");
4058 /* A check for invalid values: offset too large, too many words, and not
4061 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
4063 DEBUGOUT("\"words\" parameter out of bounds\n");
4064 return -E1000_ERR_EEPROM
;
4067 /* 82573 reads only through eerd */
4068 if(eeprom
->use_eewr
== TRUE
)
4069 return e1000_write_eeprom_eewr(hw
, offset
, words
, data
);
4071 /* Prepare the EEPROM for writing */
4072 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
4073 return -E1000_ERR_EEPROM
;
4075 if(eeprom
->type
== e1000_eeprom_microwire
) {
4076 status
= e1000_write_eeprom_microwire(hw
, offset
, words
, data
);
4078 status
= e1000_write_eeprom_spi(hw
, offset
, words
, data
);
4082 /* Done with writing */
4083 e1000_release_eeprom(hw
);
4088 /******************************************************************************
4089 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4091 * hw - Struct containing variables accessed by shared code
4092 * offset - offset within the EEPROM to be written to
4093 * words - number of words to write
4094 * data - pointer to array of 8 bit words to be written to the EEPROM
4096 *****************************************************************************/
4098 e1000_write_eeprom_spi(struct e1000_hw
*hw
,
4103 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4106 DEBUGFUNC("e1000_write_eeprom_spi");
4108 while (widx
< words
) {
4109 uint8_t write_opcode
= EEPROM_WRITE_OPCODE_SPI
;
4111 if(e1000_spi_eeprom_ready(hw
)) return -E1000_ERR_EEPROM
;
4113 e1000_standby_eeprom(hw
);
4115 /* Send the WRITE ENABLE command (8 bit opcode ) */
4116 e1000_shift_out_ee_bits(hw
, EEPROM_WREN_OPCODE_SPI
,
4117 eeprom
->opcode_bits
);
4119 e1000_standby_eeprom(hw
);
4121 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4122 if((eeprom
->address_bits
== 8) && (offset
>= 128))
4123 write_opcode
|= EEPROM_A8_OPCODE_SPI
;
4125 /* Send the Write command (8-bit opcode + addr) */
4126 e1000_shift_out_ee_bits(hw
, write_opcode
, eeprom
->opcode_bits
);
4128 e1000_shift_out_ee_bits(hw
, (uint16_t)((offset
+ widx
)*2),
4129 eeprom
->address_bits
);
4133 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4134 while (widx
< words
) {
4135 uint16_t word_out
= data
[widx
];
4136 word_out
= (word_out
>> 8) | (word_out
<< 8);
4137 e1000_shift_out_ee_bits(hw
, word_out
, 16);
4140 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4141 * operation, while the smaller eeproms are capable of an 8-byte
4142 * PAGE WRITE operation. Break the inner loop to pass new address
4144 if((((offset
+ widx
)*2) % eeprom
->page_size
) == 0) {
4145 e1000_standby_eeprom(hw
);
4151 return E1000_SUCCESS
;
4154 /******************************************************************************
4155 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4157 * hw - Struct containing variables accessed by shared code
4158 * offset - offset within the EEPROM to be written to
4159 * words - number of words to write
4160 * data - pointer to array of 16 bit words to be written to the EEPROM
4162 *****************************************************************************/
4164 e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
4169 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4171 uint16_t words_written
= 0;
4174 DEBUGFUNC("e1000_write_eeprom_microwire");
4176 /* Send the write enable command to the EEPROM (3-bit opcode plus
4177 * 6/8-bit dummy address beginning with 11). It's less work to include
4178 * the 11 of the dummy address as part of the opcode than it is to shift
4179 * it over the correct number of bits for the address. This puts the
4180 * EEPROM into write/erase mode.
4182 e1000_shift_out_ee_bits(hw
, EEPROM_EWEN_OPCODE_MICROWIRE
,
4183 (uint16_t)(eeprom
->opcode_bits
+ 2));
4185 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4187 /* Prepare the EEPROM */
4188 e1000_standby_eeprom(hw
);
4190 while (words_written
< words
) {
4191 /* Send the Write command (3-bit opcode + addr) */
4192 e1000_shift_out_ee_bits(hw
, EEPROM_WRITE_OPCODE_MICROWIRE
,
4193 eeprom
->opcode_bits
);
4195 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ words_written
),
4196 eeprom
->address_bits
);
4199 e1000_shift_out_ee_bits(hw
, data
[words_written
], 16);
4201 /* Toggle the CS line. This in effect tells the EEPROM to execute
4202 * the previous command.
4204 e1000_standby_eeprom(hw
);
4206 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4207 * signal that the command has been completed by raising the DO signal.
4208 * If DO does not go high in 10 milliseconds, then error out.
4210 for(i
= 0; i
< 200; i
++) {
4211 eecd
= E1000_READ_REG(hw
, EECD
);
4212 if(eecd
& E1000_EECD_DO
) break;
4216 DEBUGOUT("EEPROM Write did not complete\n");
4217 return -E1000_ERR_EEPROM
;
4220 /* Recover from write */
4221 e1000_standby_eeprom(hw
);
4226 /* Send the write disable command to the EEPROM (3-bit opcode plus
4227 * 6/8-bit dummy address beginning with 10). It's less work to include
4228 * the 10 of the dummy address as part of the opcode than it is to shift
4229 * it over the correct number of bits for the address. This takes the
4230 * EEPROM out of write/erase mode.
4232 e1000_shift_out_ee_bits(hw
, EEPROM_EWDS_OPCODE_MICROWIRE
,
4233 (uint16_t)(eeprom
->opcode_bits
+ 2));
4235 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4237 return E1000_SUCCESS
;
4240 /******************************************************************************
4241 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4242 * in the eeprom cache and the non modified values in the currently active bank
4245 * hw - Struct containing variables accessed by shared code
4246 * offset - offset of word in the EEPROM to read
4247 * data - word read from the EEPROM
4248 * words - number of words to read
4249 *****************************************************************************/
4251 e1000_commit_shadow_ram(struct e1000_hw
*hw
)
4253 uint32_t attempts
= 100000;
4257 int32_t error
= E1000_SUCCESS
;
4259 /* The flop register will be used to determine if flash type is STM */
4260 flop
= E1000_READ_REG(hw
, FLOP
);
4262 if (hw
->mac_type
== e1000_82573
) {
4263 for (i
=0; i
< attempts
; i
++) {
4264 eecd
= E1000_READ_REG(hw
, EECD
);
4265 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4271 if (i
== attempts
) {
4272 return -E1000_ERR_EEPROM
;
4275 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4276 if ((flop
& 0xFF00) == E1000_STM_OPCODE
) {
4277 E1000_WRITE_REG(hw
, HICR
, E1000_HICR_FW_RESET
);
4280 /* Perform the flash update */
4281 E1000_WRITE_REG(hw
, EECD
, eecd
| E1000_EECD_FLUPD
);
4283 for (i
=0; i
< attempts
; i
++) {
4284 eecd
= E1000_READ_REG(hw
, EECD
);
4285 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4291 if (i
== attempts
) {
4292 return -E1000_ERR_EEPROM
;
4299 /******************************************************************************
4300 * Reads the adapter's part number from the EEPROM
4302 * hw - Struct containing variables accessed by shared code
4303 * part_num - Adapter's part number
4304 *****************************************************************************/
4306 e1000_read_part_num(struct e1000_hw
*hw
,
4309 uint16_t offset
= EEPROM_PBA_BYTE_1
;
4310 uint16_t eeprom_data
;
4312 DEBUGFUNC("e1000_read_part_num");
4314 /* Get word 0 from EEPROM */
4315 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4316 DEBUGOUT("EEPROM Read Error\n");
4317 return -E1000_ERR_EEPROM
;
4319 /* Save word 0 in upper half of part_num */
4320 *part_num
= (uint32_t) (eeprom_data
<< 16);
4322 /* Get word 1 from EEPROM */
4323 if(e1000_read_eeprom(hw
, ++offset
, 1, &eeprom_data
) < 0) {
4324 DEBUGOUT("EEPROM Read Error\n");
4325 return -E1000_ERR_EEPROM
;
4327 /* Save word 1 in lower half of part_num */
4328 *part_num
|= eeprom_data
;
4330 return E1000_SUCCESS
;
4333 /******************************************************************************
4334 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4335 * second function of dual function devices
4337 * hw - Struct containing variables accessed by shared code
4338 *****************************************************************************/
4340 e1000_read_mac_addr(struct e1000_hw
* hw
)
4343 uint16_t eeprom_data
, i
;
4345 DEBUGFUNC("e1000_read_mac_addr");
4347 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
+= 2) {
4349 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4350 DEBUGOUT("EEPROM Read Error\n");
4351 return -E1000_ERR_EEPROM
;
4353 hw
->perm_mac_addr
[i
] = (uint8_t) (eeprom_data
& 0x00FF);
4354 hw
->perm_mac_addr
[i
+1] = (uint8_t) (eeprom_data
>> 8);
4356 if(((hw
->mac_type
== e1000_82546
) || (hw
->mac_type
== e1000_82546_rev_3
)) &&
4357 (E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_FUNC_1
))
4358 hw
->perm_mac_addr
[5] ^= 0x01;
4360 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
++)
4361 hw
->mac_addr
[i
] = hw
->perm_mac_addr
[i
];
4362 return E1000_SUCCESS
;
4365 /******************************************************************************
4366 * Initializes receive address filters.
4368 * hw - Struct containing variables accessed by shared code
4370 * Places the MAC address in receive address register 0 and clears the rest
4371 * of the receive addresss registers. Clears the multicast table. Assumes
4372 * the receiver is in reset when the routine is called.
4373 *****************************************************************************/
4375 e1000_init_rx_addrs(struct e1000_hw
*hw
)
4380 DEBUGFUNC("e1000_init_rx_addrs");
4382 /* Setup the receive address. */
4383 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4385 e1000_rar_set(hw
, hw
->mac_addr
, 0);
4387 rar_num
= E1000_RAR_ENTRIES
;
4388 /* Zero out the other 15 receive addresses. */
4389 DEBUGOUT("Clearing RAR[1-15]\n");
4390 for(i
= 1; i
< rar_num
; i
++) {
4391 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4392 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4396 /******************************************************************************
4397 * Updates the MAC's list of multicast addresses.
4399 * hw - Struct containing variables accessed by shared code
4400 * mc_addr_list - the list of new multicast addresses
4401 * mc_addr_count - number of addresses
4402 * pad - number of bytes between addresses in the list
4403 * rar_used_count - offset where to start adding mc addresses into the RAR's
4405 * The given list replaces any existing list. Clears the last 15 receive
4406 * address registers and the multicast table. Uses receive address registers
4407 * for the first 15 multicast addresses, and hashes the rest into the
4409 *****************************************************************************/
4411 e1000_mc_addr_list_update(struct e1000_hw
*hw
,
4412 uint8_t *mc_addr_list
,
4413 uint32_t mc_addr_count
,
4415 uint32_t rar_used_count
)
4417 uint32_t hash_value
;
4419 uint32_t num_rar_entry
;
4420 uint32_t num_mta_entry
;
4422 DEBUGFUNC("e1000_mc_addr_list_update");
4424 /* Set the new number of MC addresses that we are being requested to use. */
4425 hw
->num_mc_addrs
= mc_addr_count
;
4427 /* Clear RAR[1-15] */
4428 DEBUGOUT(" Clearing RAR[1-15]\n");
4429 num_rar_entry
= E1000_RAR_ENTRIES
;
4430 for(i
= rar_used_count
; i
< num_rar_entry
; i
++) {
4431 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4432 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4436 DEBUGOUT(" Clearing MTA\n");
4437 num_mta_entry
= E1000_NUM_MTA_REGISTERS
;
4438 for(i
= 0; i
< num_mta_entry
; i
++) {
4439 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
4442 /* Add the new addresses */
4443 for(i
= 0; i
< mc_addr_count
; i
++) {
4444 DEBUGOUT(" Adding the multicast addresses:\n");
4445 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
4446 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)],
4447 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 1],
4448 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 2],
4449 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 3],
4450 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 4],
4451 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 5]);
4453 hash_value
= e1000_hash_mc_addr(hw
,
4455 (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)));
4457 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
4459 /* Place this multicast address in the RAR if there is room, *
4460 * else put it in the MTA
4462 if (rar_used_count
< num_rar_entry
) {
4464 mc_addr_list
+ (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)),
4468 e1000_mta_set(hw
, hash_value
);
4471 DEBUGOUT("MC Update Complete\n");
4474 /******************************************************************************
4475 * Hashes an address to determine its location in the multicast table
4477 * hw - Struct containing variables accessed by shared code
4478 * mc_addr - the multicast address to hash
4479 *****************************************************************************/
4481 e1000_hash_mc_addr(struct e1000_hw
*hw
,
4484 uint32_t hash_value
= 0;
4486 /* The portion of the address that is used for the hash table is
4487 * determined by the mc_filter_type setting.
4489 switch (hw
->mc_filter_type
) {
4490 /* [0] [1] [2] [3] [4] [5]
4495 /* [47:36] i.e. 0x563 for above example address */
4496 hash_value
= ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
4499 /* [46:35] i.e. 0xAC6 for above example address */
4500 hash_value
= ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
4503 /* [45:34] i.e. 0x5D8 for above example address */
4504 hash_value
= ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
4507 /* [43:32] i.e. 0x634 for above example address */
4508 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
4512 hash_value
&= 0xFFF;
4517 /******************************************************************************
4518 * Sets the bit in the multicast table corresponding to the hash value.
4520 * hw - Struct containing variables accessed by shared code
4521 * hash_value - Multicast address hash value
4522 *****************************************************************************/
4524 e1000_mta_set(struct e1000_hw
*hw
,
4525 uint32_t hash_value
)
4527 uint32_t hash_bit
, hash_reg
;
4531 /* The MTA is a register array of 128 32-bit registers.
4532 * It is treated like an array of 4096 bits. We want to set
4533 * bit BitArray[hash_value]. So we figure out what register
4534 * the bit is in, read it, OR in the new bit, then write
4535 * back the new value. The register is determined by the
4536 * upper 7 bits of the hash value and the bit within that
4537 * register are determined by the lower 5 bits of the value.
4539 hash_reg
= (hash_value
>> 5) & 0x7F;
4540 hash_bit
= hash_value
& 0x1F;
4542 mta
= E1000_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
4544 mta
|= (1 << hash_bit
);
4546 /* If we are on an 82544 and we are trying to write an odd offset
4547 * in the MTA, save off the previous entry before writing and
4548 * restore the old value after writing.
4550 if((hw
->mac_type
== e1000_82544
) && ((hash_reg
& 0x1) == 1)) {
4551 temp
= E1000_READ_REG_ARRAY(hw
, MTA
, (hash_reg
- 1));
4552 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4553 E1000_WRITE_REG_ARRAY(hw
, MTA
, (hash_reg
- 1), temp
);
4555 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4559 /******************************************************************************
4560 * Puts an ethernet address into a receive address register.
4562 * hw - Struct containing variables accessed by shared code
4563 * addr - Address to put into receive address register
4564 * index - Receive address register to write
4565 *****************************************************************************/
4567 e1000_rar_set(struct e1000_hw
*hw
,
4571 uint32_t rar_low
, rar_high
;
4573 /* HW expects these in little endian so we reverse the byte order
4574 * from network order (big endian) to little endian
4576 rar_low
= ((uint32_t) addr
[0] |
4577 ((uint32_t) addr
[1] << 8) |
4578 ((uint32_t) addr
[2] << 16) | ((uint32_t) addr
[3] << 24));
4580 rar_high
= ((uint32_t) addr
[4] | ((uint32_t) addr
[5] << 8) | E1000_RAH_AV
);
4582 E1000_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
4583 E1000_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
4586 /******************************************************************************
4587 * Writes a value to the specified offset in the VLAN filter table.
4589 * hw - Struct containing variables accessed by shared code
4590 * offset - Offset in VLAN filer table to write
4591 * value - Value to write into VLAN filter table
4592 *****************************************************************************/
4594 e1000_write_vfta(struct e1000_hw
*hw
,
4600 if((hw
->mac_type
== e1000_82544
) && ((offset
& 0x1) == 1)) {
4601 temp
= E1000_READ_REG_ARRAY(hw
, VFTA
, (offset
- 1));
4602 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4603 E1000_WRITE_REG_ARRAY(hw
, VFTA
, (offset
- 1), temp
);
4605 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4609 /******************************************************************************
4610 * Clears the VLAN filer table
4612 * hw - Struct containing variables accessed by shared code
4613 *****************************************************************************/
4615 e1000_clear_vfta(struct e1000_hw
*hw
)
4618 uint32_t vfta_value
= 0;
4619 uint32_t vfta_offset
= 0;
4620 uint32_t vfta_bit_in_reg
= 0;
4622 if (hw
->mac_type
== e1000_82573
) {
4623 if (hw
->mng_cookie
.vlan_id
!= 0) {
4624 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4625 * ID. The following operations determine which 32b entry
4626 * (i.e. offset) into the array we want to set the VLAN ID
4627 * (i.e. bit) of the manageability unit. */
4628 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
4629 E1000_VFTA_ENTRY_SHIFT
) &
4630 E1000_VFTA_ENTRY_MASK
;
4631 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
4632 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
4635 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
4636 /* If the offset we want to clear is the same offset of the
4637 * manageability VLAN ID, then clear all bits except that of the
4638 * manageability unit */
4639 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
4640 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, vfta_value
);
4645 e1000_id_led_init(struct e1000_hw
* hw
)
4648 const uint32_t ledctl_mask
= 0x000000FF;
4649 const uint32_t ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
4650 const uint32_t ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
4651 uint16_t eeprom_data
, i
, temp
;
4652 const uint16_t led_mask
= 0x0F;
4654 DEBUGFUNC("e1000_id_led_init");
4656 if(hw
->mac_type
< e1000_82540
) {
4658 return E1000_SUCCESS
;
4661 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4662 hw
->ledctl_default
= ledctl
;
4663 hw
->ledctl_mode1
= hw
->ledctl_default
;
4664 hw
->ledctl_mode2
= hw
->ledctl_default
;
4666 if(e1000_read_eeprom(hw
, EEPROM_ID_LED_SETTINGS
, 1, &eeprom_data
) < 0) {
4667 DEBUGOUT("EEPROM Read Error\n");
4668 return -E1000_ERR_EEPROM
;
4670 if((eeprom_data
== ID_LED_RESERVED_0000
) ||
4671 (eeprom_data
== ID_LED_RESERVED_FFFF
)) eeprom_data
= ID_LED_DEFAULT
;
4672 for(i
= 0; i
< 4; i
++) {
4673 temp
= (eeprom_data
>> (i
<< 2)) & led_mask
;
4675 case ID_LED_ON1_DEF2
:
4676 case ID_LED_ON1_ON2
:
4677 case ID_LED_ON1_OFF2
:
4678 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4679 hw
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
4681 case ID_LED_OFF1_DEF2
:
4682 case ID_LED_OFF1_ON2
:
4683 case ID_LED_OFF1_OFF2
:
4684 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4685 hw
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
4692 case ID_LED_DEF1_ON2
:
4693 case ID_LED_ON1_ON2
:
4694 case ID_LED_OFF1_ON2
:
4695 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4696 hw
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
4698 case ID_LED_DEF1_OFF2
:
4699 case ID_LED_ON1_OFF2
:
4700 case ID_LED_OFF1_OFF2
:
4701 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4702 hw
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
4709 return E1000_SUCCESS
;
4712 /******************************************************************************
4713 * Prepares SW controlable LED for use and saves the current state of the LED.
4715 * hw - Struct containing variables accessed by shared code
4716 *****************************************************************************/
4718 e1000_setup_led(struct e1000_hw
*hw
)
4721 int32_t ret_val
= E1000_SUCCESS
;
4723 DEBUGFUNC("e1000_setup_led");
4725 switch(hw
->mac_type
) {
4726 case e1000_82542_rev2_0
:
4727 case e1000_82542_rev2_1
:
4730 /* No setup necessary */
4734 case e1000_82541_rev_2
:
4735 case e1000_82547_rev_2
:
4736 /* Turn off PHY Smart Power Down (if enabled) */
4737 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4738 &hw
->phy_spd_default
);
4741 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4742 (uint16_t)(hw
->phy_spd_default
&
4743 ~IGP01E1000_GMII_SPD
));
4748 if(hw
->media_type
== e1000_media_type_fiber
) {
4749 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4750 /* Save current LEDCTL settings */
4751 hw
->ledctl_default
= ledctl
;
4753 ledctl
&= ~(E1000_LEDCTL_LED0_IVRT
|
4754 E1000_LEDCTL_LED0_BLINK
|
4755 E1000_LEDCTL_LED0_MODE_MASK
);
4756 ledctl
|= (E1000_LEDCTL_MODE_LED_OFF
<<
4757 E1000_LEDCTL_LED0_MODE_SHIFT
);
4758 E1000_WRITE_REG(hw
, LEDCTL
, ledctl
);
4759 } else if(hw
->media_type
== e1000_media_type_copper
)
4760 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
4764 return E1000_SUCCESS
;
4767 /******************************************************************************
4768 * Restores the saved state of the SW controlable LED.
4770 * hw - Struct containing variables accessed by shared code
4771 *****************************************************************************/
4773 e1000_cleanup_led(struct e1000_hw
*hw
)
4775 int32_t ret_val
= E1000_SUCCESS
;
4777 DEBUGFUNC("e1000_cleanup_led");
4779 switch(hw
->mac_type
) {
4780 case e1000_82542_rev2_0
:
4781 case e1000_82542_rev2_1
:
4784 /* No cleanup necessary */
4788 case e1000_82541_rev_2
:
4789 case e1000_82547_rev_2
:
4790 /* Turn on PHY Smart Power Down (if previously enabled) */
4791 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4792 hw
->phy_spd_default
);
4797 /* Restore LEDCTL settings */
4798 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_default
);
4802 return E1000_SUCCESS
;
4805 /******************************************************************************
4806 * Turns on the software controllable LED
4808 * hw - Struct containing variables accessed by shared code
4809 *****************************************************************************/
4811 e1000_led_on(struct e1000_hw
*hw
)
4813 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
4815 DEBUGFUNC("e1000_led_on");
4817 switch(hw
->mac_type
) {
4818 case e1000_82542_rev2_0
:
4819 case e1000_82542_rev2_1
:
4821 /* Set SW Defineable Pin 0 to turn on the LED */
4822 ctrl
|= E1000_CTRL_SWDPIN0
;
4823 ctrl
|= E1000_CTRL_SWDPIO0
;
4826 if(hw
->media_type
== e1000_media_type_fiber
) {
4827 /* Set SW Defineable Pin 0 to turn on the LED */
4828 ctrl
|= E1000_CTRL_SWDPIN0
;
4829 ctrl
|= E1000_CTRL_SWDPIO0
;
4831 /* Clear SW Defineable Pin 0 to turn on the LED */
4832 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4833 ctrl
|= E1000_CTRL_SWDPIO0
;
4837 if(hw
->media_type
== e1000_media_type_fiber
) {
4838 /* Clear SW Defineable Pin 0 to turn on the LED */
4839 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4840 ctrl
|= E1000_CTRL_SWDPIO0
;
4841 } else if(hw
->media_type
== e1000_media_type_copper
) {
4842 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode2
);
4843 return E1000_SUCCESS
;
4848 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4850 return E1000_SUCCESS
;
4853 /******************************************************************************
4854 * Turns off the software controllable LED
4856 * hw - Struct containing variables accessed by shared code
4857 *****************************************************************************/
4859 e1000_led_off(struct e1000_hw
*hw
)
4861 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
4863 DEBUGFUNC("e1000_led_off");
4865 switch(hw
->mac_type
) {
4866 case e1000_82542_rev2_0
:
4867 case e1000_82542_rev2_1
:
4869 /* Clear SW Defineable Pin 0 to turn off the LED */
4870 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4871 ctrl
|= E1000_CTRL_SWDPIO0
;
4874 if(hw
->media_type
== e1000_media_type_fiber
) {
4875 /* Clear SW Defineable Pin 0 to turn off the LED */
4876 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4877 ctrl
|= E1000_CTRL_SWDPIO0
;
4879 /* Set SW Defineable Pin 0 to turn off the LED */
4880 ctrl
|= E1000_CTRL_SWDPIN0
;
4881 ctrl
|= E1000_CTRL_SWDPIO0
;
4885 if(hw
->media_type
== e1000_media_type_fiber
) {
4886 /* Set SW Defineable Pin 0 to turn off the LED */
4887 ctrl
|= E1000_CTRL_SWDPIN0
;
4888 ctrl
|= E1000_CTRL_SWDPIO0
;
4889 } else if(hw
->media_type
== e1000_media_type_copper
) {
4890 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
4891 return E1000_SUCCESS
;
4896 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4898 return E1000_SUCCESS
;
4901 /******************************************************************************
4902 * Clears all hardware statistics counters.
4904 * hw - Struct containing variables accessed by shared code
4905 *****************************************************************************/
4907 e1000_clear_hw_cntrs(struct e1000_hw
*hw
)
4909 volatile uint32_t temp
;
4911 temp
= E1000_READ_REG(hw
, CRCERRS
);
4912 temp
= E1000_READ_REG(hw
, SYMERRS
);
4913 temp
= E1000_READ_REG(hw
, MPC
);
4914 temp
= E1000_READ_REG(hw
, SCC
);
4915 temp
= E1000_READ_REG(hw
, ECOL
);
4916 temp
= E1000_READ_REG(hw
, MCC
);
4917 temp
= E1000_READ_REG(hw
, LATECOL
);
4918 temp
= E1000_READ_REG(hw
, COLC
);
4919 temp
= E1000_READ_REG(hw
, DC
);
4920 temp
= E1000_READ_REG(hw
, SEC
);
4921 temp
= E1000_READ_REG(hw
, RLEC
);
4922 temp
= E1000_READ_REG(hw
, XONRXC
);
4923 temp
= E1000_READ_REG(hw
, XONTXC
);
4924 temp
= E1000_READ_REG(hw
, XOFFRXC
);
4925 temp
= E1000_READ_REG(hw
, XOFFTXC
);
4926 temp
= E1000_READ_REG(hw
, FCRUC
);
4927 temp
= E1000_READ_REG(hw
, PRC64
);
4928 temp
= E1000_READ_REG(hw
, PRC127
);
4929 temp
= E1000_READ_REG(hw
, PRC255
);
4930 temp
= E1000_READ_REG(hw
, PRC511
);
4931 temp
= E1000_READ_REG(hw
, PRC1023
);
4932 temp
= E1000_READ_REG(hw
, PRC1522
);
4933 temp
= E1000_READ_REG(hw
, GPRC
);
4934 temp
= E1000_READ_REG(hw
, BPRC
);
4935 temp
= E1000_READ_REG(hw
, MPRC
);
4936 temp
= E1000_READ_REG(hw
, GPTC
);
4937 temp
= E1000_READ_REG(hw
, GORCL
);
4938 temp
= E1000_READ_REG(hw
, GORCH
);
4939 temp
= E1000_READ_REG(hw
, GOTCL
);
4940 temp
= E1000_READ_REG(hw
, GOTCH
);
4941 temp
= E1000_READ_REG(hw
, RNBC
);
4942 temp
= E1000_READ_REG(hw
, RUC
);
4943 temp
= E1000_READ_REG(hw
, RFC
);
4944 temp
= E1000_READ_REG(hw
, ROC
);
4945 temp
= E1000_READ_REG(hw
, RJC
);
4946 temp
= E1000_READ_REG(hw
, TORL
);
4947 temp
= E1000_READ_REG(hw
, TORH
);
4948 temp
= E1000_READ_REG(hw
, TOTL
);
4949 temp
= E1000_READ_REG(hw
, TOTH
);
4950 temp
= E1000_READ_REG(hw
, TPR
);
4951 temp
= E1000_READ_REG(hw
, TPT
);
4952 temp
= E1000_READ_REG(hw
, PTC64
);
4953 temp
= E1000_READ_REG(hw
, PTC127
);
4954 temp
= E1000_READ_REG(hw
, PTC255
);
4955 temp
= E1000_READ_REG(hw
, PTC511
);
4956 temp
= E1000_READ_REG(hw
, PTC1023
);
4957 temp
= E1000_READ_REG(hw
, PTC1522
);
4958 temp
= E1000_READ_REG(hw
, MPTC
);
4959 temp
= E1000_READ_REG(hw
, BPTC
);
4961 if(hw
->mac_type
< e1000_82543
) return;
4963 temp
= E1000_READ_REG(hw
, ALGNERRC
);
4964 temp
= E1000_READ_REG(hw
, RXERRC
);
4965 temp
= E1000_READ_REG(hw
, TNCRS
);
4966 temp
= E1000_READ_REG(hw
, CEXTERR
);
4967 temp
= E1000_READ_REG(hw
, TSCTC
);
4968 temp
= E1000_READ_REG(hw
, TSCTFC
);
4970 if(hw
->mac_type
<= e1000_82544
) return;
4972 temp
= E1000_READ_REG(hw
, MGTPRC
);
4973 temp
= E1000_READ_REG(hw
, MGTPDC
);
4974 temp
= E1000_READ_REG(hw
, MGTPTC
);
4976 if(hw
->mac_type
<= e1000_82547_rev_2
) return;
4978 temp
= E1000_READ_REG(hw
, IAC
);
4979 temp
= E1000_READ_REG(hw
, ICRXOC
);
4980 temp
= E1000_READ_REG(hw
, ICRXPTC
);
4981 temp
= E1000_READ_REG(hw
, ICRXATC
);
4982 temp
= E1000_READ_REG(hw
, ICTXPTC
);
4983 temp
= E1000_READ_REG(hw
, ICTXATC
);
4984 temp
= E1000_READ_REG(hw
, ICTXQEC
);
4985 temp
= E1000_READ_REG(hw
, ICTXQMTC
);
4986 temp
= E1000_READ_REG(hw
, ICRXDMTC
);
4990 /******************************************************************************
4991 * Resets Adaptive IFS to its default state.
4993 * hw - Struct containing variables accessed by shared code
4995 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4996 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4997 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4998 * before calling this function.
4999 *****************************************************************************/
5001 e1000_reset_adaptive(struct e1000_hw
*hw
)
5003 DEBUGFUNC("e1000_reset_adaptive");
5005 if(hw
->adaptive_ifs
) {
5006 if(!hw
->ifs_params_forced
) {
5007 hw
->current_ifs_val
= 0;
5008 hw
->ifs_min_val
= IFS_MIN
;
5009 hw
->ifs_max_val
= IFS_MAX
;
5010 hw
->ifs_step_size
= IFS_STEP
;
5011 hw
->ifs_ratio
= IFS_RATIO
;
5013 hw
->in_ifs_mode
= FALSE
;
5014 E1000_WRITE_REG(hw
, AIT
, 0);
5016 DEBUGOUT("Not in Adaptive IFS mode!\n");
5020 /******************************************************************************
5021 * Called during the callback/watchdog routine to update IFS value based on
5022 * the ratio of transmits to collisions.
5024 * hw - Struct containing variables accessed by shared code
5025 * tx_packets - Number of transmits since last callback
5026 * total_collisions - Number of collisions since last callback
5027 *****************************************************************************/
5029 e1000_update_adaptive(struct e1000_hw
*hw
)
5031 DEBUGFUNC("e1000_update_adaptive");
5033 if(hw
->adaptive_ifs
) {
5034 if((hw
->collision_delta
* hw
->ifs_ratio
) > hw
->tx_packet_delta
) {
5035 if(hw
->tx_packet_delta
> MIN_NUM_XMITS
) {
5036 hw
->in_ifs_mode
= TRUE
;
5037 if(hw
->current_ifs_val
< hw
->ifs_max_val
) {
5038 if(hw
->current_ifs_val
== 0)
5039 hw
->current_ifs_val
= hw
->ifs_min_val
;
5041 hw
->current_ifs_val
+= hw
->ifs_step_size
;
5042 E1000_WRITE_REG(hw
, AIT
, hw
->current_ifs_val
);
5046 if(hw
->in_ifs_mode
&& (hw
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
5047 hw
->current_ifs_val
= 0;
5048 hw
->in_ifs_mode
= FALSE
;
5049 E1000_WRITE_REG(hw
, AIT
, 0);
5053 DEBUGOUT("Not in Adaptive IFS mode!\n");
5057 /******************************************************************************
5058 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5060 * hw - Struct containing variables accessed by shared code
5061 * frame_len - The length of the frame in question
5062 * mac_addr - The Ethernet destination address of the frame in question
5063 *****************************************************************************/
5065 e1000_tbi_adjust_stats(struct e1000_hw
*hw
,
5066 struct e1000_hw_stats
*stats
,
5072 /* First adjust the frame length. */
5074 /* We need to adjust the statistics counters, since the hardware
5075 * counters overcount this packet as a CRC error and undercount
5076 * the packet as a good packet
5078 /* This packet should not be counted as a CRC error. */
5080 /* This packet does count as a Good Packet Received. */
5083 /* Adjust the Good Octets received counters */
5084 carry_bit
= 0x80000000 & stats
->gorcl
;
5085 stats
->gorcl
+= frame_len
;
5086 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5087 * Received Count) was one before the addition,
5088 * AND it is zero after, then we lost the carry out,
5089 * need to add one to Gorch (Good Octets Received Count High).
5090 * This could be simplified if all environments supported
5093 if(carry_bit
&& ((stats
->gorcl
& 0x80000000) == 0))
5095 /* Is this a broadcast or multicast? Check broadcast first,
5096 * since the test for a multicast frame will test positive on
5097 * a broadcast frame.
5099 if((mac_addr
[0] == (uint8_t) 0xff) && (mac_addr
[1] == (uint8_t) 0xff))
5100 /* Broadcast packet */
5102 else if(*mac_addr
& 0x01)
5103 /* Multicast packet */
5106 if(frame_len
== hw
->max_frame_size
) {
5107 /* In this case, the hardware has overcounted the number of
5114 /* Adjust the bin counters when the extra byte put the frame in the
5115 * wrong bin. Remember that the frame_len was adjusted above.
5117 if(frame_len
== 64) {
5120 } else if(frame_len
== 127) {
5123 } else if(frame_len
== 255) {
5126 } else if(frame_len
== 511) {
5129 } else if(frame_len
== 1023) {
5132 } else if(frame_len
== 1522) {
5137 /******************************************************************************
5138 * Gets the current PCI bus type, speed, and width of the hardware
5140 * hw - Struct containing variables accessed by shared code
5141 *****************************************************************************/
5143 e1000_get_bus_info(struct e1000_hw
*hw
)
5147 switch (hw
->mac_type
) {
5148 case e1000_82542_rev2_0
:
5149 case e1000_82542_rev2_1
:
5150 hw
->bus_type
= e1000_bus_type_unknown
;
5151 hw
->bus_speed
= e1000_bus_speed_unknown
;
5152 hw
->bus_width
= e1000_bus_width_unknown
;
5155 hw
->bus_type
= e1000_bus_type_pci_express
;
5156 hw
->bus_speed
= e1000_bus_speed_2500
;
5157 hw
->bus_width
= e1000_bus_width_pciex_4
;
5160 status
= E1000_READ_REG(hw
, STATUS
);
5161 hw
->bus_type
= (status
& E1000_STATUS_PCIX_MODE
) ?
5162 e1000_bus_type_pcix
: e1000_bus_type_pci
;
5164 if(hw
->device_id
== E1000_DEV_ID_82546EB_QUAD_COPPER
) {
5165 hw
->bus_speed
= (hw
->bus_type
== e1000_bus_type_pci
) ?
5166 e1000_bus_speed_66
: e1000_bus_speed_120
;
5167 } else if(hw
->bus_type
== e1000_bus_type_pci
) {
5168 hw
->bus_speed
= (status
& E1000_STATUS_PCI66
) ?
5169 e1000_bus_speed_66
: e1000_bus_speed_33
;
5171 switch (status
& E1000_STATUS_PCIX_SPEED
) {
5172 case E1000_STATUS_PCIX_SPEED_66
:
5173 hw
->bus_speed
= e1000_bus_speed_66
;
5175 case E1000_STATUS_PCIX_SPEED_100
:
5176 hw
->bus_speed
= e1000_bus_speed_100
;
5178 case E1000_STATUS_PCIX_SPEED_133
:
5179 hw
->bus_speed
= e1000_bus_speed_133
;
5182 hw
->bus_speed
= e1000_bus_speed_reserved
;
5186 hw
->bus_width
= (status
& E1000_STATUS_BUS64
) ?
5187 e1000_bus_width_64
: e1000_bus_width_32
;
5191 /******************************************************************************
5192 * Reads a value from one of the devices registers using port I/O (as opposed
5193 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5195 * hw - Struct containing variables accessed by shared code
5196 * offset - offset to read from
5197 *****************************************************************************/
5199 e1000_read_reg_io(struct e1000_hw
*hw
,
5202 unsigned long io_addr
= hw
->io_base
;
5203 unsigned long io_data
= hw
->io_base
+ 4;
5205 e1000_io_write(hw
, io_addr
, offset
);
5206 return e1000_io_read(hw
, io_data
);
5209 /******************************************************************************
5210 * Writes a value to one of the devices registers using port I/O (as opposed to
5211 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5213 * hw - Struct containing variables accessed by shared code
5214 * offset - offset to write to
5215 * value - value to write
5216 *****************************************************************************/
5218 e1000_write_reg_io(struct e1000_hw
*hw
,
5222 unsigned long io_addr
= hw
->io_base
;
5223 unsigned long io_data
= hw
->io_base
+ 4;
5225 e1000_io_write(hw
, io_addr
, offset
);
5226 e1000_io_write(hw
, io_data
, value
);
5230 /******************************************************************************
5231 * Estimates the cable length.
5233 * hw - Struct containing variables accessed by shared code
5234 * min_length - The estimated minimum length
5235 * max_length - The estimated maximum length
5237 * returns: - E1000_ERR_XXX
5240 * This function always returns a ranged length (minimum & maximum).
5241 * So for M88 phy's, this function interprets the one value returned from the
5242 * register to the minimum and maximum range.
5243 * For IGP phy's, the function calculates the range by the AGC registers.
5244 *****************************************************************************/
5246 e1000_get_cable_length(struct e1000_hw
*hw
,
5247 uint16_t *min_length
,
5248 uint16_t *max_length
)
5251 uint16_t agc_value
= 0;
5252 uint16_t cur_agc
, min_agc
= IGP01E1000_AGC_LENGTH_TABLE_SIZE
;
5253 uint16_t i
, phy_data
;
5254 uint16_t cable_length
;
5256 DEBUGFUNC("e1000_get_cable_length");
5258 *min_length
= *max_length
= 0;
5260 /* Use old method for Phy older than IGP */
5261 if(hw
->phy_type
== e1000_phy_m88
) {
5263 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5267 cable_length
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
5268 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
5270 /* Convert the enum value to ranged values */
5271 switch (cable_length
) {
5272 case e1000_cable_length_50
:
5274 *max_length
= e1000_igp_cable_length_50
;
5276 case e1000_cable_length_50_80
:
5277 *min_length
= e1000_igp_cable_length_50
;
5278 *max_length
= e1000_igp_cable_length_80
;
5280 case e1000_cable_length_80_110
:
5281 *min_length
= e1000_igp_cable_length_80
;
5282 *max_length
= e1000_igp_cable_length_110
;
5284 case e1000_cable_length_110_140
:
5285 *min_length
= e1000_igp_cable_length_110
;
5286 *max_length
= e1000_igp_cable_length_140
;
5288 case e1000_cable_length_140
:
5289 *min_length
= e1000_igp_cable_length_140
;
5290 *max_length
= e1000_igp_cable_length_170
;
5293 return -E1000_ERR_PHY
;
5296 } else if(hw
->phy_type
== e1000_phy_igp
) { /* For IGP PHY */
5297 uint16_t agc_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5298 {IGP01E1000_PHY_AGC_A
,
5299 IGP01E1000_PHY_AGC_B
,
5300 IGP01E1000_PHY_AGC_C
,
5301 IGP01E1000_PHY_AGC_D
};
5302 /* Read the AGC registers for all channels */
5303 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5305 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5309 cur_agc
= phy_data
>> IGP01E1000_AGC_LENGTH_SHIFT
;
5311 /* Array bound check. */
5312 if((cur_agc
>= IGP01E1000_AGC_LENGTH_TABLE_SIZE
- 1) ||
5314 return -E1000_ERR_PHY
;
5316 agc_value
+= cur_agc
;
5318 /* Update minimal AGC value. */
5319 if(min_agc
> cur_agc
)
5323 /* Remove the minimal AGC result for length < 50m */
5324 if(agc_value
< IGP01E1000_PHY_CHANNEL_NUM
* e1000_igp_cable_length_50
) {
5325 agc_value
-= min_agc
;
5327 /* Get the average length of the remaining 3 channels */
5328 agc_value
/= (IGP01E1000_PHY_CHANNEL_NUM
- 1);
5330 /* Get the average length of all the 4 channels. */
5331 agc_value
/= IGP01E1000_PHY_CHANNEL_NUM
;
5334 /* Set the range of the calculated length. */
5335 *min_length
= ((e1000_igp_cable_length_table
[agc_value
] -
5336 IGP01E1000_AGC_RANGE
) > 0) ?
5337 (e1000_igp_cable_length_table
[agc_value
] -
5338 IGP01E1000_AGC_RANGE
) : 0;
5339 *max_length
= e1000_igp_cable_length_table
[agc_value
] +
5340 IGP01E1000_AGC_RANGE
;
5343 return E1000_SUCCESS
;
5346 /******************************************************************************
5347 * Check the cable polarity
5349 * hw - Struct containing variables accessed by shared code
5350 * polarity - output parameter : 0 - Polarity is not reversed
5351 * 1 - Polarity is reversed.
5353 * returns: - E1000_ERR_XXX
5356 * For phy's older then IGP, this function simply reads the polarity bit in the
5357 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5358 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5359 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5360 * IGP01E1000_PHY_PCS_INIT_REG.
5361 *****************************************************************************/
5363 e1000_check_polarity(struct e1000_hw
*hw
,
5369 DEBUGFUNC("e1000_check_polarity");
5371 if(hw
->phy_type
== e1000_phy_m88
) {
5372 /* return the Polarity bit in the Status register. */
5373 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5377 *polarity
= (phy_data
& M88E1000_PSSR_REV_POLARITY
) >>
5378 M88E1000_PSSR_REV_POLARITY_SHIFT
;
5379 } else if(hw
->phy_type
== e1000_phy_igp
||
5380 hw
->phy_type
== e1000_phy_igp_2
) {
5381 /* Read the Status register to check the speed */
5382 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
5387 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5388 * find the polarity status */
5389 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
5390 IGP01E1000_PSSR_SPEED_1000MBPS
) {
5392 /* Read the GIG initialization PCS register (0x00B4) */
5393 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PCS_INIT_REG
,
5398 /* Check the polarity bits */
5399 *polarity
= (phy_data
& IGP01E1000_PHY_POLARITY_MASK
) ? 1 : 0;
5401 /* For 10 Mbps, read the polarity bit in the status register. (for
5402 * 100 Mbps this bit is always 0) */
5403 *polarity
= phy_data
& IGP01E1000_PSSR_POLARITY_REVERSED
;
5406 return E1000_SUCCESS
;
5409 /******************************************************************************
5410 * Check if Downshift occured
5412 * hw - Struct containing variables accessed by shared code
5413 * downshift - output parameter : 0 - No Downshift ocured.
5414 * 1 - Downshift ocured.
5416 * returns: - E1000_ERR_XXX
5419 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5420 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5421 * Link Health register. In IGP this bit is latched high, so the driver must
5422 * read it immediately after link is established.
5423 *****************************************************************************/
5425 e1000_check_downshift(struct e1000_hw
*hw
)
5430 DEBUGFUNC("e1000_check_downshift");
5432 if(hw
->phy_type
== e1000_phy_igp
||
5433 hw
->phy_type
== e1000_phy_igp_2
) {
5434 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_LINK_HEALTH
,
5439 hw
->speed_downgraded
= (phy_data
& IGP01E1000_PLHR_SS_DOWNGRADE
) ? 1 : 0;
5440 } else if(hw
->phy_type
== e1000_phy_m88
) {
5441 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5446 hw
->speed_downgraded
= (phy_data
& M88E1000_PSSR_DOWNSHIFT
) >>
5447 M88E1000_PSSR_DOWNSHIFT_SHIFT
;
5450 return E1000_SUCCESS
;
5453 /*****************************************************************************
5455 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5456 * gigabit link is achieved to improve link quality.
5458 * hw: Struct containing variables accessed by shared code
5460 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5461 * E1000_SUCCESS at any other case.
5463 ****************************************************************************/
5466 e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
5470 uint16_t phy_data
, phy_saved_data
, speed
, duplex
, i
;
5471 uint16_t dsp_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5472 {IGP01E1000_PHY_AGC_PARAM_A
,
5473 IGP01E1000_PHY_AGC_PARAM_B
,
5474 IGP01E1000_PHY_AGC_PARAM_C
,
5475 IGP01E1000_PHY_AGC_PARAM_D
};
5476 uint16_t min_length
, max_length
;
5478 DEBUGFUNC("e1000_config_dsp_after_link_change");
5480 if(hw
->phy_type
!= e1000_phy_igp
)
5481 return E1000_SUCCESS
;
5484 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
5486 DEBUGOUT("Error getting link speed and duplex\n");
5490 if(speed
== SPEED_1000
) {
5492 e1000_get_cable_length(hw
, &min_length
, &max_length
);
5494 if((hw
->dsp_config_state
== e1000_dsp_config_enabled
) &&
5495 min_length
>= e1000_igp_cable_length_50
) {
5497 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5498 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
],
5503 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5505 ret_val
= e1000_write_phy_reg(hw
, dsp_reg_array
[i
],
5510 hw
->dsp_config_state
= e1000_dsp_config_activated
;
5513 if((hw
->ffe_config_state
== e1000_ffe_config_enabled
) &&
5514 (min_length
< e1000_igp_cable_length_50
)) {
5516 uint16_t ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_20
;
5517 uint32_t idle_errs
= 0;
5519 /* clear previous idle error counts */
5520 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5525 for(i
= 0; i
< ffe_idle_err_timeout
; i
++) {
5527 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5532 idle_errs
+= (phy_data
& SR_1000T_IDLE_ERROR_CNT
);
5533 if(idle_errs
> SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT
) {
5534 hw
->ffe_config_state
= e1000_ffe_config_active
;
5536 ret_val
= e1000_write_phy_reg(hw
,
5537 IGP01E1000_PHY_DSP_FFE
,
5538 IGP01E1000_PHY_DSP_FFE_CM_CP
);
5545 ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_100
;
5550 if(hw
->dsp_config_state
== e1000_dsp_config_activated
) {
5551 /* Save off the current value of register 0x2F5B to be restored at
5552 * the end of the routines. */
5553 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5558 /* Disable the PHY transmitter */
5559 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5566 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5567 IGP01E1000_IEEE_FORCE_GIGA
);
5570 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5571 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
], &phy_data
);
5575 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5576 phy_data
|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS
;
5578 ret_val
= e1000_write_phy_reg(hw
,dsp_reg_array
[i
], phy_data
);
5583 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5584 IGP01E1000_IEEE_RESTART_AUTONEG
);
5590 /* Now enable the transmitter */
5591 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5596 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
5599 if(hw
->ffe_config_state
== e1000_ffe_config_active
) {
5600 /* Save off the current value of register 0x2F5B to be restored at
5601 * the end of the routines. */
5602 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5607 /* Disable the PHY transmitter */
5608 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5615 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5616 IGP01E1000_IEEE_FORCE_GIGA
);
5619 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_DSP_FFE
,
5620 IGP01E1000_PHY_DSP_FFE_DEFAULT
);
5624 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5625 IGP01E1000_IEEE_RESTART_AUTONEG
);
5631 /* Now enable the transmitter */
5632 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5637 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
5640 return E1000_SUCCESS
;
5643 /*****************************************************************************
5644 * Set PHY to class A mode
5645 * Assumes the following operations will follow to enable the new class mode.
5646 * 1. Do a PHY soft reset
5647 * 2. Restart auto-negotiation or force link.
5649 * hw - Struct containing variables accessed by shared code
5650 ****************************************************************************/
5652 e1000_set_phy_mode(struct e1000_hw
*hw
)
5655 uint16_t eeprom_data
;
5657 DEBUGFUNC("e1000_set_phy_mode");
5659 if((hw
->mac_type
== e1000_82545_rev_3
) &&
5660 (hw
->media_type
== e1000_media_type_copper
)) {
5661 ret_val
= e1000_read_eeprom(hw
, EEPROM_PHY_CLASS_WORD
, 1, &eeprom_data
);
5666 if((eeprom_data
!= EEPROM_RESERVED_WORD
) &&
5667 (eeprom_data
& EEPROM_PHY_CLASS_A
)) {
5668 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x000B);
5671 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x8104);
5675 hw
->phy_reset_disable
= FALSE
;
5679 return E1000_SUCCESS
;
5682 /*****************************************************************************
5684 * This function sets the lplu state according to the active flag. When
5685 * activating lplu this function also disables smart speed and vise versa.
5686 * lplu will not be activated unless the device autonegotiation advertisment
5687 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5688 * hw: Struct containing variables accessed by shared code
5689 * active - true to enable lplu false to disable lplu.
5691 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5692 * E1000_SUCCESS at any other case.
5694 ****************************************************************************/
5697 e1000_set_d3_lplu_state(struct e1000_hw
*hw
,
5702 DEBUGFUNC("e1000_set_d3_lplu_state");
5704 if(hw
->phy_type
!= e1000_phy_igp
&& hw
->phy_type
!= e1000_phy_igp_2
)
5705 return E1000_SUCCESS
;
5707 /* During driver activity LPLU should not be used or it will attain link
5708 * from the lowest speeds starting from 10Mbps. The capability is used for
5709 * Dx transitions and states */
5710 if(hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
) {
5711 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
, &phy_data
);
5715 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
5721 if(hw
->mac_type
== e1000_82541_rev_2
||
5722 hw
->mac_type
== e1000_82547_rev_2
) {
5723 phy_data
&= ~IGP01E1000_GMII_FLEX_SPD
;
5724 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5728 phy_data
&= ~IGP02E1000_PM_D3_LPLU
;
5729 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5735 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5736 * Dx states where the power conservation is most important. During
5737 * driver activity we should enable SmartSpeed, so performance is
5739 if (hw
->smart_speed
== e1000_smart_speed_on
) {
5740 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5745 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
5746 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5750 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
5751 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5756 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5757 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5763 } else if((hw
->autoneg_advertised
== AUTONEG_ADVERTISE_SPEED_DEFAULT
) ||
5764 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_ALL
) ||
5765 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_100_ALL
)) {
5767 if(hw
->mac_type
== e1000_82541_rev_2
||
5768 hw
->mac_type
== e1000_82547_rev_2
) {
5769 phy_data
|= IGP01E1000_GMII_FLEX_SPD
;
5770 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5774 phy_data
|= IGP02E1000_PM_D3_LPLU
;
5775 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5781 /* When LPLU is enabled we should disable SmartSpeed */
5782 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
5786 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5787 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
5792 return E1000_SUCCESS
;
5795 /*****************************************************************************
5797 * This function sets the lplu d0 state according to the active flag. When
5798 * activating lplu this function also disables smart speed and vise versa.
5799 * lplu will not be activated unless the device autonegotiation advertisment
5800 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5801 * hw: Struct containing variables accessed by shared code
5802 * active - true to enable lplu false to disable lplu.
5804 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5805 * E1000_SUCCESS at any other case.
5807 ****************************************************************************/
5810 e1000_set_d0_lplu_state(struct e1000_hw
*hw
,
5815 DEBUGFUNC("e1000_set_d0_lplu_state");
5817 if(hw
->mac_type
<= e1000_82547_rev_2
)
5818 return E1000_SUCCESS
;
5820 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
5825 phy_data
&= ~IGP02E1000_PM_D0_LPLU
;
5826 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
5830 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5831 * Dx states where the power conservation is most important. During
5832 * driver activity we should enable SmartSpeed, so performance is
5834 if (hw
->smart_speed
== e1000_smart_speed_on
) {
5835 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5840 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
5841 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5845 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
5846 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5851 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5852 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5861 phy_data
|= IGP02E1000_PM_D0_LPLU
;
5862 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
5866 /* When LPLU is enabled we should disable SmartSpeed */
5867 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
5871 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5872 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
5877 return E1000_SUCCESS
;
5880 /******************************************************************************
5881 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5883 * hw - Struct containing variables accessed by shared code
5884 *****************************************************************************/
5886 e1000_set_vco_speed(struct e1000_hw
*hw
)
5889 uint16_t default_page
= 0;
5892 DEBUGFUNC("e1000_set_vco_speed");
5894 switch(hw
->mac_type
) {
5895 case e1000_82545_rev_3
:
5896 case e1000_82546_rev_3
:
5899 return E1000_SUCCESS
;
5902 /* Set PHY register 30, page 5, bit 8 to 0 */
5904 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, &default_page
);
5908 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0005);
5912 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
5916 phy_data
&= ~M88E1000_PHY_VCO_REG_BIT8
;
5917 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
5921 /* Set PHY register 30, page 4, bit 11 to 1 */
5923 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0004);
5927 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
5931 phy_data
|= M88E1000_PHY_VCO_REG_BIT11
;
5932 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
5936 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, default_page
);
5940 return E1000_SUCCESS
;
5944 /*****************************************************************************
5945 * This function reads the cookie from ARC ram.
5947 * returns: - E1000_SUCCESS .
5948 ****************************************************************************/
5950 e1000_host_if_read_cookie(struct e1000_hw
* hw
, uint8_t *buffer
)
5953 uint32_t offset
= E1000_MNG_DHCP_COOKIE_OFFSET
;
5954 uint8_t length
= E1000_MNG_DHCP_COOKIE_LENGTH
;
5956 length
= (length
>> 2);
5957 offset
= (offset
>> 2);
5959 for (i
= 0; i
< length
; i
++) {
5960 *((uint32_t *) buffer
+ i
) =
5961 E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
);
5963 return E1000_SUCCESS
;
5967 /*****************************************************************************
5968 * This function checks whether the HOST IF is enabled for command operaton
5969 * and also checks whether the previous command is completed.
5970 * It busy waits in case of previous command is not completed.
5972 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5974 * - E1000_SUCCESS for success.
5975 ****************************************************************************/
5977 e1000_mng_enable_host_if(struct e1000_hw
* hw
)
5982 /* Check that the host interface is enabled. */
5983 hicr
= E1000_READ_REG(hw
, HICR
);
5984 if ((hicr
& E1000_HICR_EN
) == 0) {
5985 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5986 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
5988 /* check the previous command is completed */
5989 for (i
= 0; i
< E1000_MNG_DHCP_COMMAND_TIMEOUT
; i
++) {
5990 hicr
= E1000_READ_REG(hw
, HICR
);
5991 if (!(hicr
& E1000_HICR_C
))
5996 if (i
== E1000_MNG_DHCP_COMMAND_TIMEOUT
) {
5997 DEBUGOUT("Previous command timeout failed .\n");
5998 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6000 return E1000_SUCCESS
;
6003 /*****************************************************************************
6004 * This function writes the buffer content at the offset given on the host if.
6005 * It also does alignment considerations to do the writes in most efficient way.
6006 * Also fills up the sum of the buffer in *buffer parameter.
6008 * returns - E1000_SUCCESS for success.
6009 ****************************************************************************/
6011 e1000_mng_host_if_write(struct e1000_hw
* hw
, uint8_t *buffer
,
6012 uint16_t length
, uint16_t offset
, uint8_t *sum
)
6015 uint8_t *bufptr
= buffer
;
6017 uint16_t remaining
, i
, j
, prev_bytes
;
6019 /* sum = only sum of the data and it is not checksum */
6021 if (length
== 0 || offset
+ length
> E1000_HI_MAX_MNG_DATA_LENGTH
) {
6022 return -E1000_ERR_PARAM
;
6025 tmp
= (uint8_t *)&data
;
6026 prev_bytes
= offset
& 0x3;
6031 data
= E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
);
6032 for (j
= prev_bytes
; j
< sizeof(uint32_t); j
++) {
6033 *(tmp
+ j
) = *bufptr
++;
6036 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
, data
);
6037 length
-= j
- prev_bytes
;
6041 remaining
= length
& 0x3;
6042 length
-= remaining
;
6044 /* Calculate length in DWORDs */
6047 /* The device driver writes the relevant command block into the
6049 for (i
= 0; i
< length
; i
++) {
6050 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6051 *(tmp
+ j
) = *bufptr
++;
6055 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6058 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6060 *(tmp
+ j
) = *bufptr
++;
6066 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6069 return E1000_SUCCESS
;
6073 /*****************************************************************************
6074 * This function writes the command header after does the checksum calculation.
6076 * returns - E1000_SUCCESS for success.
6077 ****************************************************************************/
6079 e1000_mng_write_cmd_header(struct e1000_hw
* hw
,
6080 struct e1000_host_mng_command_header
* hdr
)
6086 /* Write the whole command header structure which includes sum of
6089 uint16_t length
= sizeof(struct e1000_host_mng_command_header
);
6091 sum
= hdr
->checksum
;
6094 buffer
= (uint8_t *) hdr
;
6099 hdr
->checksum
= 0 - sum
;
6102 /* The device driver writes the relevant command block into the ram area. */
6103 for (i
= 0; i
< length
; i
++)
6104 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, i
, *((uint32_t *) hdr
+ i
));
6106 return E1000_SUCCESS
;
6110 /*****************************************************************************
6111 * This function indicates to ARC that a new command is pending which completes
6112 * one write operation by the driver.
6114 * returns - E1000_SUCCESS for success.
6115 ****************************************************************************/
6117 e1000_mng_write_commit(
6118 struct e1000_hw
* hw
)
6122 hicr
= E1000_READ_REG(hw
, HICR
);
6123 /* Setting this bit tells the ARC that a new command is pending. */
6124 E1000_WRITE_REG(hw
, HICR
, hicr
| E1000_HICR_C
);
6126 return E1000_SUCCESS
;
6130 /*****************************************************************************
6131 * This function checks the mode of the firmware.
6133 * returns - TRUE when the mode is IAMT or FALSE.
6134 ****************************************************************************/
6136 e1000_check_mng_mode(
6137 struct e1000_hw
*hw
)
6141 fwsm
= E1000_READ_REG(hw
, FWSM
);
6143 if((fwsm
& E1000_FWSM_MODE_MASK
) ==
6144 (E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
6151 /*****************************************************************************
6152 * This function writes the dhcp info .
6153 ****************************************************************************/
6155 e1000_mng_write_dhcp_info(struct e1000_hw
* hw
, uint8_t *buffer
,
6159 struct e1000_host_mng_command_header hdr
;
6161 hdr
.command_id
= E1000_MNG_DHCP_TX_PAYLOAD_CMD
;
6162 hdr
.command_length
= length
;
6167 ret_val
= e1000_mng_enable_host_if(hw
);
6168 if (ret_val
== E1000_SUCCESS
) {
6169 ret_val
= e1000_mng_host_if_write(hw
, buffer
, length
, sizeof(hdr
),
6171 if (ret_val
== E1000_SUCCESS
) {
6172 ret_val
= e1000_mng_write_cmd_header(hw
, &hdr
);
6173 if (ret_val
== E1000_SUCCESS
)
6174 ret_val
= e1000_mng_write_commit(hw
);
6181 /*****************************************************************************
6182 * This function calculates the checksum.
6184 * returns - checksum of buffer contents.
6185 ****************************************************************************/
6187 e1000_calculate_mng_checksum(char *buffer
, uint32_t length
)
6195 for (i
=0; i
< length
; i
++)
6198 return (uint8_t) (0 - sum
);
6201 /*****************************************************************************
6202 * This function checks whether tx pkt filtering needs to be enabled or not.
6204 * returns - TRUE for packet filtering or FALSE.
6205 ****************************************************************************/
6207 e1000_enable_tx_pkt_filtering(struct e1000_hw
*hw
)
6209 /* called in init as well as watchdog timer functions */
6211 int32_t ret_val
, checksum
;
6212 boolean_t tx_filter
= FALSE
;
6213 struct e1000_host_mng_dhcp_cookie
*hdr
= &(hw
->mng_cookie
);
6214 uint8_t *buffer
= (uint8_t *) &(hw
->mng_cookie
);
6216 if (e1000_check_mng_mode(hw
)) {
6217 ret_val
= e1000_mng_enable_host_if(hw
);
6218 if (ret_val
== E1000_SUCCESS
) {
6219 ret_val
= e1000_host_if_read_cookie(hw
, buffer
);
6220 if (ret_val
== E1000_SUCCESS
) {
6221 checksum
= hdr
->checksum
;
6223 if ((hdr
->signature
== E1000_IAMT_SIGNATURE
) &&
6224 checksum
== e1000_calculate_mng_checksum((char *)buffer
,
6225 E1000_MNG_DHCP_COOKIE_LENGTH
)) {
6227 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT
)
6236 hw
->tx_pkt_filtering
= tx_filter
;
6240 /******************************************************************************
6241 * Verifies the hardware needs to allow ARPs to be processed by the host
6243 * hw - Struct containing variables accessed by shared code
6245 * returns: - TRUE/FALSE
6247 *****************************************************************************/
6249 e1000_enable_mng_pass_thru(struct e1000_hw
*hw
)
6252 uint32_t fwsm
, factps
;
6254 if (hw
->asf_firmware_present
) {
6255 manc
= E1000_READ_REG(hw
, MANC
);
6257 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
6258 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
6260 if (e1000_arc_subsystem_valid(hw
) == TRUE
) {
6261 fwsm
= E1000_READ_REG(hw
, FWSM
);
6262 factps
= E1000_READ_REG(hw
, FACTPS
);
6264 if (((fwsm
& E1000_FWSM_MODE_MASK
) ==
6265 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
)) &&
6266 (factps
& E1000_FACTPS_MNGCG
))
6269 if ((manc
& E1000_MANC_SMBUS_EN
) && !(manc
& E1000_MANC_ASF_EN
))
6276 e1000_polarity_reversal_workaround(struct e1000_hw
*hw
)
6279 uint16_t mii_status_reg
;
6282 /* Polarity reversal workaround for forced 10F/10H links. */
6284 /* Disable the transmitter on the PHY */
6286 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6289 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFFF);
6293 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6297 /* This loop will early-out if the NO link condition has been met. */
6298 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6299 /* Read the MII Status Register and wait for Link Status bit
6303 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6307 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6311 if((mii_status_reg
& ~MII_SR_LINK_STATUS
) == 0) break;
6312 msec_delay_irq(100);
6315 /* Recommended delay time after link has been lost */
6316 msec_delay_irq(1000);
6318 /* Now we will re-enable th transmitter on the PHY */
6320 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6324 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFF0);
6328 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFF00);
6332 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x0000);
6336 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6340 /* This loop will early-out if the link condition has been met. */
6341 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6342 /* Read the MII Status Register and wait for Link Status bit
6346 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6350 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6354 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
6355 msec_delay_irq(100);
6357 return E1000_SUCCESS
;
6360 /***************************************************************************
6362 * Disables PCI-Express master access.
6364 * hw: Struct containing variables accessed by shared code
6368 ***************************************************************************/
6370 e1000_set_pci_express_master_disable(struct e1000_hw
*hw
)
6374 DEBUGFUNC("e1000_set_pci_express_master_disable");
6376 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6379 ctrl
= E1000_READ_REG(hw
, CTRL
);
6380 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
6381 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6384 /***************************************************************************
6386 * Enables PCI-Express master access.
6388 * hw: Struct containing variables accessed by shared code
6392 ***************************************************************************/
6394 e1000_enable_pciex_master(struct e1000_hw
*hw
)
6398 DEBUGFUNC("e1000_enable_pciex_master");
6400 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6403 ctrl
= E1000_READ_REG(hw
, CTRL
);
6404 ctrl
&= ~E1000_CTRL_GIO_MASTER_DISABLE
;
6405 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6408 /*******************************************************************************
6410 * Disables PCI-Express master access and verifies there are no pending requests
6412 * hw: Struct containing variables accessed by shared code
6414 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6415 * caused the master requests to be disabled.
6416 * E1000_SUCCESS master requests disabled.
6418 ******************************************************************************/
6420 e1000_disable_pciex_master(struct e1000_hw
*hw
)
6422 int32_t timeout
= MASTER_DISABLE_TIMEOUT
; /* 80ms */
6424 DEBUGFUNC("e1000_disable_pciex_master");
6426 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6427 return E1000_SUCCESS
;
6429 e1000_set_pci_express_master_disable(hw
);
6432 if(!(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_GIO_MASTER_ENABLE
))
6440 DEBUGOUT("Master requests are pending.\n");
6441 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
6444 return E1000_SUCCESS
;
6447 /*******************************************************************************
6449 * Check for EEPROM Auto Read bit done.
6451 * hw: Struct containing variables accessed by shared code
6453 * returns: - E1000_ERR_RESET if fail to reset MAC
6454 * E1000_SUCCESS at any other case.
6456 ******************************************************************************/
6458 e1000_get_auto_rd_done(struct e1000_hw
*hw
)
6460 int32_t timeout
= AUTO_READ_DONE_TIMEOUT
;
6462 DEBUGFUNC("e1000_get_auto_rd_done");
6464 switch (hw
->mac_type
) {
6470 if (E1000_READ_REG(hw
, EECD
) & E1000_EECD_AUTO_RD
) break;
6476 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6477 return -E1000_ERR_RESET
;
6482 return E1000_SUCCESS
;
6485 /***************************************************************************
6486 * Checks if the PHY configuration is done
6488 * hw: Struct containing variables accessed by shared code
6490 * returns: - E1000_ERR_RESET if fail to reset MAC
6491 * E1000_SUCCESS at any other case.
6493 ***************************************************************************/
6495 e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
6497 DEBUGFUNC("e1000_get_phy_cfg_done");
6499 /* Simply wait for 10ms */
6502 return E1000_SUCCESS
;
6505 /***************************************************************************
6507 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6508 * adapter or Eeprom access.
6510 * hw: Struct containing variables accessed by shared code
6512 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6513 * E1000_SUCCESS at any other case.
6515 ***************************************************************************/
6517 e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6522 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6524 if(!hw
->eeprom_semaphore_present
)
6525 return E1000_SUCCESS
;
6528 /* Get the FW semaphore. */
6529 timeout
= hw
->eeprom
.word_size
+ 1;
6531 swsm
= E1000_READ_REG(hw
, SWSM
);
6532 swsm
|= E1000_SWSM_SWESMBI
;
6533 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6534 /* if we managed to set the bit we got the semaphore. */
6535 swsm
= E1000_READ_REG(hw
, SWSM
);
6536 if(swsm
& E1000_SWSM_SWESMBI
)
6544 /* Release semaphores */
6545 e1000_put_hw_eeprom_semaphore(hw
);
6546 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6547 return -E1000_ERR_EEPROM
;
6550 return E1000_SUCCESS
;
6553 /***************************************************************************
6554 * This function clears HW semaphore bits.
6556 * hw: Struct containing variables accessed by shared code
6560 ***************************************************************************/
6562 e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6566 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6568 if(!hw
->eeprom_semaphore_present
)
6571 swsm
= E1000_READ_REG(hw
, SWSM
);
6572 /* Release both semaphores. */
6573 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
6574 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6577 /******************************************************************************
6578 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6579 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6580 * the caller to figure out how to deal with it.
6582 * hw - Struct containing variables accessed by shared code
6584 * returns: - E1000_BLK_PHY_RESET
6587 *****************************************************************************/
6589 e1000_check_phy_reset_block(struct e1000_hw
*hw
)
6592 if(hw
->mac_type
> e1000_82547_rev_2
)
6593 manc
= E1000_READ_REG(hw
, MANC
);
6594 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
6595 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
6599 e1000_arc_subsystem_valid(struct e1000_hw
*hw
)
6603 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6604 * may not be provided a DMA clock when no manageability features are
6605 * enabled. We do not want to perform any reads/writes to these registers
6606 * if this is the case. We read FWSM to determine the manageability mode.
6608 switch (hw
->mac_type
) {
6610 fwsm
= E1000_READ_REG(hw
, FWSM
);
6611 if((fwsm
& E1000_FWSM_MODE_MASK
) != 0)