arch/arm/plat-omap/mux.c

   1 /*
   2  * linux/arch/arm/plat-omap/mux.c
   3  *
   4  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
   5  *
   6  * Copyright (C) 2003 - 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23  *
  24  */
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <asm/system.h>
  29 #include <asm/io.h>
  30 #include <linux/spinlock.h>
  31 #include <asm/arch/mux.h>
  32
  33 #ifdef CONFIG_OMAP_MUX
  34
  35 #define OMAP24XX_L4_BASE        0x48000000
  36 #define OMAP24XX_PULL_ENA       (1 << 3)
  37 #define OMAP24XX_PULL_UP        (1 << 4)
  38
  39 static struct pin_config * pin_table;
  40 static unsigned long pin_table_sz;
  41
  42 extern struct pin_config * omap730_pins;
  43 extern struct pin_config * omap1xxx_pins;
  44 extern struct pin_config * omap24xx_pins;
  45
  46 int __init omap_mux_register(struct pin_config * pins, unsigned long size)
  47 {
  48         pin_table = pins;
  49         pin_table_sz = size;
  50
  51         return 0;
  52 }
  53
  54 /*
  55  * Sets the Omap MUX and PULL_DWN registers based on the table
  56  */
  57 int __init_or_module omap_cfg_reg(const unsigned long index)
  58 {
  59         static DEFINE_SPINLOCK(mux_spin_lock);
  60
  61         unsigned long flags;
  62         struct pin_config *cfg;
  63         unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
  64                 pull_orig = 0, pull = 0;
  65         unsigned int mask, warn = 0;
  66
  67         if (!pin_table)
  68                 BUG();
  69
  70         if (index >= pin_table_sz) {
  71                 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
  72                        index, pin_table_sz);
  73                 dump_stack();
  74                 return -ENODEV;
  75         }
  76
  77         cfg = (struct pin_config *)&pin_table[index];
  78         if (cpu_is_omap24xx()) {
  79                 u8 reg = 0;
  80
  81                 reg |= cfg->mask & 0x7;
  82                 if (cfg->pull_val)
  83                         reg |= OMAP24XX_PULL_ENA;
  84                 if(cfg->pu_pd_val)
  85                         reg |= OMAP24XX_PULL_UP;
  86 #ifdef CONFIG_OMAP_MUX_DEBUG
  87                 printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
  88                        cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
  89                        omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
  90 #endif
  91                 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
  92
  93                 return 0;
  94         }
  95
  96         /* Check the mux register in question */
  97         if (cfg->mux_reg) {
  98                 unsigned        tmp1, tmp2;
  99
 100                 spin_lock_irqsave(&mux_spin_lock, flags);
 101                 reg_orig = omap_readl(cfg->mux_reg);
 102
 103                 /* The mux registers always seem to be 3 bits long */
 104                 mask = (0x7 << cfg->mask_offset);
 105                 tmp1 = reg_orig & mask;
 106                 reg = reg_orig & ~mask;
 107
 108                 tmp2 = (cfg->mask << cfg->mask_offset);
 109                 reg |= tmp2;
 110
 111                 if (tmp1 != tmp2)
 112                         warn = 1;
 113
 114                 omap_writel(reg, cfg->mux_reg);
 115                 spin_unlock_irqrestore(&mux_spin_lock, flags);
 116         }
 117
 118         /* Check for pull up or pull down selection on 1610 */
 119         if (!cpu_is_omap1510()) {
 120                 if (cfg->pu_pd_reg && cfg->pull_val) {
 121                         spin_lock_irqsave(&mux_spin_lock, flags);
 122                         pu_pd_orig = omap_readl(cfg->pu_pd_reg);
 123                         mask = 1 << cfg->pull_bit;
 124
 125                         if (cfg->pu_pd_val) {
 126                                 if (!(pu_pd_orig & mask))
 127                                         warn = 1;
 128                                 /* Use pull up */
 129                                 pu_pd = pu_pd_orig | mask;
 130                         } else {
 131                                 if (pu_pd_orig & mask)
 132                                         warn = 1;
 133                                 /* Use pull down */
 134                                 pu_pd = pu_pd_orig & ~mask;
 135                         }
 136                         omap_writel(pu_pd, cfg->pu_pd_reg);
 137                         spin_unlock_irqrestore(&mux_spin_lock, flags);
 138                 }
 139         }
 140
 141         /* Check for an associated pull down register */
 142         if (cfg->pull_reg) {
 143                 spin_lock_irqsave(&mux_spin_lock, flags);
 144                 pull_orig = omap_readl(cfg->pull_reg);
 145                 mask = 1 << cfg->pull_bit;
 146
 147                 if (cfg->pull_val) {
 148                         if (pull_orig & mask)
 149                                 warn = 1;
 150                         /* Low bit = pull enabled */
 151                         pull = pull_orig & ~mask;
 152                 } else {
 153                         if (!(pull_orig & mask))
 154                                 warn = 1;
 155                         /* High bit = pull disabled */
 156                         pull = pull_orig | mask;
 157                 }
 158
 159                 omap_writel(pull, cfg->pull_reg);
 160                 spin_unlock_irqrestore(&mux_spin_lock, flags);
 161         }
 162
 163         if (warn) {
 164 #ifdef CONFIG_OMAP_MUX_WARNINGS
 165                 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
 166 #endif
 167         }
 168
 169 #ifdef CONFIG_OMAP_MUX_DEBUG
 170         if (cfg->debug || warn) {
 171                 printk("MUX: Setting register %s\n", cfg->name);
 172                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 173                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
 174
 175                 if (!cpu_is_omap1510()) {
 176                         if (cfg->pu_pd_reg && cfg->pull_val) {
 177                                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 178                                        cfg->pu_pd_name, cfg->pu_pd_reg,
 179                                        pu_pd_orig, pu_pd);
 180                         }
 181                 }
 182
 183                 if (cfg->pull_reg)
 184                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 185                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
 186         }
 187 #endif
 188
 189 #ifdef CONFIG_OMAP_MUX_ERRORS
 190         return warn ? -ETXTBSY : 0;
 191 #else
 192         return 0;
 193 #endif
 194 }
 195 EXPORT_SYMBOL(omap_cfg_reg);
 196 #else
 197 #define omap_mux_init() do {} while(0)
 198 #define omap_cfg_reg(x) do {} while(0)
 199 #endif  /* CONFIG_OMAP_MUX */