arch/mips/ddb5xxx/ddb5074/irq.c

   1 /*
   2  *  arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
   3  *
   4  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
   5  *                     Sony Software Development Center Europe (SDCE), Brussels
   6  */
   7 #include <linux/init.h>
   8 #include <linux/irq.h>
   9 #include <linux/signal.h>
  10 #include <linux/sched.h>
  11 #include <linux/types.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/ioport.h>
  14
  15 #include <asm/i8259.h>
  16 #include <asm/io.h>
  17 #include <asm/irq_cpu.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/nile4.h>
  20 #include <asm/ddb5xxx/ddb5xxx.h>
  21 #include <asm/ddb5xxx/ddb5074.h>
  22
  23
  24 extern asmlinkage void ddbIRQ(void);
  25
  26 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
  27
  28 #define M1543_PNP_CONFIG        0x03f0  /* PnP Config Port */
  29 #define M1543_PNP_INDEX         0x03f0  /* PnP Index Port */
  30 #define M1543_PNP_DATA          0x03f1  /* PnP Data Port */
  31
  32 #define M1543_PNP_ALT_CONFIG    0x0370  /* Alternative PnP Config Port */
  33 #define M1543_PNP_ALT_INDEX     0x0370  /* Alternative PnP Index Port */
  34 #define M1543_PNP_ALT_DATA      0x0371  /* Alternative PnP Data Port */
  35
  36 #define M1543_INT1_MASTER_CTRL  0x0020  /* INT_1 (master) Control Register */
  37 #define M1543_INT1_MASTER_MASK  0x0021  /* INT_1 (master) Mask Register */
  38
  39 #define M1543_INT1_SLAVE_CTRL   0x00a0  /* INT_1 (slave) Control Register */
  40 #define M1543_INT1_SLAVE_MASK   0x00a1  /* INT_1 (slave) Mask Register */
  41
  42 #define M1543_INT1_MASTER_ELCR  0x04d0  /* INT_1 (master) Edge/Level Control */
  43 #define M1543_INT1_SLAVE_ELCR   0x04d1  /* INT_1 (slave) Edge/Level Control */
  44
  45
  46 static void m1543_irq_setup(void)
  47 {
  48         /*
  49          *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
  50          *  the possible IO sources in the M1543 are in use by us.  We will
  51          *  use the following mapping:
  52          *
  53          *      IRQ1  - keyboard (default set by M1543)
  54          *      IRQ3  - reserved for UART B (default set by M1543) (note that
  55          *              the schematics for the DDB Vrc-5074 board seem to
  56          *              indicate that IRQ3 is connected to the DS1386
  57          *              watchdog timer interrupt output so we might have
  58          *              a conflict)
  59          *      IRQ4  - reserved for UART A (default set by M1543)
  60          *      IRQ5  - parallel (default set by M1543)
  61          *      IRQ8  - DS1386 time of day (RTC) interrupt
  62          *      IRQ12 - mouse
  63          */
  64
  65         /*
  66          *  Assing mouse interrupt to IRQ12
  67          */
  68
  69         /* Enter configuration mode */
  70         outb(0x51, M1543_PNP_CONFIG);
  71         outb(0x23, M1543_PNP_CONFIG);
  72
  73         /* Select logical device 7 (Keyboard) */
  74         outb(0x07, M1543_PNP_INDEX);
  75         outb(0x07, M1543_PNP_DATA);
  76
  77         /* Select IRQ12 */
  78         outb(0x72, M1543_PNP_INDEX);
  79         outb(0x0c, M1543_PNP_DATA);
  80
  81         outb(0x30, M1543_PNP_INDEX);
  82         printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
  83
  84         outb(0x70, M1543_PNP_INDEX);
  85         printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
  86
  87         /* Leave configration mode */
  88         outb(0xbb, M1543_PNP_CONFIG);
  89
  90
  91 }
  92
  93 void ddb_local0_irqdispatch(struct pt_regs *regs)
  94 {
  95         u32 mask;
  96         int nile4_irq;
  97
  98         mask = nile4_get_irq_stat(0);
  99
 100         /* Handle the timer interrupt first */
 101 #if 0
 102         if (mask & (1 << NILE4_INT_GPT)) {
 103                 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
 104                 mask &= ~(1 << NILE4_INT_GPT);
 105         }
 106 #endif
 107         for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
 108                 if (mask & 1) {
 109                         if (nile4_irq == NILE4_INT_INTE) {
 110                                 int i8259_irq;
 111
 112                                 nile4_clear_irq(NILE4_INT_INTE);
 113                                 i8259_irq = nile4_i8259_iack();
 114                                 do_IRQ(i8259_irq, regs);
 115                         } else
 116                                 do_IRQ(nile4_to_irq(nile4_irq), regs);
 117
 118                 }
 119 }
 120
 121 void ddb_local1_irqdispatch(void)
 122 {
 123         printk("ddb_local1_irqdispatch called\n");
 124 }
 125
 126 void ddb_buserror_irq(void)
 127 {
 128         printk("ddb_buserror_irq called\n");
 129 }
 130
 131 void ddb_8254timer_irq(void)
 132 {
 133         printk("ddb_8254timer_irq called\n");
 134 }
 135
 136 void __init arch_init_irq(void)
 137 {
 138         /* setup cascade interrupts */
 139         setup_irq(NILE4_IRQ_BASE  + NILE4_INT_INTE, &irq_cascade);
 140         setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
 141
 142         set_except_vector(0, ddbIRQ);
 143
 144         nile4_irq_setup(NILE4_IRQ_BASE);
 145         m1543_irq_setup();
 146         init_i8259_irqs();
 147
 148
 149         printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
 150
 151         mips_cpu_irq_init(CPU_IRQ_BASE);
 152
 153         printk("enabling 8259 cascade\n");
 154
 155         ddb5074_led_hex(0);
 156
 157         /* Enable the interrupt cascade */
 158         nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
 159 }