2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * These are the low level assembler for performing cache and TLB
23 * functions on the arm926.
25 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
27 #include <linux/linkage.h>
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/pgtable.h>
32 #include <asm/procinfo.h>
34 #include <asm/ptrace.h>
35 #include "proc-macros.S"
38 * This is the maximum size of an area which will be invalidated
39 * using the single invalidate entry instructions. Anything larger
40 * than this, and we go for the whole cache.
42 * This value should be chosen such that we choose the cheapest
45 #define CACHE_DLIMIT 16384
48 * the cache line size of the I and D cache
50 #define CACHE_DLINESIZE 32
54 * cpu_arm926_proc_init()
56 ENTRY(cpu_arm926_proc_init)
60 * cpu_arm926_proc_fin()
62 ENTRY(cpu_arm926_proc_fin)
64 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
66 bl arm926_flush_kern_cache_all
67 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
68 bic r0, r0, #0x1000 @ ...i............
69 bic r0, r0, #0x000e @ ............wca.
70 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 * cpu_arm926_reset(loc)
76 * Perform a soft reset of the system. Put the CPU into the
77 * same state as it would be if it had been reset, and branch
78 * to what would be the reset vector.
80 * loc: location to jump to for soft reset
83 ENTRY(cpu_arm926_reset)
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
87 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
88 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
89 bic ip, ip, #0x000f @ ............wcam
90 bic ip, ip, #0x1100 @ ...i...s........
91 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 * cpu_arm926_do_idle()
97 * Called with IRQs disabled
100 ENTRY(cpu_arm926_do_idle)
102 mrc p15, 0, r1, c1, c0, 0 @ Read control register
103 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
105 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
111 * flush_user_cache_all()
113 * Clean and invalidate all cache entries in a particular
116 ENTRY(arm926_flush_user_cache_all)
120 * flush_kern_cache_all()
122 * Clean and invalidate the entire cache.
124 ENTRY(arm926_flush_kern_cache_all)
128 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
129 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
131 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
135 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
136 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
140 * flush_user_cache_range(start, end, flags)
142 * Clean and invalidate a range of cache entries in the
143 * specified address range.
145 * - start - start address (inclusive)
146 * - end - end address (exclusive)
147 * - flags - vm_flags describing address space
149 ENTRY(arm926_flush_user_cache_range)
151 sub r3, r1, r0 @ calculate total size
152 cmp r3, #CACHE_DLIMIT
153 bgt __flush_whole_cache
155 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
156 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
157 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
158 add r0, r0, #CACHE_DLINESIZE
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
163 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
165 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
173 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
177 * coherent_kern_range(start, end)
179 * Ensure coherency between the Icache and the Dcache in the
180 * region described by start, end. If you have non-snooping
181 * Harvard caches, you need to implement this function.
183 * - start - virtual start address
184 * - end - virtual end address
186 ENTRY(arm926_coherent_kern_range)
190 * coherent_user_range(start, end)
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start, end. If you have non-snooping
194 * Harvard caches, you need to implement this function.
196 * - start - virtual start address
197 * - end - virtual end address
199 ENTRY(arm926_coherent_user_range)
200 bic r0, r0, #CACHE_DLINESIZE - 1
201 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 add r0, r0, #CACHE_DLINESIZE
206 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 * flush_kern_dcache_page(void *page)
212 * Ensure no D cache aliasing occurs, either with itself or
215 * - addr - page aligned address
217 ENTRY(arm926_flush_kern_dcache_page)
219 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
220 add r0, r0, #CACHE_DLINESIZE
224 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
225 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 * dma_inv_range(start, end)
231 * Invalidate (discard) the specified virtual address range.
232 * May not write back any entries. If 'start' or 'end'
233 * are not cache line aligned, those lines must be written
236 * - start - virtual start address
237 * - end - virtual end address
241 ENTRY(arm926_dma_inv_range)
242 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
243 tst r0, #CACHE_DLINESIZE - 1
244 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
245 tst r1, #CACHE_DLINESIZE - 1
246 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
248 bic r0, r0, #CACHE_DLINESIZE - 1
249 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
250 add r0, r0, #CACHE_DLINESIZE
253 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 * dma_clean_range(start, end)
259 * Clean the specified virtual address range.
261 * - start - virtual start address
262 * - end - virtual end address
266 ENTRY(arm926_dma_clean_range)
267 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
268 bic r0, r0, #CACHE_DLINESIZE - 1
269 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
270 add r0, r0, #CACHE_DLINESIZE
274 mcr p15, 0, r0, c7, c10, 4 @ drain WB
278 * dma_flush_range(start, end)
280 * Clean and invalidate the specified virtual address range.
282 * - start - virtual start address
283 * - end - virtual end address
285 ENTRY(arm926_dma_flush_range)
286 bic r0, r0, #CACHE_DLINESIZE - 1
288 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
289 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
291 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 add r0, r0, #CACHE_DLINESIZE
296 mcr p15, 0, r0, c7, c10, 4 @ drain WB
299 ENTRY(arm926_cache_fns)
300 .long arm926_flush_kern_cache_all
301 .long arm926_flush_user_cache_all
302 .long arm926_flush_user_cache_range
303 .long arm926_coherent_kern_range
304 .long arm926_coherent_user_range
305 .long arm926_flush_kern_dcache_page
306 .long arm926_dma_inv_range
307 .long arm926_dma_clean_range
308 .long arm926_dma_flush_range
310 ENTRY(cpu_arm926_dcache_clean_area)
311 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
312 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
313 add r0, r0, #CACHE_DLINESIZE
314 subs r1, r1, #CACHE_DLINESIZE
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
320 /* =============================== PageTable ============================== */
323 * cpu_arm926_switch_mm(pgd)
325 * Set the translation base pointer to be as described by pgd.
327 * pgd: new page tables
330 ENTRY(cpu_arm926_switch_mm)
332 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
333 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
335 @ && 'Clean & Invalidate whole DCache'
336 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
339 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
340 mcr p15, 0, ip, c7, c10, 4 @ drain WB
341 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
342 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
346 * cpu_arm926_set_pte(ptep, pte)
348 * Set a PTE and flush it out
351 ENTRY(cpu_arm926_set_pte)
352 str r1, [r0], #-2048 @ linux version
354 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
356 bic r2, r1, #PTE_SMALL_AP_MASK
357 bic r2, r2, #PTE_TYPE_MASK
358 orr r2, r2, #PTE_TYPE_SMALL
360 tst r1, #L_PTE_USER @ User?
361 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
363 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
364 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
366 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
369 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
370 eor r3, r2, #0x0a @ C & small page?
374 str r2, [r0] @ hardware version
376 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 mcr p15, 0, r0, c7, c10, 4 @ drain WB
384 .type __arm926_setup, #function
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
388 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
389 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
392 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
393 mov r0, #4 @ disable write-back on caches explicitly
394 mcr p15, 7, r0, c15, c0, 0
397 mrc p15, 0, r0, c1, c0 @ get control register v4
398 ldr r5, arm926_cr1_clear
400 ldr r5, arm926_cr1_set
402 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
403 orr r0, r0, #0x4000 @ .1.. .... .... ....
406 .size __arm926_setup, . - __arm926_setup
410 * .RVI ZFRS BLDP WCAM
411 * .011 0001 ..11 0101
414 .type arm926_cr1_clear, #object
415 .type arm926_cr1_set, #object
424 * Purpose : Function pointers used to access above functions - all calls
427 .type arm926_processor_functions, #object
428 arm926_processor_functions:
429 .word v5tj_early_abort
430 .word cpu_arm926_proc_init
431 .word cpu_arm926_proc_fin
432 .word cpu_arm926_reset
433 .word cpu_arm926_do_idle
434 .word cpu_arm926_dcache_clean_area
435 .word cpu_arm926_switch_mm
436 .word cpu_arm926_set_pte
437 .size arm926_processor_functions, . - arm926_processor_functions
441 .type cpu_arch_name, #object
444 .size cpu_arch_name, . - cpu_arch_name
446 .type cpu_elf_name, #object
449 .size cpu_elf_name, . - cpu_elf_name
451 .type cpu_arm926_name, #object
454 #ifndef CONFIG_CPU_ICACHE_DISABLE
457 #ifndef CONFIG_CPU_DCACHE_DISABLE
459 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
464 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
469 .size cpu_arm926_name, . - cpu_arm926_name
473 .section ".proc.info.init", #alloc, #execinstr
475 .type __arm926_proc_info,#object
477 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
479 .long PMD_TYPE_SECT | \
480 PMD_SECT_BUFFERABLE | \
481 PMD_SECT_CACHEABLE | \
483 PMD_SECT_AP_WRITE | \
488 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
489 .long cpu_arm926_name
490 .long arm926_processor_functions
493 .long arm926_cache_fns
494 .size __arm926_proc_info, . - __arm926_proc_info