2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/uaccess.h>
20 #include <asm/pgalloc.h>
21 #include <asm/proto.h>
25 * The current flushing context - we pass it instead of 5 arguments:
34 unsigned force_split
: 1;
38 #define CPA_FLUSHTLB 1
42 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
44 void update_page_count(int level
, unsigned long pages
)
48 /* Protect against CPA */
49 spin_lock_irqsave(&pgd_lock
, flags
);
50 direct_pages_count
[level
] += pages
;
51 spin_unlock_irqrestore(&pgd_lock
, flags
);
54 static void split_page_count(int level
)
56 direct_pages_count
[level
]--;
57 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
60 int arch_report_meminfo(char *page
)
62 int n
= sprintf(page
, "DirectMap4k: %8lu kB\n",
63 direct_pages_count
[PG_LEVEL_4K
] << 2);
64 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
65 n
+= sprintf(page
+ n
, "DirectMap2M: %8lu kB\n",
66 direct_pages_count
[PG_LEVEL_2M
] << 11);
68 n
+= sprintf(page
+ n
, "DirectMap4M: %8lu kB\n",
69 direct_pages_count
[PG_LEVEL_2M
] << 12);
73 n
+= sprintf(page
+ n
, "DirectMap1G: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_1G
] << 20);
79 static inline void split_page_count(int level
) { }
84 static inline unsigned long highmap_start_pfn(void)
86 return __pa(_text
) >> PAGE_SHIFT
;
89 static inline unsigned long highmap_end_pfn(void)
91 return __pa(round_up((unsigned long)_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
96 #ifdef CONFIG_DEBUG_PAGEALLOC
97 # define debug_pagealloc 1
99 # define debug_pagealloc 0
103 within(unsigned long addr
, unsigned long start
, unsigned long end
)
105 return addr
>= start
&& addr
< end
;
113 * clflush_cache_range - flush a cache range with clflush
114 * @addr: virtual start address
115 * @size: number of bytes to flush
117 * clflush is an unordered instruction which needs fencing with mfence
118 * to avoid ordering issues.
120 void clflush_cache_range(void *vaddr
, unsigned int size
)
122 void *vend
= vaddr
+ size
- 1;
126 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
129 * Flush any possible final partial cacheline:
136 static void __cpa_flush_all(void *arg
)
138 unsigned long cache
= (unsigned long)arg
;
141 * Flush all to work around Errata in early athlons regarding
142 * large page flushing.
146 if (cache
&& boot_cpu_data
.x86_model
>= 4)
150 static void cpa_flush_all(unsigned long cache
)
152 BUG_ON(irqs_disabled());
154 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
157 static void __cpa_flush_range(void *arg
)
160 * We could optimize that further and do individual per page
161 * tlb invalidates for a low number of pages. Caveat: we must
162 * flush the high aliases on 64bit as well.
167 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
169 unsigned int i
, level
;
172 BUG_ON(irqs_disabled());
173 WARN_ON(PAGE_ALIGN(start
) != start
);
175 on_each_cpu(__cpa_flush_range
, NULL
, 1);
181 * We only need to flush on one CPU,
182 * clflush is a MESI-coherent instruction that
183 * will cause all other CPUs to flush the same
186 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
187 pte_t
*pte
= lookup_address(addr
, &level
);
190 * Only flush present addresses:
192 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
193 clflush_cache_range((void *) addr
, PAGE_SIZE
);
197 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
)
199 unsigned int i
, level
;
202 BUG_ON(irqs_disabled());
204 on_each_cpu(__cpa_flush_range
, NULL
, 1);
210 if (numpages
>= 1024) {
211 if (boot_cpu_data
.x86_model
>= 4)
216 * We only need to flush on one CPU,
217 * clflush is a MESI-coherent instruction that
218 * will cause all other CPUs to flush the same
221 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
++) {
222 pte_t
*pte
= lookup_address(*addr
, &level
);
225 * Only flush present addresses:
227 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
228 clflush_cache_range((void *) *addr
, PAGE_SIZE
);
233 * Certain areas of memory on x86 require very specific protection flags,
234 * for example the BIOS area or kernel text. Callers don't always get this
235 * right (again, ioremap() on BIOS memory is not uncommon) so this function
236 * checks and fixes these known static required protection bits.
238 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
241 pgprot_t forbidden
= __pgprot(0);
244 * The BIOS area between 640k and 1Mb needs to be executable for
245 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
247 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
248 pgprot_val(forbidden
) |= _PAGE_NX
;
251 * The kernel text needs to be executable for obvious reasons
252 * Does not cover __inittext since that is gone later on. On
253 * 64bit we do not enforce !NX on the low mapping
255 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
256 pgprot_val(forbidden
) |= _PAGE_NX
;
259 * The .rodata section needs to be read-only. Using the pfn
260 * catches all aliases.
262 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
263 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
264 pgprot_val(forbidden
) |= _PAGE_RW
;
266 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
272 * Lookup the page table entry for a virtual address. Return a pointer
273 * to the entry and the level of the mapping.
275 * Note: We return pud and pmd either when the entry is marked large
276 * or when the present bit is not set. Otherwise we would return a
277 * pointer to a nonexisting mapping.
279 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
281 pgd_t
*pgd
= pgd_offset_k(address
);
285 *level
= PG_LEVEL_NONE
;
290 pud
= pud_offset(pgd
, address
);
294 *level
= PG_LEVEL_1G
;
295 if (pud_large(*pud
) || !pud_present(*pud
))
298 pmd
= pmd_offset(pud
, address
);
302 *level
= PG_LEVEL_2M
;
303 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
306 *level
= PG_LEVEL_4K
;
308 return pte_offset_kernel(pmd
, address
);
310 EXPORT_SYMBOL_GPL(lookup_address
);
313 * Set the new pmd in all the pgds we know about:
315 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
318 set_pte_atomic(kpte
, pte
);
320 if (!SHARED_KERNEL_PMD
) {
323 list_for_each_entry(page
, &pgd_list
, lru
) {
328 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
329 pud
= pud_offset(pgd
, address
);
330 pmd
= pmd_offset(pud
, address
);
331 set_pte_atomic((pte_t
*)pmd
, pte
);
338 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
339 struct cpa_data
*cpa
)
341 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
342 pte_t new_pte
, old_pte
, *tmp
;
343 pgprot_t old_prot
, new_prot
;
347 if (cpa
->force_split
)
350 spin_lock_irqsave(&pgd_lock
, flags
);
352 * Check for races, another CPU might have split this page
355 tmp
= lookup_address(address
, &level
);
361 psize
= PMD_PAGE_SIZE
;
362 pmask
= PMD_PAGE_MASK
;
366 psize
= PUD_PAGE_SIZE
;
367 pmask
= PUD_PAGE_MASK
;
376 * Calculate the number of pages, which fit into this large
377 * page starting at address:
379 nextpage_addr
= (address
+ psize
) & pmask
;
380 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
381 if (numpages
< cpa
->numpages
)
382 cpa
->numpages
= numpages
;
385 * We are safe now. Check whether the new pgprot is the same:
388 old_prot
= new_prot
= pte_pgprot(old_pte
);
390 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
391 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
394 * old_pte points to the large page base address. So we need
395 * to add the offset of the virtual address:
397 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
400 new_prot
= static_protections(new_prot
, address
, pfn
);
403 * We need to check the full range, whether
404 * static_protection() requires a different pgprot for one of
405 * the pages in the range we try to preserve:
407 addr
= address
+ PAGE_SIZE
;
409 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
410 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
412 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
417 * If there are no changes, return. maxpages has been updated
420 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
426 * We need to change the attributes. Check, whether we can
427 * change the large page in one go. We request a split, when
428 * the address is not aligned and the number of pages is
429 * smaller than the number of pages in the large page. Note
430 * that we limited the number of possible pages already to
431 * the number of pages in the large page.
433 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
435 * The address is aligned and the number of pages
436 * covers the full page.
438 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
439 __set_pmd_pte(kpte
, address
, new_pte
);
440 cpa
->flags
|= CPA_FLUSHTLB
;
445 spin_unlock_irqrestore(&pgd_lock
, flags
);
450 static int split_large_page(pte_t
*kpte
, unsigned long address
)
452 unsigned long flags
, pfn
, pfninc
= 1;
453 unsigned int i
, level
;
456 struct page
*base
= alloc_pages(GFP_KERNEL
, 0);
460 spin_lock_irqsave(&pgd_lock
, flags
);
462 * Check for races, another CPU might have split this page
465 tmp
= lookup_address(address
, &level
);
469 pbase
= (pte_t
*)page_address(base
);
470 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
471 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
474 if (level
== PG_LEVEL_1G
) {
475 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
476 pgprot_val(ref_prot
) |= _PAGE_PSE
;
481 * Get the target pfn from the original entry:
483 pfn
= pte_pfn(*kpte
);
484 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
485 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
487 if (address
>= (unsigned long)__va(0) &&
488 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
489 split_page_count(level
);
492 if (address
>= (unsigned long)__va(1UL<<32) &&
493 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
494 split_page_count(level
);
498 * Install the new, split up pagetable. Important details here:
500 * On Intel the NX bit of all levels must be cleared to make a
501 * page executable. See section 4.13.2 of Intel 64 and IA-32
502 * Architectures Software Developer's Manual).
504 * Mark the entry present. The current mapping might be
505 * set to not present, which we preserved above.
507 ref_prot
= pte_pgprot(pte_mkexec(pte_clrhuge(*kpte
)));
508 pgprot_val(ref_prot
) |= _PAGE_PRESENT
;
509 __set_pmd_pte(kpte
, address
, mk_pte(base
, ref_prot
));
514 * If we dropped out via the lookup_address check under
515 * pgd_lock then stick the page back into the pool:
519 spin_unlock_irqrestore(&pgd_lock
, flags
);
524 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
526 unsigned long address
;
529 pte_t
*kpte
, old_pte
;
531 if (cpa
->flags
& CPA_ARRAY
)
532 address
= cpa
->vaddr
[cpa
->curpage
];
534 address
= *cpa
->vaddr
;
537 kpte
= lookup_address(address
, &level
);
542 if (!pte_val(old_pte
)) {
545 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
546 "vaddr = %lx cpa->vaddr = %lx\n", address
,
551 if (level
== PG_LEVEL_4K
) {
553 pgprot_t new_prot
= pte_pgprot(old_pte
);
554 unsigned long pfn
= pte_pfn(old_pte
);
556 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
557 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
559 new_prot
= static_protections(new_prot
, address
, pfn
);
562 * We need to keep the pfn from the existing PTE,
563 * after all we're only going to change it's attributes
564 * not the memory it points to
566 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
569 * Do we really change anything ?
571 if (pte_val(old_pte
) != pte_val(new_pte
)) {
572 set_pte_atomic(kpte
, new_pte
);
573 cpa
->flags
|= CPA_FLUSHTLB
;
580 * Check, whether we can keep the large page intact
581 * and just change the pte:
583 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
585 * When the range fits into the existing large page,
586 * return. cp->numpages and cpa->tlbflush have been updated in
593 * We have to split the large page:
595 err
= split_large_page(kpte
, address
);
597 cpa
->flags
|= CPA_FLUSHTLB
;
604 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
606 static int cpa_process_alias(struct cpa_data
*cpa
)
608 struct cpa_data alias_cpa
;
610 unsigned long temp_cpa_vaddr
, vaddr
;
612 if (cpa
->pfn
>= max_pfn_mapped
)
616 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
620 * No need to redo, when the primary call touched the direct
623 if (cpa
->flags
& CPA_ARRAY
)
624 vaddr
= cpa
->vaddr
[cpa
->curpage
];
628 if (!(within(vaddr
, PAGE_OFFSET
,
629 PAGE_OFFSET
+ (max_low_pfn_mapped
<< PAGE_SHIFT
))
631 || within(vaddr
, PAGE_OFFSET
+ (1UL<<32),
632 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))
637 temp_cpa_vaddr
= (unsigned long) __va(cpa
->pfn
<< PAGE_SHIFT
);
638 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
639 alias_cpa
.flags
&= ~CPA_ARRAY
;
642 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
649 * No need to redo, when the primary call touched the high
652 if (within(vaddr
, (unsigned long) _text
, (unsigned long) _end
))
656 * If the physical address is inside the kernel map, we need
657 * to touch the high mapped kernel as well:
659 if (!within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn()))
663 temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) + __START_KERNEL_map
- phys_base
;
664 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
665 alias_cpa
.flags
&= ~CPA_ARRAY
;
668 * The high mapping range is imprecise, so ignore the return value.
670 __change_page_attr_set_clr(&alias_cpa
, 0);
675 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
677 int ret
, numpages
= cpa
->numpages
;
681 * Store the remaining nr of pages for the large page
682 * preservation check.
684 cpa
->numpages
= numpages
;
685 /* for array changes, we can't use large page */
686 if (cpa
->flags
& CPA_ARRAY
)
689 ret
= __change_page_attr(cpa
, checkalias
);
694 ret
= cpa_process_alias(cpa
);
700 * Adjust the number of pages with the result of the
701 * CPA operation. Either a large page has been
702 * preserved or a single page update happened.
704 BUG_ON(cpa
->numpages
> numpages
);
705 numpages
-= cpa
->numpages
;
706 if (cpa
->flags
& CPA_ARRAY
)
709 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
715 static inline int cache_attr(pgprot_t attr
)
717 return pgprot_val(attr
) &
718 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
721 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
722 pgprot_t mask_set
, pgprot_t mask_clr
,
723 int force_split
, int array
)
726 int ret
, cache
, checkalias
;
729 * Check, if we are requested to change a not supported
732 mask_set
= canon_pgprot(mask_set
);
733 mask_clr
= canon_pgprot(mask_clr
);
734 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
737 /* Ensure we are PAGE_SIZE aligned */
739 if (*addr
& ~PAGE_MASK
) {
742 * People should not be passing in unaligned addresses:
748 for (i
= 0; i
< numpages
; i
++) {
749 if (addr
[i
] & ~PAGE_MASK
) {
750 addr
[i
] &= PAGE_MASK
;
756 /* Must avoid aliasing mappings in the highmem code */
760 cpa
.numpages
= numpages
;
761 cpa
.mask_set
= mask_set
;
762 cpa
.mask_clr
= mask_clr
;
765 cpa
.force_split
= force_split
;
768 cpa
.flags
|= CPA_ARRAY
;
770 /* No alias checking for _NX bit modifications */
771 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
773 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
776 * Check whether we really changed something:
778 if (!(cpa
.flags
& CPA_FLUSHTLB
))
782 * No need to flush, when we did not set any of the caching
785 cache
= cache_attr(mask_set
);
788 * On success we use clflush, when the CPU supports it to
789 * avoid the wbindv. If the CPU does not support it and in the
790 * error case we fall back to cpa_flush_all (which uses
793 if (!ret
&& cpu_has_clflush
) {
794 if (cpa
.flags
& CPA_ARRAY
)
795 cpa_flush_array(addr
, numpages
, cache
);
797 cpa_flush_range(*addr
, numpages
, cache
);
799 cpa_flush_all(cache
);
805 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
806 pgprot_t mask
, int array
)
808 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
812 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
813 pgprot_t mask
, int array
)
815 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
819 int _set_memory_uc(unsigned long addr
, int numpages
)
822 * for now UC MINUS. see comments in ioremap_nocache()
824 return change_page_attr_set(&addr
, numpages
,
825 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
828 int set_memory_uc(unsigned long addr
, int numpages
)
831 * for now UC MINUS. see comments in ioremap_nocache()
833 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
834 _PAGE_CACHE_UC_MINUS
, NULL
))
837 return _set_memory_uc(addr
, numpages
);
839 EXPORT_SYMBOL(set_memory_uc
);
841 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
847 * for now UC MINUS. see comments in ioremap_nocache()
849 for (i
= 0; i
< addrinarray
; i
++) {
850 start
= __pa(addr
[i
]);
851 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
852 if (end
!= __pa(addr
[i
+ 1]))
856 if (reserve_memtype(start
, end
, _PAGE_CACHE_UC_MINUS
, NULL
))
860 return change_page_attr_set(addr
, addrinarray
,
861 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
863 for (i
= 0; i
< addrinarray
; i
++) {
864 unsigned long tmp
= __pa(addr
[i
]);
868 for (end
= tmp
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
869 if (end
!= __pa(addr
[i
+ 1]))
873 free_memtype(tmp
, end
);
877 EXPORT_SYMBOL(set_memory_array_uc
);
879 int _set_memory_wc(unsigned long addr
, int numpages
)
881 return change_page_attr_set(&addr
, numpages
,
882 __pgprot(_PAGE_CACHE_WC
), 0);
885 int set_memory_wc(unsigned long addr
, int numpages
)
888 return set_memory_uc(addr
, numpages
);
890 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
891 _PAGE_CACHE_WC
, NULL
))
894 return _set_memory_wc(addr
, numpages
);
896 EXPORT_SYMBOL(set_memory_wc
);
898 int _set_memory_wb(unsigned long addr
, int numpages
)
900 return change_page_attr_clear(&addr
, numpages
,
901 __pgprot(_PAGE_CACHE_MASK
), 0);
904 int set_memory_wb(unsigned long addr
, int numpages
)
906 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
908 return _set_memory_wb(addr
, numpages
);
910 EXPORT_SYMBOL(set_memory_wb
);
912 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
916 for (i
= 0; i
< addrinarray
; i
++) {
917 unsigned long start
= __pa(addr
[i
]);
920 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
921 if (end
!= __pa(addr
[i
+ 1]))
925 free_memtype(start
, end
);
927 return change_page_attr_clear(addr
, addrinarray
,
928 __pgprot(_PAGE_CACHE_MASK
), 1);
930 EXPORT_SYMBOL(set_memory_array_wb
);
932 int set_memory_x(unsigned long addr
, int numpages
)
934 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
936 EXPORT_SYMBOL(set_memory_x
);
938 int set_memory_nx(unsigned long addr
, int numpages
)
940 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
942 EXPORT_SYMBOL(set_memory_nx
);
944 int set_memory_ro(unsigned long addr
, int numpages
)
946 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
949 int set_memory_rw(unsigned long addr
, int numpages
)
951 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
954 int set_memory_np(unsigned long addr
, int numpages
)
956 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
959 int set_memory_4k(unsigned long addr
, int numpages
)
961 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
965 int set_pages_uc(struct page
*page
, int numpages
)
967 unsigned long addr
= (unsigned long)page_address(page
);
969 return set_memory_uc(addr
, numpages
);
971 EXPORT_SYMBOL(set_pages_uc
);
973 int set_pages_wb(struct page
*page
, int numpages
)
975 unsigned long addr
= (unsigned long)page_address(page
);
977 return set_memory_wb(addr
, numpages
);
979 EXPORT_SYMBOL(set_pages_wb
);
981 int set_pages_x(struct page
*page
, int numpages
)
983 unsigned long addr
= (unsigned long)page_address(page
);
985 return set_memory_x(addr
, numpages
);
987 EXPORT_SYMBOL(set_pages_x
);
989 int set_pages_nx(struct page
*page
, int numpages
)
991 unsigned long addr
= (unsigned long)page_address(page
);
993 return set_memory_nx(addr
, numpages
);
995 EXPORT_SYMBOL(set_pages_nx
);
997 int set_pages_ro(struct page
*page
, int numpages
)
999 unsigned long addr
= (unsigned long)page_address(page
);
1001 return set_memory_ro(addr
, numpages
);
1004 int set_pages_rw(struct page
*page
, int numpages
)
1006 unsigned long addr
= (unsigned long)page_address(page
);
1008 return set_memory_rw(addr
, numpages
);
1011 #ifdef CONFIG_DEBUG_PAGEALLOC
1013 static int __set_pages_p(struct page
*page
, int numpages
)
1015 unsigned long tempaddr
= (unsigned long) page_address(page
);
1016 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1017 .numpages
= numpages
,
1018 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1019 .mask_clr
= __pgprot(0),
1023 * No alias checking needed for setting present flag. otherwise,
1024 * we may need to break large pages for 64-bit kernel text
1025 * mappings (this adds to complexity if we want to do this from
1026 * atomic context especially). Let's keep it simple!
1028 return __change_page_attr_set_clr(&cpa
, 0);
1031 static int __set_pages_np(struct page
*page
, int numpages
)
1033 unsigned long tempaddr
= (unsigned long) page_address(page
);
1034 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1035 .numpages
= numpages
,
1036 .mask_set
= __pgprot(0),
1037 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1041 * No alias checking needed for setting not present flag. otherwise,
1042 * we may need to break large pages for 64-bit kernel text
1043 * mappings (this adds to complexity if we want to do this from
1044 * atomic context especially). Let's keep it simple!
1046 return __change_page_attr_set_clr(&cpa
, 0);
1049 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1051 if (PageHighMem(page
))
1054 debug_check_no_locks_freed(page_address(page
),
1055 numpages
* PAGE_SIZE
);
1059 * If page allocator is not up yet then do not call c_p_a():
1061 if (!debug_pagealloc_enabled
)
1065 * The return value is ignored as the calls cannot fail.
1066 * Large pages for identity mappings are not used at boot time
1067 * and hence no memory allocations during large page split.
1070 __set_pages_p(page
, numpages
);
1072 __set_pages_np(page
, numpages
);
1075 * We should perform an IPI and flush all tlbs,
1076 * but that can deadlock->flush only current cpu:
1081 #ifdef CONFIG_HIBERNATION
1083 bool kernel_page_present(struct page
*page
)
1088 if (PageHighMem(page
))
1091 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1092 return (pte_val(*pte
) & _PAGE_PRESENT
);
1095 #endif /* CONFIG_HIBERNATION */
1097 #endif /* CONFIG_DEBUG_PAGEALLOC */
1100 * The testcases use internal knowledge of the implementation that shouldn't
1101 * be exposed to the rest of the kernel. Include these directly here.
1103 #ifdef CONFIG_CPA_DEBUG
1104 #include "pageattr-test.c"