1 #ifndef __PARISC_SYSTEM_H
2 #define __PARISC_SYSTEM_H
4 #include <linux/config.h>
7 /* The program status word as bitfields. */
39 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
41 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
46 extern struct task_struct
*_switch_to(struct task_struct
*, struct task_struct
*);
48 #define switch_to(prev, next, last) do { \
49 (last) = _switch_to(prev, next); \
53 * On SMP systems, when the scheduler does migration-cost autodetection,
54 * it needs a way to flush as much of the CPU's caches as possible.
58 static inline void sched_cacheflush(void)
63 /* interrupt control */
64 #define local_save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory")
65 #define local_irq_disable() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
66 #define local_irq_enable() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
68 #define local_irq_save(x) \
69 __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" )
70 #define local_irq_restore(x) \
71 __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" )
73 #define irqs_disabled() \
75 unsigned long flags; \
76 local_save_flags(flags); \
77 (flags & PSW_I) == 0; \
80 #define mfctl(reg) ({ \
82 __asm__ __volatile__( \
83 "mfctl " #reg ",%0" : \
89 #define mtctl(gr, cr) \
90 __asm__ __volatile__("mtctl %0,%1" \
92 : "r" (gr), "i" (cr) : "memory")
94 /* these are here to de-mystefy the calling code, and to provide hooks */
95 /* which I needed for debugging EIEM problems -PB */
96 #define get_eiem() mfctl(15)
97 static inline void set_eiem(unsigned long val
)
102 #define mfsp(reg) ({ \
104 __asm__ __volatile__( \
105 "mfsp " #reg ",%0" : \
111 #define mtsp(gr, cr) \
112 __asm__ __volatile__("mtsp %0,%1" \
114 : "r" (gr), "i" (cr) : "memory")
118 ** This is simply the barrier() macro from linux/kernel.h but when serial.c
119 ** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
120 ** hasn't yet been included yet so it fails, thus repeating the macro here.
122 ** PA-RISC architecture allows for weakly ordered memory accesses although
123 ** none of the processors use it. There is a strong ordered bit that is
124 ** set in the O-bit of the page directory entry. Operating systems that
125 ** can not tolerate out of order accesses should set this bit when mapping
126 ** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
127 ** of the processor implemented the PSW O-bit). The PCX-W ERS states that
128 ** the TLB O-bit is not implemented so the page directory does not need to
129 ** have the O-bit set when mapping pages (section 3.1). This section also
130 ** states that the PSW Y, Z, G, and O bits are not implemented.
131 ** So it looks like nothing needs to be done for parisc-linux (yet).
132 ** (thanks to chada for the above comment -ggg)
134 ** The __asm__ op below simple prevents gcc/ld from reordering
135 ** instructions across the mb() "call".
137 #define mb() __asm__ __volatile__("":::"memory") /* barrier() */
140 #define smp_mb() mb()
141 #define smp_rmb() mb()
142 #define smp_wmb() mb()
143 #define smp_read_barrier_depends() do { } while(0)
144 #define read_barrier_depends() do { } while(0)
146 #define set_mb(var, value) do { var = value; mb(); } while (0)
147 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
151 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
152 and GCC only guarantees 8-byte alignment for stack locals, we can't
153 be assured of 16-byte alignment for atomic lock data even if we
154 specify "__attribute ((aligned(16)))" in the type declaration. So,
155 we use a struct containing an array of four ints for the atomic lock
156 type and dynamically select the 16-byte aligned int from the array
157 for the semaphore. */
159 #define __PA_LDCW_ALIGNMENT 16
160 #define __ldcw_align(a) ({ \
161 unsigned long __ret = (unsigned long) &(a)->lock[0]; \
162 __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \
163 (volatile unsigned int *) __ret; \
167 #else /*CONFIG_PA20*/
168 /* From: "Jim Hull" <jim.hull of hp.com>
169 I've attached a summary of the change, but basically, for PA 2.0, as
170 long as the ",CO" (coherent operation) completer is specified, then the
171 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
172 they only require "natural" alignment (4-byte for ldcw, 8-byte for
175 #define __PA_LDCW_ALIGNMENT 4
176 #define __ldcw_align(a) ((volatile unsigned int *)a)
177 #define LDCW "ldcw,co"
179 #endif /*!CONFIG_PA20*/
181 /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
182 #define __ldcw(a) ({ \
184 __asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \
189 # define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
192 #define KERNEL_START (0x10100000 - 0x1000)
193 #define arch_align_stack(x) (x)