2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
25 * @bus: pointer to PCI bus structure to search
27 * Given a PCI bus, returns the highest PCI bus number present in the set
28 * including the given PCI bus and its list of child PCI buses.
30 unsigned char __devinit
31 pci_bus_max_busnr(struct pci_bus
* bus
)
33 struct list_head
*tmp
;
37 list_for_each(tmp
, &bus
->children
) {
38 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
46 * pci_max_busnr - returns maximum PCI bus number
48 * Returns the highest PCI bus number present in the system global list of
51 unsigned char __devinit
54 struct pci_bus
*bus
= NULL
;
58 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
59 n
= pci_bus_max_busnr(bus
);
66 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 pos
, int cap
)
72 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
76 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
82 pos
+= PCI_CAP_LIST_NEXT
;
87 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
89 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
90 pos
+ PCI_CAP_LIST_NEXT
, cap
);
92 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
94 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
99 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
100 if (!(status
& PCI_STATUS_CAP_LIST
))
104 case PCI_HEADER_TYPE_NORMAL
:
105 case PCI_HEADER_TYPE_BRIDGE
:
106 pos
= PCI_CAPABILITY_LIST
;
108 case PCI_HEADER_TYPE_CARDBUS
:
109 pos
= PCI_CB_CAPABILITY_LIST
;
114 return __pci_find_next_cap(bus
, devfn
, pos
, cap
);
118 * pci_find_capability - query for devices' capabilities
119 * @dev: PCI device to query
120 * @cap: capability code
122 * Tell if a device supports a given PCI capability.
123 * Returns the address of the requested capability structure within the
124 * device's PCI configuration space or 0 in case the device does not
125 * support it. Possible values for @cap:
127 * %PCI_CAP_ID_PM Power Management
128 * %PCI_CAP_ID_AGP Accelerated Graphics Port
129 * %PCI_CAP_ID_VPD Vital Product Data
130 * %PCI_CAP_ID_SLOTID Slot Identification
131 * %PCI_CAP_ID_MSI Message Signalled Interrupts
132 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
133 * %PCI_CAP_ID_PCIX PCI-X
134 * %PCI_CAP_ID_EXP PCI Express
136 int pci_find_capability(struct pci_dev
*dev
, int cap
)
138 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
142 * pci_bus_find_capability - query for devices' capabilities
143 * @bus: the PCI bus to query
144 * @devfn: PCI device to query
145 * @cap: capability code
147 * Like pci_find_capability() but works for pci devices that do not have a
148 * pci_dev structure set up yet.
150 * Returns the address of the requested capability structure within the
151 * device's PCI configuration space or 0 in case the device does not
154 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
158 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
160 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
164 * pci_find_ext_capability - Find an extended capability
165 * @dev: PCI device to query
166 * @cap: capability code
168 * Returns the address of the requested extended capability structure
169 * within the device's PCI configuration space or 0 if the device does
170 * not support it. Possible values for @cap:
172 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
173 * %PCI_EXT_CAP_ID_VC Virtual Channel
174 * %PCI_EXT_CAP_ID_DSN Device Serial Number
175 * %PCI_EXT_CAP_ID_PWR Power Budgeting
177 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
180 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
183 if (dev
->cfg_size
<= 256)
186 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
190 * If we have no capabilities, this is indicated by cap ID,
191 * cap version and next pointer all being 0.
197 if (PCI_EXT_CAP_ID(header
) == cap
)
200 pos
= PCI_EXT_CAP_NEXT(header
);
204 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
212 * pci_find_parent_resource - return resource region of parent bus of given region
213 * @dev: PCI device structure contains resources to be searched
214 * @res: child resource record for which parent is sought
216 * For given resource region of given device, return the resource
217 * region of parent bus the given region is contained in or where
218 * it should be allocated from.
221 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
223 const struct pci_bus
*bus
= dev
->bus
;
225 struct resource
*best
= NULL
;
227 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
228 struct resource
*r
= bus
->resource
[i
];
231 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
232 continue; /* Not contained */
233 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
234 continue; /* Wrong type */
235 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
236 return r
; /* Exact match */
237 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
238 best
= r
; /* Approximating prefetchable by non-prefetchable */
244 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
245 * @dev: PCI device to have its BARs restored
247 * Restore the BAR values for a given device, so as to make it
248 * accessible by its driver.
251 pci_restore_bars(struct pci_dev
*dev
)
255 switch (dev
->hdr_type
) {
256 case PCI_HEADER_TYPE_NORMAL
:
259 case PCI_HEADER_TYPE_BRIDGE
:
262 case PCI_HEADER_TYPE_CARDBUS
:
266 /* Should never get here, but just in case... */
270 for (i
= 0; i
< numres
; i
++)
271 pci_update_resource(dev
, &dev
->resource
[i
], i
);
274 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
277 * pci_set_power_state - Set the power state of a PCI device
278 * @dev: PCI device to be suspended
279 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
281 * Transition a device to a new power state, using the Power Management
282 * Capabilities in the device's config space.
285 * -EINVAL if trying to enter a lower state than we're already in.
286 * 0 if we're already in the requested state.
287 * -EIO if device does not support PCI PM.
288 * 0 if we can successfully change the power state.
291 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
293 int pm
, need_restore
= 0;
296 /* bound the state we're entering */
297 if (state
> PCI_D3hot
)
300 /* Validate current state:
301 * Can enter D0 from any state, but if we can only go deeper
302 * to sleep if we're already in a low power state
304 if (state
!= PCI_D0
&& dev
->current_state
> state
)
306 else if (dev
->current_state
== state
)
307 return 0; /* we're already there */
309 /* find PCI PM capability in list */
310 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
312 /* abort if the device doesn't support PM capabilities */
316 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
317 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
319 "PCI: %s has unsupported PM cap regs version (%u)\n",
320 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
324 /* check if this device supports the desired state */
325 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
327 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
330 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
332 /* If we're (effectively) in D3, force entire word to 0.
333 * This doesn't affect PME_Status, disables PME_En, and
334 * sets PowerState to 0.
336 switch (dev
->current_state
) {
340 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
343 case PCI_UNKNOWN
: /* Boot-up */
344 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
345 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
347 /* Fall-through: force to D0 */
353 /* enter specified state */
354 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
356 /* Mandatory power management transition delays */
357 /* see PCI PM 1.1 5.6.1 table 18 */
358 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
360 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
364 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
365 * Firmware method after natice method ?
367 if (platform_pci_set_power_state
)
368 platform_pci_set_power_state(dev
, state
);
370 dev
->current_state
= state
;
372 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
373 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
374 * from D3hot to D0 _may_ perform an internal reset, thereby
375 * going to "D0 Uninitialized" rather than "D0 Initialized".
376 * For example, at least some versions of the 3c905B and the
377 * 3c556B exhibit this behaviour.
379 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
380 * devices in a D3hot state at boot. Consequently, we need to
381 * restore at least the BARs so that the device will be
382 * accessible to its driver.
385 pci_restore_bars(dev
);
390 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
393 * pci_choose_state - Choose the power state of a PCI device
394 * @dev: PCI device to be suspended
395 * @state: target sleep state for the whole system. This is the value
396 * that is passed to suspend() function.
398 * Returns PCI power state suitable for given device and given system
402 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
406 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
409 if (platform_pci_choose_state
) {
410 ret
= platform_pci_choose_state(dev
, state
);
415 switch (state
.event
) {
418 case PM_EVENT_FREEZE
:
419 case PM_EVENT_SUSPEND
:
422 printk("They asked me for state %d\n", state
.event
);
428 EXPORT_SYMBOL(pci_choose_state
);
431 * pci_save_state - save the PCI configuration space of a device before suspending
432 * @dev: - PCI device that we're dealing with
435 pci_save_state(struct pci_dev
*dev
)
438 /* XXX: 100% dword access ok here? */
439 for (i
= 0; i
< 16; i
++)
440 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
445 * pci_restore_state - Restore the saved state of a PCI device
446 * @dev: - PCI device that we're dealing with
449 pci_restore_state(struct pci_dev
*dev
)
453 for (i
= 0; i
< 16; i
++)
454 pci_write_config_dword(dev
,i
* 4, dev
->saved_config_space
[i
]);
459 * pci_enable_device_bars - Initialize some of a device for use
460 * @dev: PCI device to be initialized
461 * @bars: bitmask of BAR's that must be configured
463 * Initialize device before it's used by a driver. Ask low-level code
464 * to enable selected I/O and memory resources. Wake up the device if it
465 * was suspended. Beware, this function can fail.
469 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
473 err
= pci_set_power_state(dev
, PCI_D0
);
474 if (err
< 0 && err
!= -EIO
)
476 err
= pcibios_enable_device(dev
, bars
);
483 * pci_enable_device - Initialize device before it's used by a driver.
484 * @dev: PCI device to be initialized
486 * Initialize device before it's used by a driver. Ask low-level code
487 * to enable I/O and memory. Wake up the device if it was suspended.
488 * Beware, this function can fail.
491 pci_enable_device(struct pci_dev
*dev
)
495 if ((err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1)))
497 pci_fixup_device(pci_fixup_enable
, dev
);
503 * pcibios_disable_device - disable arch specific PCI resources for device dev
504 * @dev: the PCI device to disable
506 * Disables architecture specific PCI resources for the device. This
507 * is the default implementation. Architecture implementations can
510 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
513 * pci_disable_device - Disable PCI device after use
514 * @dev: PCI device to be disabled
516 * Signal to the system that the PCI device is not in use by the system
517 * anymore. This only involves disabling PCI bus-mastering, if active.
520 pci_disable_device(struct pci_dev
*dev
)
524 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
525 if (pci_command
& PCI_COMMAND_MASTER
) {
526 pci_command
&= ~PCI_COMMAND_MASTER
;
527 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
529 dev
->is_busmaster
= 0;
531 pcibios_disable_device(dev
);
536 * pci_enable_wake - enable device to generate PME# when suspended
537 * @dev: - PCI device to operate on
538 * @state: - Current state of device.
539 * @enable: - Flag to enable or disable generation
541 * Set the bits in the device's PM Capabilities to generate PME# when
542 * the system is suspended.
544 * -EIO is returned if device doesn't have PM Capabilities.
545 * -EINVAL is returned if device supports it, but can't generate wake events.
546 * 0 if operation is successful.
549 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
554 /* find PCI PM capability in list */
555 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
557 /* If device doesn't support PM Capabilities, but request is to disable
558 * wake events, it's a nop; otherwise fail */
560 return enable
? -EIO
: 0;
562 /* Check device's ability to generate PME# */
563 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
565 value
&= PCI_PM_CAP_PME_MASK
;
566 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
568 /* Check if it can generate PME# from requested state. */
569 if (!value
|| !(value
& (1 << state
)))
570 return enable
? -EINVAL
: 0;
572 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
574 /* Clear PME_Status by writing 1 to it and enable PME# */
575 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
578 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
580 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
586 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
590 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
594 while (dev
->bus
->self
) {
595 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
596 dev
= dev
->bus
->self
;
603 * pci_release_region - Release a PCI bar
604 * @pdev: PCI device whose resources were previously reserved by pci_request_region
605 * @bar: BAR to release
607 * Releases the PCI I/O and memory resources previously reserved by a
608 * successful call to pci_request_region. Call this function only
609 * after all use of the PCI regions has ceased.
611 void pci_release_region(struct pci_dev
*pdev
, int bar
)
613 if (pci_resource_len(pdev
, bar
) == 0)
615 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
616 release_region(pci_resource_start(pdev
, bar
),
617 pci_resource_len(pdev
, bar
));
618 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
619 release_mem_region(pci_resource_start(pdev
, bar
),
620 pci_resource_len(pdev
, bar
));
624 * pci_request_region - Reserved PCI I/O and memory resource
625 * @pdev: PCI device whose resources are to be reserved
626 * @bar: BAR to be reserved
627 * @res_name: Name to be associated with resource.
629 * Mark the PCI region associated with PCI device @pdev BR @bar as
630 * being reserved by owner @res_name. Do not access any
631 * address inside the PCI regions unless this call returns
634 * Returns 0 on success, or %EBUSY on error. A warning
635 * message is also printed on failure.
637 int pci_request_region(struct pci_dev
*pdev
, int bar
, char *res_name
)
639 if (pci_resource_len(pdev
, bar
) == 0)
642 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
643 if (!request_region(pci_resource_start(pdev
, bar
),
644 pci_resource_len(pdev
, bar
), res_name
))
647 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
648 if (!request_mem_region(pci_resource_start(pdev
, bar
),
649 pci_resource_len(pdev
, bar
), res_name
))
656 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
657 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
658 bar
+ 1, /* PCI BAR # */
659 pci_resource_len(pdev
, bar
), pci_resource_start(pdev
, bar
),
666 * pci_release_regions - Release reserved PCI I/O and memory resources
667 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
669 * Releases all PCI I/O and memory resources previously reserved by a
670 * successful call to pci_request_regions. Call this function only
671 * after all use of the PCI regions has ceased.
674 void pci_release_regions(struct pci_dev
*pdev
)
678 for (i
= 0; i
< 6; i
++)
679 pci_release_region(pdev
, i
);
683 * pci_request_regions - Reserved PCI I/O and memory resources
684 * @pdev: PCI device whose resources are to be reserved
685 * @res_name: Name to be associated with resource.
687 * Mark all PCI regions associated with PCI device @pdev as
688 * being reserved by owner @res_name. Do not access any
689 * address inside the PCI regions unless this call returns
692 * Returns 0 on success, or %EBUSY on error. A warning
693 * message is also printed on failure.
695 int pci_request_regions(struct pci_dev
*pdev
, char *res_name
)
699 for (i
= 0; i
< 6; i
++)
700 if(pci_request_region(pdev
, i
, res_name
))
706 pci_release_region(pdev
, i
);
712 * pci_set_master - enables bus-mastering for device dev
713 * @dev: the PCI device to enable
715 * Enables bus-mastering on the device and calls pcibios_set_master()
716 * to do the needed arch specific settings.
719 pci_set_master(struct pci_dev
*dev
)
723 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
724 if (! (cmd
& PCI_COMMAND_MASTER
)) {
725 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
726 cmd
|= PCI_COMMAND_MASTER
;
727 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
729 dev
->is_busmaster
= 1;
730 pcibios_set_master(dev
);
733 #ifndef HAVE_ARCH_PCI_MWI
734 /* This can be overridden by arch code. */
735 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
738 * pci_generic_prep_mwi - helper function for pci_set_mwi
739 * @dev: the PCI device for which MWI is enabled
741 * Helper function for generic implementation of pcibios_prep_mwi
742 * function. Originally copied from drivers/net/acenic.c.
743 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
745 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
748 pci_generic_prep_mwi(struct pci_dev
*dev
)
752 if (!pci_cache_line_size
)
753 return -EINVAL
; /* The system doesn't support MWI. */
755 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
756 equal to or multiple of the right value. */
757 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
758 if (cacheline_size
>= pci_cache_line_size
&&
759 (cacheline_size
% pci_cache_line_size
) == 0)
762 /* Write the correct value. */
763 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
765 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
766 if (cacheline_size
== pci_cache_line_size
)
769 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
770 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
774 #endif /* !HAVE_ARCH_PCI_MWI */
777 * pci_set_mwi - enables memory-write-invalidate PCI transaction
778 * @dev: the PCI device for which MWI is enabled
780 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
781 * and then calls @pcibios_set_mwi to do the needed arch specific
782 * operations or a generic mwi-prep function.
784 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
787 pci_set_mwi(struct pci_dev
*dev
)
792 #ifdef HAVE_ARCH_PCI_MWI
793 rc
= pcibios_prep_mwi(dev
);
795 rc
= pci_generic_prep_mwi(dev
);
801 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
802 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
803 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
804 cmd
|= PCI_COMMAND_INVALIDATE
;
805 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
812 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
813 * @dev: the PCI device to disable
815 * Disables PCI Memory-Write-Invalidate transaction on the device
818 pci_clear_mwi(struct pci_dev
*dev
)
822 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
823 if (cmd
& PCI_COMMAND_INVALIDATE
) {
824 cmd
&= ~PCI_COMMAND_INVALIDATE
;
825 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
830 * pci_intx - enables/disables PCI INTx for device dev
831 * @pdev: the PCI device to operate on
832 * @enable: boolean: whether to enable or disable PCI INTx
834 * Enables/disables PCI INTx for device dev
837 pci_intx(struct pci_dev
*pdev
, int enable
)
839 u16 pci_command
, new;
841 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
844 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
846 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
849 if (new != pci_command
) {
850 pci_write_config_word(pdev
, PCI_COMMAND
, new);
854 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
856 * These can be overridden by arch-specific implementations
859 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
861 if (!pci_dma_supported(dev
, mask
))
864 dev
->dma_mask
= mask
;
870 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
872 if (!pci_dma_supported(dev
, mask
))
875 dev
->dev
.coherent_dma_mask
= mask
;
881 static int __devinit
pci_init(void)
883 struct pci_dev
*dev
= NULL
;
885 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
886 pci_fixup_device(pci_fixup_final
, dev
);
891 static int __devinit
pci_setup(char *str
)
894 char *k
= strchr(str
, ',');
897 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
898 /* PCI layer options should be handled here */
899 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
906 device_initcall(pci_init
);
908 __setup("pci=", pci_setup
);
910 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
911 /* FIXME: Some boxes have multiple ISA bridges! */
912 struct pci_dev
*isa_bridge
;
913 EXPORT_SYMBOL(isa_bridge
);
916 EXPORT_SYMBOL_GPL(pci_restore_bars
);
917 EXPORT_SYMBOL(pci_enable_device_bars
);
918 EXPORT_SYMBOL(pci_enable_device
);
919 EXPORT_SYMBOL(pci_disable_device
);
920 EXPORT_SYMBOL(pci_max_busnr
);
921 EXPORT_SYMBOL(pci_bus_max_busnr
);
922 EXPORT_SYMBOL(pci_find_capability
);
923 EXPORT_SYMBOL(pci_bus_find_capability
);
924 EXPORT_SYMBOL(pci_release_regions
);
925 EXPORT_SYMBOL(pci_request_regions
);
926 EXPORT_SYMBOL(pci_release_region
);
927 EXPORT_SYMBOL(pci_request_region
);
928 EXPORT_SYMBOL(pci_set_master
);
929 EXPORT_SYMBOL(pci_set_mwi
);
930 EXPORT_SYMBOL(pci_clear_mwi
);
931 EXPORT_SYMBOL_GPL(pci_intx
);
932 EXPORT_SYMBOL(pci_set_dma_mask
);
933 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
934 EXPORT_SYMBOL(pci_assign_resource
);
935 EXPORT_SYMBOL(pci_find_parent_resource
);
937 EXPORT_SYMBOL(pci_set_power_state
);
938 EXPORT_SYMBOL(pci_save_state
);
939 EXPORT_SYMBOL(pci_restore_state
);
940 EXPORT_SYMBOL(pci_enable_wake
);
944 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
945 EXPORT_SYMBOL(pci_pci_problems
);