2 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
12 #ifndef __SAVAGEFB_H__
13 #define __SAVAGEFB_H__
15 #include <linux/i2c.h>
16 #include <linux/i2c-id.h>
17 #include <linux/i2c-algo-bit.h>
21 # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
24 # define SavagePrintRegs(...)
28 #define PCI_CHIP_SAVAGE4 0x8a22
29 #define PCI_CHIP_SAVAGE3D 0x8a20
30 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
31 #define PCI_CHIP_SAVAGE2000 0x9102
32 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
33 #define PCI_CHIP_SAVAGE_MX 0x8c11
34 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
35 #define PCI_CHIP_SAVAGE_IX 0x8c13
36 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
37 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
38 /* Twister is a code name; hope I get the real name soon. */
39 #define PCI_CHIP_S3TWISTER_P 0x8d01
40 #define PCI_CHIP_S3TWISTER_K 0x8d02
41 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43 #define PCI_CHIP_SUPSAV_MX128 0x8c22
44 #define PCI_CHIP_SUPSAV_MX64 0x8c24
45 #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
55 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
57 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
59 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
61 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
63 /* Chip tags. These are used to group the adapters into
78 #define BIOS_BSIZE 1024
79 #define BIOS_BASE 0xc0000
81 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
82 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
83 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
84 #define SAVAGE_NEWMMIO_VGABASE 0x8000
86 #define BASE_FREQ 14318
87 #define HALF_BASE_FREQ 7159
89 #define FIFO_CONTROL_REG 0x8200
90 #define MIU_CONTROL_REG 0x8204
91 #define STREAMS_TIMEOUT_REG 0x8208
92 #define MISC_TIMEOUT_REG 0x820c
94 #define MONO_PAT_0 0xa4e8
95 #define MONO_PAT_1 0xa4ec
97 #define MAXFIFO 0x7f00
99 #define BCI_CMD_NOP 0x40000000
100 #define BCI_CMD_SETREG 0x96000000
101 #define BCI_CMD_RECT 0x48000000
102 #define BCI_CMD_RECT_XP 0x01000000
103 #define BCI_CMD_RECT_YP 0x02000000
104 #define BCI_CMD_SEND_COLOR 0x00008000
105 #define BCI_CMD_DEST_GBD 0x00000000
106 #define BCI_CMD_SRC_GBD 0x00000020
107 #define BCI_CMD_SRC_SOLID 0x00000000
108 #define BCI_CMD_SRC_MONO 0x00000060
109 #define BCI_CMD_CLIP_NEW 0x00006000
110 #define BCI_CMD_CLIP_LR 0x00004000
112 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
113 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
114 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
115 #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
116 #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
118 #define BCI_GBD1 0xE0
119 #define BCI_GBD2 0xE1
121 #define BCI_BUFFER_OFFSET 0x10000
122 #define BCI_SIZE 0x4000
124 #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
126 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
127 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
128 #define BCI_CMD_SEND_COLOR 0x00008000
136 unsigned int HDisplay
;
137 unsigned int HSyncStart
;
138 unsigned int HSyncEnd
;
140 unsigned int HAdjusted
;
141 unsigned int VDisplay
;
142 unsigned int VSyncStart
;
143 unsigned int VSyncEnd
;
151 /* --------------------------------------------------------------------- */
153 #define NR_PALETTE 256
158 struct savagefb_i2c_chan
{
159 struct savagefb_par
*par
;
160 struct i2c_adapter adapter
;
161 struct i2c_algo_bit_data algo
;
162 volatile u8 __iomem
*ioaddr
;
166 struct savagefb_par
{
167 struct pci_dev
*pcidev
;
169 struct savagefb_i2c_chan chan
;
171 u32 pseudo_palette
[16];
191 volatile u8 __iomem
*vbase
;
196 volatile u32 __iomem
*bci_base
;
197 unsigned int bci_ptr
;
203 void (*SavageWaitIdle
) (struct savagefb_par
*par
);
204 void (*SavageWaitFifo
) (struct savagefb_par
*par
, int space
);
206 int MCLK
, REFCLK
, LCDclk
;
207 int HorizScaleFactor
;
210 int SavagePanelWidth
;
211 int SavagePanelHeight
;
214 u16 red
, green
, blue
, transp
;
215 } palette
[NR_PALETTE
];
220 unsigned char MiscOutReg
; /* Misc */
221 unsigned char CRTC
[25]; /* Crtc Controller */
222 unsigned char Sequencer
[5]; /* Video Sequencer */
223 unsigned char Graphics
[9]; /* Video Graphics */
224 unsigned char Attribute
[21]; /* Video Atribute */
226 unsigned int mode
, refresh
;
227 unsigned char SR08
, SR0E
, SR0F
;
228 unsigned char SR10
, SR11
, SR12
, SR13
, SR15
, SR18
, SR29
, SR30
;
229 unsigned char SR54
[8];
231 unsigned char CR31
, CR32
, CR33
, CR34
, CR36
, CR3A
, CR3B
, CR3C
;
232 unsigned char CR40
, CR41
, CR42
, CR43
, CR45
;
233 unsigned char CR50
, CR51
, CR53
, CR55
, CR58
, CR5B
, CR5D
, CR5E
;
234 unsigned char CR60
, CR63
, CR65
, CR66
, CR67
, CR68
, CR69
, CR6D
, CR6F
;
235 unsigned char CR86
, CR88
;
236 unsigned char CR90
, CR91
, CRB0
;
237 unsigned int STREAMS
[22]; /* yuck, streams regs */
238 unsigned int MMPR0
, MMPR1
, MMPR2
, MMPR3
;
241 #define BCI_BD_BW_DISABLE 0x10000000
242 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
243 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
248 #define vga_in8(addr) (inb (addr))
249 #define vga_in16(addr) (inw (addr))
250 #define vga_in32(addr) (inl (addr))
252 #define vga_out8(addr,val) (outb ((val), (addr)))
253 #define vga_out16(addr,val) (outw ((val), (addr)))
254 #define vga_out32(addr,val) (outl ((val), (addr)))
256 #define savage_in16(addr) readw(par->mmio.vbase + (addr))
257 #define savage_in32(addr) readl(par->mmio.vbase + (addr))
259 #define savage_out16(addr,val) writew((val), par->mmio.vbase + (addr))
260 #define savage_out32(addr,val) writel((val), par->mmio.vbase + (addr))
262 static inline u8
VGArCR (u8 index
)
268 static inline u8
VGArGR (u8 index
)
274 static inline u8
VGArSEQ (u8 index
)
280 #define VGAwCR(index, val) \
282 vga_out8 (0x3d4, index); \
283 vga_out8 (0x3d5, val); \
286 #define VGAwGR(index, val) \
288 vga_out8 (0x3ce, index); \
289 vga_out8 (0x3cf, val); \
292 #define VGAwSEQ(index, val) \
294 vga_out8 (0x3c4, index); \
295 vga_out8 (0x3c5, val); \
298 #define VGAenablePalette() \
302 tmp = vga_in8 (0x3da); \
303 vga_out8 (0x3c0, 0x00); \
304 paletteEnabled = 1; \
307 #define VGAdisablePalette() \
311 tmp = vga_in8 (0x3da); \
312 vga_out8 (0x3c0, 0x20); \
313 paletteEnabled = 0; \
316 #define VGAwATTR(index, value) \
320 if (paletteEnabled) \
325 tmp = vga_in8 (0x3da); \
326 vga_out8 (0x3c0, index); \
327 vga_out8 (0x3c0, value); \
330 #define VGAwMISC(value) \
332 vga_out8 (0x3c2, value); \
335 #ifndef CONFIG_FB_SAVAGE_ACCEL
336 #define savagefb_set_clip(x)
339 #define VerticalRetraceWait() \
341 vga_out8 (0x3d4, 0x17); \
342 if (vga_in8 (0x3d5) & 0x80) { \
343 while ((vga_in8(0x3da) & 0x08) == 0x08) ; \
344 while ((vga_in8(0x3da) & 0x08) == 0x00) ; \
348 extern int savagefb_probe_i2c_connector(struct fb_info
*info
,
350 extern void savagefb_create_i2c_busses(struct fb_info
*info
);
351 extern void savagefb_delete_i2c_busses(struct fb_info
*info
);
352 extern int savagefb_sync(struct fb_info
*info
);
353 extern void savagefb_copyarea(struct fb_info
*info
,
354 const struct fb_copyarea
*region
);
355 extern void savagefb_fillrect(struct fb_info
*info
,
356 const struct fb_fillrect
*rect
);
357 extern void savagefb_imageblit(struct fb_info
*info
,
358 const struct fb_image
*image
);
361 #endif /* __SAVAGEFB_H__ */