2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.3"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
127 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
129 /* Avoid conditionals by using array */
130 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
131 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
132 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
134 /* This driver supports yukon2 chipset only */
135 static const char *yukon2_name
[] = {
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
143 /* Access to external PHY */
144 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
148 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
149 gma_write16(hw
, port
, GM_SMI_CTRL
,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
152 for (i
= 0; i
< PHY_RETRIES
; i
++) {
153 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
158 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
162 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
166 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
167 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
169 for (i
= 0; i
< PHY_RETRIES
; i
++) {
170 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
171 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
181 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
185 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
186 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
190 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
197 pr_debug("sky2_set_power_state %d\n", state
);
198 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
200 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
201 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
202 (power_control
& PCI_PM_CAP_PME_D3cold
);
204 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
206 power_control
|= PCI_PM_CTRL_PME_STATUS
;
207 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw
, B0_POWER_CTRL
,
213 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
215 /* disable Core Clock Division, */
216 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
218 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
219 /* enable bits are inverted */
220 sky2_write8(hw
, B2_Y2_CLK_GATE
,
221 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
222 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
223 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
225 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
227 /* Turn off phy power saving */
228 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
229 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
231 /* looks like this XL is back asswards .. */
232 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
233 reg1
|= PCI_Y2_PHY1_COMA
;
235 reg1
|= PCI_Y2_PHY2_COMA
;
238 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
239 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_ON
);
240 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
241 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
242 reg1
&= P_ASPM_CONTROL_MSK
;
243 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
244 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
247 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
253 /* Turn on phy power saving */
254 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
255 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
256 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
258 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
259 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
261 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
262 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw
, B2_Y2_CLK_GATE
,
266 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
267 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
268 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
270 /* switch power to VAUX */
271 if (vaux
&& state
!= PCI_D3cold
)
272 sky2_write8(hw
, B0_POWER_CTRL
,
273 (PC_VAUX_ENA
| PC_VCC_ENA
|
274 PC_VAUX_ON
| PC_VCC_OFF
));
277 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
281 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
282 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
286 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
292 /* disable PHY IRQs */
293 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
296 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
297 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
298 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
300 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
301 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
302 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
305 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
307 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
308 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
310 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
311 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
312 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
314 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
316 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
318 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
319 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
321 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
323 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
326 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
328 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
329 /* enable automatic crossover */
330 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
332 /* disable energy detect */
333 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
335 /* enable automatic crossover */
336 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
338 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
339 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
340 ctrl
&= ~PHY_M_PC_DSC_MSK
;
341 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
344 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
346 /* workaround for deviation #4.88 (CRC errors) */
347 /* disable Automatic Crossover */
349 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
350 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
352 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
355 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
356 ctrl
&= ~PHY_M_MAC_MD_MSK
;
357 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
358 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
360 /* select page 1 to access Fiber registers */
361 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
365 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
366 if (sky2
->autoneg
== AUTONEG_DISABLE
)
371 ctrl
|= PHY_CT_RESET
;
372 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
378 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
380 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
381 ct1000
|= PHY_M_1000C_AFD
;
382 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
383 ct1000
|= PHY_M_1000C_AHD
;
384 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
385 adv
|= PHY_M_AN_100_FD
;
386 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
387 adv
|= PHY_M_AN_100_HD
;
388 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
389 adv
|= PHY_M_AN_10_FD
;
390 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
391 adv
|= PHY_M_AN_10_HD
;
392 } else /* special defines for FIBER (88E1011S only) */
393 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
395 /* Set Flow-control capabilities */
396 if (sky2
->tx_pause
&& sky2
->rx_pause
)
397 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
398 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
399 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
400 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
401 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
403 /* Restart Auto-negotiation */
404 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
406 /* forced speed/duplex settings */
407 ct1000
= PHY_M_1000C_MSE
;
409 if (sky2
->duplex
== DUPLEX_FULL
)
410 ctrl
|= PHY_CT_DUP_MD
;
412 switch (sky2
->speed
) {
414 ctrl
|= PHY_CT_SP1000
;
417 ctrl
|= PHY_CT_SP100
;
421 ctrl
|= PHY_CT_RESET
;
424 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
425 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
427 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
428 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
430 /* Setup Phy LED's */
431 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
434 switch (hw
->chip_id
) {
435 case CHIP_ID_YUKON_FE
:
436 /* on 88E3082 these bits are at 11..9 (shifted left) */
437 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
439 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
441 /* delete ACT LED control bits */
442 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
443 /* change ACT LED control to blink mode */
444 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
445 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
448 case CHIP_ID_YUKON_XL
:
449 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
451 /* select page 3 to access LED control register */
452 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
454 /* set LED Function Control register */
455 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
456 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
457 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
458 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
459 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
461 /* set Polarity Control register */
462 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
463 (PHY_M_POLC_LS1_P_MIX(4) |
464 PHY_M_POLC_IS0_P_MIX(4) |
465 PHY_M_POLC_LOS_CTRL(2) |
466 PHY_M_POLC_INIT_CTRL(2) |
467 PHY_M_POLC_STA1_CTRL(2) |
468 PHY_M_POLC_STA0_CTRL(2)));
470 /* restore page register */
471 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
473 case CHIP_ID_YUKON_EC_U
:
474 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
476 /* select page 3 to access LED control register */
477 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
479 /* set LED Function Control register */
480 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
481 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
482 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
483 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
484 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
486 /* set Blink Rate in LED Timer Control Register */
487 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
488 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
489 /* restore page register */
490 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
494 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
495 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
496 /* turn off the Rx LED (LED_RX) */
497 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
500 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
501 /* apply fixes in PHY AFE */
502 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
503 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
505 /* increase differential signal amplitude in 10BASE-T */
506 gm_phy_write(hw
, port
, 0x18, 0xaa99);
507 gm_phy_write(hw
, port
, 0x17, 0x2011);
509 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
510 gm_phy_write(hw
, port
, 0x18, 0xa204);
511 gm_phy_write(hw
, port
, 0x17, 0x2002);
513 /* set page register to 0 */
514 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
516 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
518 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
519 /* turn on 100 Mbps LED (LED_LINK100) */
520 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
524 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
527 /* Enable phy interrupt on auto-negotiation complete (or link up) */
528 if (sky2
->autoneg
== AUTONEG_ENABLE
)
529 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
531 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
534 /* Force a renegotiation */
535 static void sky2_phy_reinit(struct sky2_port
*sky2
)
537 spin_lock_bh(&sky2
->phy_lock
);
538 sky2_phy_init(sky2
->hw
, sky2
->port
);
539 spin_unlock_bh(&sky2
->phy_lock
);
542 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
544 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
547 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
549 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
550 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
552 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
554 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
555 /* WA DEV_472 -- looks like crossed wires on port 2 */
556 /* clear GMAC 1 Control reset */
557 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
559 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
560 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
561 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
562 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
563 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
566 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
567 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
568 reg
|= GM_GPCR_AU_ALL_DIS
;
569 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
570 gma_read16(hw
, port
, GM_GP_CTRL
);
572 switch (sky2
->speed
) {
574 reg
&= ~GM_GPCR_SPEED_100
;
575 reg
|= GM_GPCR_SPEED_1000
;
578 reg
&= ~GM_GPCR_SPEED_1000
;
579 reg
|= GM_GPCR_SPEED_100
;
582 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
586 if (sky2
->duplex
== DUPLEX_FULL
)
587 reg
|= GM_GPCR_DUP_FULL
;
589 /* turn off pause in 10/100mbps half duplex */
590 else if (sky2
->speed
!= SPEED_1000
&&
591 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
592 sky2
->tx_pause
= sky2
->rx_pause
= 0;
594 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
596 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
597 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
599 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
600 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
601 /* disable Rx flow-control */
602 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
605 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
607 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
609 spin_lock_bh(&sky2
->phy_lock
);
610 sky2_phy_init(hw
, port
);
611 spin_unlock_bh(&sky2
->phy_lock
);
614 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
615 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
617 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
618 gma_read16(hw
, port
, i
);
619 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
621 /* transmit control */
622 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
624 /* receive control reg: unicast + multicast + no FCS */
625 gma_write16(hw
, port
, GM_RX_CTRL
,
626 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
628 /* transmit flow control */
629 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
631 /* transmit parameter */
632 gma_write16(hw
, port
, GM_TX_PARAM
,
633 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
634 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
635 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
636 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
638 /* serial mode register */
639 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
640 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
642 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
643 reg
|= GM_SMOD_JUMBO_ENA
;
645 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
647 /* virtual address for data */
648 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
650 /* physical address: used for pause frames */
651 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
653 /* ignore counter overflows */
654 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
655 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
656 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
658 /* Configure Rx MAC FIFO */
659 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
660 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
661 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
663 /* Flush Rx MAC FIFO on any flow control or error */
664 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
666 /* Set threshold to 0xa (64 bytes)
667 * ASF disabled so no need to do WA dev #4.30
669 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
671 /* Configure Tx MAC FIFO */
672 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
673 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
675 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
676 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
677 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
678 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
679 /* set Tx GMAC FIFO Almost Empty Threshold */
680 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
681 /* Disable Store & Forward mode for TX */
682 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
688 /* Assign Ram Buffer allocation.
689 * start and end are in units of 4k bytes
690 * ram registers are in units of 64bit words
692 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
696 start
= startk
* 4096/8;
697 end
= (endk
* 4096/8) - 1;
699 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
700 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
701 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
702 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
703 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
705 if (q
== Q_R1
|| q
== Q_R2
) {
706 u32 space
= (endk
- startk
) * 4096/8;
707 u32 tp
= space
- space
/4;
709 /* On receive queue's set the thresholds
710 * give receiver priority when > 3/4 full
711 * send pause when down to 2K
713 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
714 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
717 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
718 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
720 /* Enable store & forward on Tx queue's because
721 * Tx FIFO is only 1K on Yukon
723 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
726 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
727 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
730 /* Setup Bus Memory Interface */
731 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
733 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
734 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
735 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
736 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
739 /* Setup prefetch unit registers. This is the interface between
740 * hardware and driver list elements
742 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
745 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
746 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
747 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
748 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
749 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
750 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
752 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
755 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
757 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
759 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
763 /* Update chip's next pointer */
764 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
767 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
772 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
774 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
775 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
779 /* Return high part of DMA address (could be 32 or 64 bit) */
780 static inline u32
high32(dma_addr_t a
)
782 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
785 /* Build description to hardware about buffer */
786 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
788 struct sky2_rx_le
*le
;
789 u32 hi
= high32(map
);
790 u16 len
= sky2
->rx_bufsize
;
792 if (sky2
->rx_addr64
!= hi
) {
793 le
= sky2_next_rx(sky2
);
794 le
->addr
= cpu_to_le32(hi
);
796 le
->opcode
= OP_ADDR64
| HW_OWNER
;
797 sky2
->rx_addr64
= high32(map
+ len
);
800 le
= sky2_next_rx(sky2
);
801 le
->addr
= cpu_to_le32((u32
) map
);
802 le
->length
= cpu_to_le16(len
);
804 le
->opcode
= OP_PACKET
| HW_OWNER
;
808 /* Tell chip where to start receive checksum.
809 * Actually has two checksums, but set both same to avoid possible byte
812 static void rx_set_checksum(struct sky2_port
*sky2
)
814 struct sky2_rx_le
*le
;
816 le
= sky2_next_rx(sky2
);
817 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
819 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
821 sky2_write32(sky2
->hw
,
822 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
823 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
828 * The RX Stop command will not work for Yukon-2 if the BMU does not
829 * reach the end of packet and since we can't make sure that we have
830 * incoming data, we must reset the BMU while it is not doing a DMA
831 * transfer. Since it is possible that the RX path is still active,
832 * the RX RAM buffer will be stopped first, so any possible incoming
833 * data will not trigger a DMA. After the RAM buffer is stopped, the
834 * BMU is polled until any DMA in progress is ended and only then it
837 static void sky2_rx_stop(struct sky2_port
*sky2
)
839 struct sky2_hw
*hw
= sky2
->hw
;
840 unsigned rxq
= rxqaddr
[sky2
->port
];
843 /* disable the RAM Buffer receive queue */
844 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
846 for (i
= 0; i
< 0xffff; i
++)
847 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
848 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
851 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
854 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
856 /* reset the Rx prefetch unit */
857 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
860 /* Clean out receive buffer area, assumes receiver hardware stopped */
861 static void sky2_rx_clean(struct sky2_port
*sky2
)
865 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
866 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
867 struct ring_info
*re
= sky2
->rx_ring
+ i
;
870 pci_unmap_single(sky2
->hw
->pdev
,
871 re
->mapaddr
, sky2
->rx_bufsize
,
879 /* Basic MII support */
880 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
882 struct mii_ioctl_data
*data
= if_mii(ifr
);
883 struct sky2_port
*sky2
= netdev_priv(dev
);
884 struct sky2_hw
*hw
= sky2
->hw
;
885 int err
= -EOPNOTSUPP
;
887 if (!netif_running(dev
))
888 return -ENODEV
; /* Phy still in reset */
892 data
->phy_id
= PHY_ADDR_MARV
;
898 spin_lock_bh(&sky2
->phy_lock
);
899 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
900 spin_unlock_bh(&sky2
->phy_lock
);
907 if (!capable(CAP_NET_ADMIN
))
910 spin_lock_bh(&sky2
->phy_lock
);
911 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
913 spin_unlock_bh(&sky2
->phy_lock
);
919 #ifdef SKY2_VLAN_TAG_USED
920 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
922 struct sky2_port
*sky2
= netdev_priv(dev
);
923 struct sky2_hw
*hw
= sky2
->hw
;
924 u16 port
= sky2
->port
;
926 spin_lock_bh(&sky2
->tx_lock
);
928 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
929 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
932 spin_unlock_bh(&sky2
->tx_lock
);
935 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
937 struct sky2_port
*sky2
= netdev_priv(dev
);
938 struct sky2_hw
*hw
= sky2
->hw
;
939 u16 port
= sky2
->port
;
941 spin_lock_bh(&sky2
->tx_lock
);
943 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
944 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
946 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
948 spin_unlock_bh(&sky2
->tx_lock
);
953 * It appears the hardware has a bug in the FIFO logic that
954 * cause it to hang if the FIFO gets overrun and the receive buffer
955 * is not aligned. ALso alloc_skb() won't align properly if slab
956 * debugging is enabled.
958 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
962 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
964 unsigned long p
= (unsigned long) skb
->data
;
965 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
972 * Allocate and setup receiver buffer pool.
973 * In case of 64 bit dma, there are 2X as many list elements
974 * available as ring entries
975 * and need to reserve one list element so we don't wrap around.
977 static int sky2_rx_start(struct sky2_port
*sky2
)
979 struct sky2_hw
*hw
= sky2
->hw
;
980 unsigned rxq
= rxqaddr
[sky2
->port
];
983 sky2
->rx_put
= sky2
->rx_next
= 0;
986 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
987 /* MAC Rx RAM Read is controlled by hardware */
988 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
991 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
993 rx_set_checksum(sky2
);
994 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
995 struct ring_info
*re
= sky2
->rx_ring
+ i
;
997 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
1001 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1002 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1003 sky2_rx_add(sky2
, re
->mapaddr
);
1006 /* Truncate oversize frames */
1007 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), sky2
->rx_bufsize
- 8);
1008 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1010 /* Tell chip about available buffers */
1011 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1014 sky2_rx_clean(sky2
);
1018 /* Bring up network interface. */
1019 static int sky2_up(struct net_device
*dev
)
1021 struct sky2_port
*sky2
= netdev_priv(dev
);
1022 struct sky2_hw
*hw
= sky2
->hw
;
1023 unsigned port
= sky2
->port
;
1024 u32 ramsize
, rxspace
, imask
;
1025 int cap
, err
= -ENOMEM
;
1026 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1029 * On dual port PCI-X card, there is an problem where status
1030 * can be received out of order due to split transactions
1032 if (otherdev
&& netif_running(otherdev
) &&
1033 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1034 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1037 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1038 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1039 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1045 if (netif_msg_ifup(sky2
))
1046 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1048 /* must be power of 2 */
1049 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1051 sizeof(struct sky2_tx_le
),
1056 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1060 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1062 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1066 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1068 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1073 sky2_mac_init(hw
, port
);
1075 /* Determine available ram buffer space (in 4K blocks).
1076 * Note: not sure about the FE setting below yet
1078 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1081 ramsize
= sky2_read8(hw
, B2_E_0
);
1083 /* Give transmitter one third (rounded up) */
1084 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1086 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1087 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1089 /* Make sure SyncQ is disabled */
1090 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1093 sky2_qset(hw
, txqaddr
[port
]);
1095 /* Set almost empty threshold */
1096 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1097 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1099 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1102 err
= sky2_rx_start(sky2
);
1106 /* Enable interrupts from phy/mac for port */
1107 imask
= sky2_read32(hw
, B0_IMSK
);
1108 imask
|= portirq_msk
[port
];
1109 sky2_write32(hw
, B0_IMSK
, imask
);
1115 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1116 sky2
->rx_le
, sky2
->rx_le_map
);
1120 pci_free_consistent(hw
->pdev
,
1121 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1122 sky2
->tx_le
, sky2
->tx_le_map
);
1125 kfree(sky2
->tx_ring
);
1126 kfree(sky2
->rx_ring
);
1128 sky2
->tx_ring
= NULL
;
1129 sky2
->rx_ring
= NULL
;
1133 /* Modular subtraction in ring */
1134 static inline int tx_dist(unsigned tail
, unsigned head
)
1136 return (head
- tail
) & (TX_RING_SIZE
- 1);
1139 /* Number of list elements available for next tx */
1140 static inline int tx_avail(const struct sky2_port
*sky2
)
1142 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1145 /* Estimate of number of transmit list elements required */
1146 static unsigned tx_le_req(const struct sk_buff
*skb
)
1150 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1151 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1153 if (skb_shinfo(skb
)->tso_size
)
1156 if (skb
->ip_summed
== CHECKSUM_HW
)
1163 * Put one packet in ring for transmit.
1164 * A single packet can generate multiple list elements, and
1165 * the number of ring elements will probably be less than the number
1166 * of list elements used.
1168 * No BH disabling for tx_lock here (like tg3)
1170 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1172 struct sky2_port
*sky2
= netdev_priv(dev
);
1173 struct sky2_hw
*hw
= sky2
->hw
;
1174 struct sky2_tx_le
*le
= NULL
;
1175 struct tx_ring_info
*re
;
1183 /* No BH disabling for tx_lock here. We are running in BH disabled
1184 * context and TX reclaim runs via poll inside of a software
1185 * interrupt, and no related locks in IRQ processing.
1187 if (!spin_trylock(&sky2
->tx_lock
))
1188 return NETDEV_TX_LOCKED
;
1190 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1191 /* There is a known but harmless race with lockless tx
1192 * and netif_stop_queue.
1194 if (!netif_queue_stopped(dev
)) {
1195 netif_stop_queue(dev
);
1196 if (net_ratelimit())
1197 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1200 spin_unlock(&sky2
->tx_lock
);
1202 return NETDEV_TX_BUSY
;
1205 if (unlikely(netif_msg_tx_queued(sky2
)))
1206 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1207 dev
->name
, sky2
->tx_prod
, skb
->len
);
1209 len
= skb_headlen(skb
);
1210 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1211 addr64
= high32(mapping
);
1213 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1215 /* Send high bits if changed or crosses boundary */
1216 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1217 le
= get_tx_le(sky2
);
1218 le
->tx
.addr
= cpu_to_le32(addr64
);
1220 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1221 sky2
->tx_addr64
= high32(mapping
+ len
);
1224 /* Check for TCP Segmentation Offload */
1225 mss
= skb_shinfo(skb
)->tso_size
;
1227 /* just drop the packet if non-linear expansion fails */
1228 if (skb_header_cloned(skb
) &&
1229 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1234 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1235 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1239 if (mss
!= sky2
->tx_last_mss
) {
1240 le
= get_tx_le(sky2
);
1241 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1242 le
->tx
.tso
.rsvd
= 0;
1243 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1245 sky2
->tx_last_mss
= mss
;
1249 #ifdef SKY2_VLAN_TAG_USED
1250 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1251 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1253 le
= get_tx_le(sky2
);
1255 le
->opcode
= OP_VLAN
|HW_OWNER
;
1258 le
->opcode
|= OP_VLAN
;
1259 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1264 /* Handle TCP checksum offload */
1265 if (skb
->ip_summed
== CHECKSUM_HW
) {
1266 u16 hdr
= skb
->h
.raw
- skb
->data
;
1267 u16 offset
= hdr
+ skb
->csum
;
1269 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1270 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1273 le
= get_tx_le(sky2
);
1274 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1275 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1276 le
->length
= 0; /* initial checksum value */
1277 le
->ctrl
= 1; /* one packet */
1278 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1281 le
= get_tx_le(sky2
);
1282 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1283 le
->length
= cpu_to_le16(len
);
1285 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1287 /* Record the transmit mapping info */
1289 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1291 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1292 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1293 struct tx_ring_info
*fre
;
1295 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1296 frag
->size
, PCI_DMA_TODEVICE
);
1297 addr64
= high32(mapping
);
1298 if (addr64
!= sky2
->tx_addr64
) {
1299 le
= get_tx_le(sky2
);
1300 le
->tx
.addr
= cpu_to_le32(addr64
);
1302 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1303 sky2
->tx_addr64
= addr64
;
1306 le
= get_tx_le(sky2
);
1307 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1308 le
->length
= cpu_to_le16(frag
->size
);
1310 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1313 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1314 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1317 re
->idx
= sky2
->tx_prod
;
1320 avail
= tx_avail(sky2
);
1321 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1322 le
->ctrl
|= FRC_STAT
;
1323 if (avail
<= MAX_SKB_TX_LE
)
1324 netif_stop_queue(dev
);
1327 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1330 spin_unlock(&sky2
->tx_lock
);
1332 dev
->trans_start
= jiffies
;
1333 return NETDEV_TX_OK
;
1337 * Free ring elements from starting at tx_cons until "done"
1339 * NB: the hardware will tell us about partial completion of multi-part
1340 * buffers; these are deferred until completion.
1342 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1344 struct net_device
*dev
= sky2
->netdev
;
1345 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1349 BUG_ON(done
>= TX_RING_SIZE
);
1351 if (unlikely(netif_msg_tx_done(sky2
)))
1352 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1355 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1356 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1357 struct sk_buff
*skb
= re
->skb
;
1360 BUG_ON(nxt
>= TX_RING_SIZE
);
1361 prefetch(sky2
->tx_ring
+ nxt
);
1363 /* Check for partial status */
1364 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1368 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1369 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1371 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1372 struct tx_ring_info
*fre
;
1373 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1374 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1375 skb_shinfo(skb
)->frags
[i
].size
,
1382 sky2
->tx_cons
= put
;
1383 if (tx_avail(sky2
) > MAX_SKB_TX_LE
)
1384 netif_wake_queue(dev
);
1387 /* Cleanup all untransmitted buffers, assume transmitter not running */
1388 static void sky2_tx_clean(struct sky2_port
*sky2
)
1390 spin_lock_bh(&sky2
->tx_lock
);
1391 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1392 spin_unlock_bh(&sky2
->tx_lock
);
1395 /* Network shutdown */
1396 static int sky2_down(struct net_device
*dev
)
1398 struct sky2_port
*sky2
= netdev_priv(dev
);
1399 struct sky2_hw
*hw
= sky2
->hw
;
1400 unsigned port
= sky2
->port
;
1404 /* Never really got started! */
1408 if (netif_msg_ifdown(sky2
))
1409 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1411 /* Stop more packets from being queued */
1412 netif_stop_queue(dev
);
1414 sky2_phy_reset(hw
, port
);
1416 /* Stop transmitter */
1417 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1418 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1420 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1421 RB_RST_SET
| RB_DIS_OP_MD
);
1423 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1424 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1425 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1427 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1429 /* Workaround shared GMAC reset */
1430 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1431 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1432 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1434 /* Disable Force Sync bit and Enable Alloc bit */
1435 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1436 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1438 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1439 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1440 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1442 /* Reset the PCI FIFO of the async Tx queue */
1443 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1444 BMU_RST_SET
| BMU_FIFO_RST
);
1446 /* Reset the Tx prefetch units */
1447 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1450 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1454 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1455 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1457 /* Disable port IRQ */
1458 imask
= sky2_read32(hw
, B0_IMSK
);
1459 imask
&= ~portirq_msk
[port
];
1460 sky2_write32(hw
, B0_IMSK
, imask
);
1462 /* turn off LED's */
1463 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1465 synchronize_irq(hw
->pdev
->irq
);
1467 sky2_tx_clean(sky2
);
1468 sky2_rx_clean(sky2
);
1470 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1471 sky2
->rx_le
, sky2
->rx_le_map
);
1472 kfree(sky2
->rx_ring
);
1474 pci_free_consistent(hw
->pdev
,
1475 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1476 sky2
->tx_le
, sky2
->tx_le_map
);
1477 kfree(sky2
->tx_ring
);
1482 sky2
->rx_ring
= NULL
;
1483 sky2
->tx_ring
= NULL
;
1488 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1493 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1494 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1496 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1497 case PHY_M_PS_SPEED_1000
:
1499 case PHY_M_PS_SPEED_100
:
1506 static void sky2_link_up(struct sky2_port
*sky2
)
1508 struct sky2_hw
*hw
= sky2
->hw
;
1509 unsigned port
= sky2
->port
;
1512 /* Enable Transmit FIFO Underrun */
1513 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1515 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1516 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1517 reg
|= GM_GPCR_AU_ALL_DIS
;
1519 /* Is write/read necessary? Copied from sky2_mac_init */
1520 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1521 gma_read16(hw
, port
, GM_GP_CTRL
);
1523 switch (sky2
->speed
) {
1525 reg
&= ~GM_GPCR_SPEED_100
;
1526 reg
|= GM_GPCR_SPEED_1000
;
1529 reg
&= ~GM_GPCR_SPEED_1000
;
1530 reg
|= GM_GPCR_SPEED_100
;
1533 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1537 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1539 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1540 reg
|= GM_GPCR_DUP_FULL
;
1543 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1544 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1545 gma_read16(hw
, port
, GM_GP_CTRL
);
1547 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1549 netif_carrier_on(sky2
->netdev
);
1550 netif_wake_queue(sky2
->netdev
);
1552 /* Turn on link LED */
1553 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1554 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1556 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1557 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1558 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1560 switch(sky2
->speed
) {
1562 led
|= PHY_M_LEDC_INIT_CTRL(7);
1566 led
|= PHY_M_LEDC_STA1_CTRL(7);
1570 led
|= PHY_M_LEDC_STA0_CTRL(7);
1574 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1575 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1576 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1579 if (netif_msg_link(sky2
))
1580 printk(KERN_INFO PFX
1581 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1582 sky2
->netdev
->name
, sky2
->speed
,
1583 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1584 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1585 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1588 static void sky2_link_down(struct sky2_port
*sky2
)
1590 struct sky2_hw
*hw
= sky2
->hw
;
1591 unsigned port
= sky2
->port
;
1594 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1596 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1597 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1598 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1599 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1601 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1602 /* restore Asymmetric Pause bit */
1603 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1604 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1608 netif_carrier_off(sky2
->netdev
);
1609 netif_stop_queue(sky2
->netdev
);
1611 /* Turn on link LED */
1612 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1614 if (netif_msg_link(sky2
))
1615 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1616 sky2_phy_init(hw
, port
);
1619 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1621 struct sky2_hw
*hw
= sky2
->hw
;
1622 unsigned port
= sky2
->port
;
1625 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1627 if (lpa
& PHY_M_AN_RF
) {
1628 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1632 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1633 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1634 printk(KERN_ERR PFX
"%s: master/slave fault",
1635 sky2
->netdev
->name
);
1639 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1640 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1641 sky2
->netdev
->name
);
1645 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1647 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1649 /* Pause bits are offset (9..8) */
1650 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1653 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1654 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1656 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1657 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1658 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1660 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1665 /* Interrupt from PHY */
1666 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1668 struct net_device
*dev
= hw
->dev
[port
];
1669 struct sky2_port
*sky2
= netdev_priv(dev
);
1670 u16 istatus
, phystat
;
1672 spin_lock(&sky2
->phy_lock
);
1673 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1674 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1676 if (!netif_running(dev
))
1679 if (netif_msg_intr(sky2
))
1680 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1681 sky2
->netdev
->name
, istatus
, phystat
);
1683 if (istatus
& PHY_M_IS_AN_COMPL
) {
1684 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1689 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1690 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1692 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1694 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1696 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1697 if (phystat
& PHY_M_PS_LINK_UP
)
1700 sky2_link_down(sky2
);
1703 spin_unlock(&sky2
->phy_lock
);
1707 /* Transmit timeout is only called if we are running, carries is up
1708 * and tx queue is full (stopped).
1710 static void sky2_tx_timeout(struct net_device
*dev
)
1712 struct sky2_port
*sky2
= netdev_priv(dev
);
1713 struct sky2_hw
*hw
= sky2
->hw
;
1714 unsigned txq
= txqaddr
[sky2
->port
];
1717 if (netif_msg_timer(sky2
))
1718 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1720 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1721 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1723 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1725 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1727 if (report
!= done
) {
1728 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1730 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1731 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1732 } else if (report
!= sky2
->tx_cons
) {
1733 printk(KERN_INFO PFX
"status report lost?\n");
1735 spin_lock_bh(&sky2
->tx_lock
);
1736 sky2_tx_complete(sky2
, report
);
1737 spin_unlock_bh(&sky2
->tx_lock
);
1739 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1741 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1742 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1744 sky2_tx_clean(sky2
);
1747 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1752 /* Want receive buffer size to be multiple of 64 bits
1753 * and incl room for vlan and truncation
1755 static inline unsigned sky2_buf_size(int mtu
)
1757 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1760 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1762 struct sky2_port
*sky2
= netdev_priv(dev
);
1763 struct sky2_hw
*hw
= sky2
->hw
;
1768 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1771 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1774 if (!netif_running(dev
)) {
1779 imask
= sky2_read32(hw
, B0_IMSK
);
1780 sky2_write32(hw
, B0_IMSK
, 0);
1782 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1783 netif_stop_queue(dev
);
1784 netif_poll_disable(hw
->dev
[0]);
1786 synchronize_irq(hw
->pdev
->irq
);
1788 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1789 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1791 sky2_rx_clean(sky2
);
1794 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1795 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1796 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1798 if (dev
->mtu
> ETH_DATA_LEN
)
1799 mode
|= GM_SMOD_JUMBO_ENA
;
1801 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1803 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1805 err
= sky2_rx_start(sky2
);
1806 sky2_write32(hw
, B0_IMSK
, imask
);
1811 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1813 netif_poll_enable(hw
->dev
[0]);
1814 netif_wake_queue(dev
);
1821 * Receive one packet.
1822 * For small packets or errors, just reuse existing skb.
1823 * For larger packets, get new buffer.
1825 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1826 u16 length
, u32 status
)
1828 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1829 struct sk_buff
*skb
= NULL
;
1831 if (unlikely(netif_msg_rx_status(sky2
)))
1832 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1833 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1835 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1836 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1838 if (status
& GMR_FS_ANY_ERR
)
1841 if (!(status
& GMR_FS_RX_OK
))
1844 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1847 if (length
< copybreak
) {
1848 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1852 skb_reserve(skb
, 2);
1853 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1854 length
, PCI_DMA_FROMDEVICE
);
1855 memcpy(skb
->data
, re
->skb
->data
, length
);
1856 skb
->ip_summed
= re
->skb
->ip_summed
;
1857 skb
->csum
= re
->skb
->csum
;
1858 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1859 length
, PCI_DMA_FROMDEVICE
);
1861 struct sk_buff
*nskb
;
1863 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1869 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1870 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1871 prefetch(skb
->data
);
1873 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1874 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1877 skb_put(skb
, length
);
1879 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1880 sky2_rx_add(sky2
, re
->mapaddr
);
1882 /* Tell receiver about new buffers. */
1883 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
);
1888 ++sky2
->net_stats
.rx_over_errors
;
1892 ++sky2
->net_stats
.rx_errors
;
1894 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1895 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1896 sky2
->netdev
->name
, status
, length
);
1898 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1899 sky2
->net_stats
.rx_length_errors
++;
1900 if (status
& GMR_FS_FRAGMENT
)
1901 sky2
->net_stats
.rx_frame_errors
++;
1902 if (status
& GMR_FS_CRC_ERR
)
1903 sky2
->net_stats
.rx_crc_errors
++;
1904 if (status
& GMR_FS_RX_FF_OV
)
1905 sky2
->net_stats
.rx_fifo_errors
++;
1910 /* Transmit complete */
1911 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1913 struct sky2_port
*sky2
= netdev_priv(dev
);
1915 if (netif_running(dev
)) {
1916 spin_lock(&sky2
->tx_lock
);
1917 sky2_tx_complete(sky2
, last
);
1918 spin_unlock(&sky2
->tx_lock
);
1922 /* Process status response ring */
1923 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1926 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1930 while (hw
->st_idx
!= hwidx
) {
1931 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1932 struct net_device
*dev
;
1933 struct sky2_port
*sky2
;
1934 struct sk_buff
*skb
;
1938 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1940 BUG_ON(le
->link
>= 2);
1941 dev
= hw
->dev
[le
->link
];
1943 sky2
= netdev_priv(dev
);
1944 length
= le
->length
;
1945 status
= le
->status
;
1947 switch (le
->opcode
& ~HW_OWNER
) {
1949 skb
= sky2_receive(sky2
, length
, status
);
1954 skb
->protocol
= eth_type_trans(skb
, dev
);
1955 dev
->last_rx
= jiffies
;
1957 #ifdef SKY2_VLAN_TAG_USED
1958 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1959 vlan_hwaccel_receive_skb(skb
,
1961 be16_to_cpu(sky2
->rx_tag
));
1964 netif_receive_skb(skb
);
1966 if (++work_done
>= to_do
)
1970 #ifdef SKY2_VLAN_TAG_USED
1972 sky2
->rx_tag
= length
;
1976 sky2
->rx_tag
= length
;
1980 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1981 skb
->ip_summed
= CHECKSUM_HW
;
1982 skb
->csum
= le16_to_cpu(status
);
1986 /* TX index reports status for both ports */
1987 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
1988 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
1990 sky2_tx_done(hw
->dev
[1],
1991 ((status
>> 24) & 0xff)
1992 | (u16
)(length
& 0xf) << 8);
1996 if (net_ratelimit())
1997 printk(KERN_WARNING PFX
1998 "unknown status opcode 0x%x\n", le
->opcode
);
2007 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2009 struct net_device
*dev
= hw
->dev
[port
];
2011 if (net_ratelimit())
2012 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2015 if (status
& Y2_IS_PAR_RD1
) {
2016 if (net_ratelimit())
2017 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2020 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2023 if (status
& Y2_IS_PAR_WR1
) {
2024 if (net_ratelimit())
2025 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2028 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2031 if (status
& Y2_IS_PAR_MAC1
) {
2032 if (net_ratelimit())
2033 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2034 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2037 if (status
& Y2_IS_PAR_RX1
) {
2038 if (net_ratelimit())
2039 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2040 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2043 if (status
& Y2_IS_TCP_TXA1
) {
2044 if (net_ratelimit())
2045 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2047 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2051 static void sky2_hw_intr(struct sky2_hw
*hw
)
2053 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2055 if (status
& Y2_IS_TIST_OV
)
2056 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2058 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2061 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2062 if (net_ratelimit())
2063 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2064 pci_name(hw
->pdev
), pci_err
);
2066 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2067 sky2_pci_write16(hw
, PCI_STATUS
,
2068 pci_err
| PCI_STATUS_ERROR_BITS
);
2069 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2072 if (status
& Y2_IS_PCI_EXP
) {
2073 /* PCI-Express uncorrectable Error occurred */
2076 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2078 if (net_ratelimit())
2079 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2080 pci_name(hw
->pdev
), pex_err
);
2082 /* clear the interrupt */
2083 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2084 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2086 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2088 if (pex_err
& PEX_FATAL_ERRORS
) {
2089 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2090 hwmsk
&= ~Y2_IS_PCI_EXP
;
2091 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2095 if (status
& Y2_HWE_L1_MASK
)
2096 sky2_hw_error(hw
, 0, status
);
2098 if (status
& Y2_HWE_L1_MASK
)
2099 sky2_hw_error(hw
, 1, status
);
2102 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2104 struct net_device
*dev
= hw
->dev
[port
];
2105 struct sky2_port
*sky2
= netdev_priv(dev
);
2106 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2108 if (netif_msg_intr(sky2
))
2109 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2112 if (status
& GM_IS_RX_FF_OR
) {
2113 ++sky2
->net_stats
.rx_fifo_errors
;
2114 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2117 if (status
& GM_IS_TX_FF_UR
) {
2118 ++sky2
->net_stats
.tx_fifo_errors
;
2119 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2123 /* This should never happen it is a fatal situation */
2124 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2125 const char *rxtx
, u32 mask
)
2127 struct net_device
*dev
= hw
->dev
[port
];
2128 struct sky2_port
*sky2
= netdev_priv(dev
);
2131 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2132 dev
? dev
->name
: "<not registered>", rxtx
);
2134 imask
= sky2_read32(hw
, B0_IMSK
);
2136 sky2_write32(hw
, B0_IMSK
, imask
);
2139 spin_lock(&sky2
->phy_lock
);
2140 sky2_link_down(sky2
);
2141 spin_unlock(&sky2
->phy_lock
);
2145 /* If idle then force a fake soft NAPI poll once a second
2146 * to work around cases where sharing an edge triggered interrupt.
2148 static void sky2_idle(unsigned long arg
)
2150 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2151 struct net_device
*dev
= hw
->dev
[0];
2153 if (__netif_rx_schedule_prep(dev
))
2154 __netif_rx_schedule(dev
);
2156 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2160 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2162 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2163 int work_limit
= min(dev0
->quota
, *budget
);
2165 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2167 if (status
& Y2_IS_HW_ERR
)
2170 if (status
& Y2_IS_IRQ_PHY1
)
2171 sky2_phy_intr(hw
, 0);
2173 if (status
& Y2_IS_IRQ_PHY2
)
2174 sky2_phy_intr(hw
, 1);
2176 if (status
& Y2_IS_IRQ_MAC1
)
2177 sky2_mac_intr(hw
, 0);
2179 if (status
& Y2_IS_IRQ_MAC2
)
2180 sky2_mac_intr(hw
, 1);
2182 if (status
& Y2_IS_CHK_RX1
)
2183 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2185 if (status
& Y2_IS_CHK_RX2
)
2186 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2188 if (status
& Y2_IS_CHK_TXA1
)
2189 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2191 if (status
& Y2_IS_CHK_TXA2
)
2192 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2194 if (status
& Y2_IS_STAT_BMU
)
2195 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2197 work_done
= sky2_status_intr(hw
, work_limit
);
2198 *budget
-= work_done
;
2199 dev0
->quota
-= work_done
;
2201 if (work_done
>= work_limit
)
2204 netif_rx_complete(dev0
);
2206 status
= sky2_read32(hw
, B0_Y2_SP_LISR
);
2210 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2212 struct sky2_hw
*hw
= dev_id
;
2213 struct net_device
*dev0
= hw
->dev
[0];
2216 /* Reading this mask interrupts as side effect */
2217 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2218 if (status
== 0 || status
== ~0)
2221 prefetch(&hw
->st_le
[hw
->st_idx
]);
2222 if (likely(__netif_rx_schedule_prep(dev0
)))
2223 __netif_rx_schedule(dev0
);
2228 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 static void sky2_netpoll(struct net_device
*dev
)
2231 struct sky2_port
*sky2
= netdev_priv(dev
);
2233 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2237 /* Chip internal frequency for clock calculations */
2238 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2240 switch (hw
->chip_id
) {
2241 case CHIP_ID_YUKON_EC
:
2242 case CHIP_ID_YUKON_EC_U
:
2243 return 125; /* 125 Mhz */
2244 case CHIP_ID_YUKON_FE
:
2245 return 100; /* 100 Mhz */
2246 default: /* YUKON_XL */
2247 return 156; /* 156 Mhz */
2251 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2253 return sky2_mhz(hw
) * us
;
2256 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2258 return clk
/ sky2_mhz(hw
);
2262 static int __devinit
sky2_reset(struct sky2_hw
*hw
)
2268 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2270 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2271 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2272 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2273 pci_name(hw
->pdev
), hw
->chip_id
);
2277 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2279 /* This rev is really old, and requires untested workarounds */
2280 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2281 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2282 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2283 hw
->chip_id
, hw
->chip_rev
);
2288 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2289 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2290 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2294 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2295 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2297 /* clear PCI errors, if any */
2298 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2300 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2301 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2304 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2306 /* clear any PEX errors */
2307 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2308 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2311 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2312 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2315 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2316 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2317 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2321 sky2_set_power_state(hw
, PCI_D0
);
2323 for (i
= 0; i
< hw
->ports
; i
++) {
2324 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2325 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2328 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2330 /* Clear I2C IRQ noise */
2331 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2333 /* turn off hardware timer (unused) */
2334 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2335 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2337 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2339 /* Turn off descriptor polling */
2340 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2342 /* Turn off receive timestamp */
2343 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2344 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2346 /* enable the Tx Arbiters */
2347 for (i
= 0; i
< hw
->ports
; i
++)
2348 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2350 /* Initialize ram interface */
2351 for (i
= 0; i
< hw
->ports
; i
++) {
2352 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2354 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2355 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2356 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2357 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2358 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2359 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2360 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2361 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2362 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2363 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2364 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2365 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2368 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2370 for (i
= 0; i
< hw
->ports
; i
++)
2371 sky2_phy_reset(hw
, i
);
2373 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2376 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2377 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2379 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2380 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2382 /* Set the list last index */
2383 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2385 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2386 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2388 /* set Status-FIFO ISR watermark */
2389 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2390 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2392 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2394 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2395 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2396 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2398 /* enable status unit */
2399 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2401 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2402 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2403 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2408 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2412 modes
= SUPPORTED_10baseT_Half
2413 | SUPPORTED_10baseT_Full
2414 | SUPPORTED_100baseT_Half
2415 | SUPPORTED_100baseT_Full
2416 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2418 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2419 modes
|= SUPPORTED_1000baseT_Half
2420 | SUPPORTED_1000baseT_Full
;
2422 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2423 | SUPPORTED_Autoneg
;
2427 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2429 struct sky2_port
*sky2
= netdev_priv(dev
);
2430 struct sky2_hw
*hw
= sky2
->hw
;
2432 ecmd
->transceiver
= XCVR_INTERNAL
;
2433 ecmd
->supported
= sky2_supported_modes(hw
);
2434 ecmd
->phy_address
= PHY_ADDR_MARV
;
2436 ecmd
->supported
= SUPPORTED_10baseT_Half
2437 | SUPPORTED_10baseT_Full
2438 | SUPPORTED_100baseT_Half
2439 | SUPPORTED_100baseT_Full
2440 | SUPPORTED_1000baseT_Half
2441 | SUPPORTED_1000baseT_Full
2442 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2443 ecmd
->port
= PORT_TP
;
2445 ecmd
->port
= PORT_FIBRE
;
2447 ecmd
->advertising
= sky2
->advertising
;
2448 ecmd
->autoneg
= sky2
->autoneg
;
2449 ecmd
->speed
= sky2
->speed
;
2450 ecmd
->duplex
= sky2
->duplex
;
2454 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2456 struct sky2_port
*sky2
= netdev_priv(dev
);
2457 const struct sky2_hw
*hw
= sky2
->hw
;
2458 u32 supported
= sky2_supported_modes(hw
);
2460 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2461 ecmd
->advertising
= supported
;
2467 switch (ecmd
->speed
) {
2469 if (ecmd
->duplex
== DUPLEX_FULL
)
2470 setting
= SUPPORTED_1000baseT_Full
;
2471 else if (ecmd
->duplex
== DUPLEX_HALF
)
2472 setting
= SUPPORTED_1000baseT_Half
;
2477 if (ecmd
->duplex
== DUPLEX_FULL
)
2478 setting
= SUPPORTED_100baseT_Full
;
2479 else if (ecmd
->duplex
== DUPLEX_HALF
)
2480 setting
= SUPPORTED_100baseT_Half
;
2486 if (ecmd
->duplex
== DUPLEX_FULL
)
2487 setting
= SUPPORTED_10baseT_Full
;
2488 else if (ecmd
->duplex
== DUPLEX_HALF
)
2489 setting
= SUPPORTED_10baseT_Half
;
2497 if ((setting
& supported
) == 0)
2500 sky2
->speed
= ecmd
->speed
;
2501 sky2
->duplex
= ecmd
->duplex
;
2504 sky2
->autoneg
= ecmd
->autoneg
;
2505 sky2
->advertising
= ecmd
->advertising
;
2507 if (netif_running(dev
))
2508 sky2_phy_reinit(sky2
);
2513 static void sky2_get_drvinfo(struct net_device
*dev
,
2514 struct ethtool_drvinfo
*info
)
2516 struct sky2_port
*sky2
= netdev_priv(dev
);
2518 strcpy(info
->driver
, DRV_NAME
);
2519 strcpy(info
->version
, DRV_VERSION
);
2520 strcpy(info
->fw_version
, "N/A");
2521 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2524 static const struct sky2_stat
{
2525 char name
[ETH_GSTRING_LEN
];
2528 { "tx_bytes", GM_TXO_OK_HI
},
2529 { "rx_bytes", GM_RXO_OK_HI
},
2530 { "tx_broadcast", GM_TXF_BC_OK
},
2531 { "rx_broadcast", GM_RXF_BC_OK
},
2532 { "tx_multicast", GM_TXF_MC_OK
},
2533 { "rx_multicast", GM_RXF_MC_OK
},
2534 { "tx_unicast", GM_TXF_UC_OK
},
2535 { "rx_unicast", GM_RXF_UC_OK
},
2536 { "tx_mac_pause", GM_TXF_MPAUSE
},
2537 { "rx_mac_pause", GM_RXF_MPAUSE
},
2538 { "collisions", GM_TXF_COL
},
2539 { "late_collision",GM_TXF_LAT_COL
},
2540 { "aborted", GM_TXF_ABO_COL
},
2541 { "single_collisions", GM_TXF_SNG_COL
},
2542 { "multi_collisions", GM_TXF_MUL_COL
},
2544 { "rx_short", GM_RXF_SHT
},
2545 { "rx_runt", GM_RXE_FRAG
},
2546 { "rx_64_byte_packets", GM_RXF_64B
},
2547 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2548 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2549 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2550 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2551 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2552 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2553 { "rx_too_long", GM_RXF_LNG_ERR
},
2554 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2555 { "rx_jabber", GM_RXF_JAB_PKT
},
2556 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2558 { "tx_64_byte_packets", GM_TXF_64B
},
2559 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2560 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2561 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2562 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2563 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2564 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2565 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2568 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2570 struct sky2_port
*sky2
= netdev_priv(dev
);
2572 return sky2
->rx_csum
;
2575 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2577 struct sky2_port
*sky2
= netdev_priv(dev
);
2579 sky2
->rx_csum
= data
;
2581 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2582 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2587 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2589 struct sky2_port
*sky2
= netdev_priv(netdev
);
2590 return sky2
->msg_enable
;
2593 static int sky2_nway_reset(struct net_device
*dev
)
2595 struct sky2_port
*sky2
= netdev_priv(dev
);
2597 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2600 sky2_phy_reinit(sky2
);
2605 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2607 struct sky2_hw
*hw
= sky2
->hw
;
2608 unsigned port
= sky2
->port
;
2611 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2612 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2613 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2614 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2616 for (i
= 2; i
< count
; i
++)
2617 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2620 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2622 struct sky2_port
*sky2
= netdev_priv(netdev
);
2623 sky2
->msg_enable
= value
;
2626 static int sky2_get_stats_count(struct net_device
*dev
)
2628 return ARRAY_SIZE(sky2_stats
);
2631 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2632 struct ethtool_stats
*stats
, u64
* data
)
2634 struct sky2_port
*sky2
= netdev_priv(dev
);
2636 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2639 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2643 switch (stringset
) {
2645 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2646 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2647 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2652 /* Use hardware MIB variables for critical path statistics and
2653 * transmit feedback not reported at interrupt.
2654 * Other errors are accounted for in interrupt handler.
2656 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2658 struct sky2_port
*sky2
= netdev_priv(dev
);
2661 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2663 sky2
->net_stats
.tx_bytes
= data
[0];
2664 sky2
->net_stats
.rx_bytes
= data
[1];
2665 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2666 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2667 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2668 sky2
->net_stats
.collisions
= data
[10];
2669 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2671 return &sky2
->net_stats
;
2674 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2676 struct sky2_port
*sky2
= netdev_priv(dev
);
2677 struct sky2_hw
*hw
= sky2
->hw
;
2678 unsigned port
= sky2
->port
;
2679 const struct sockaddr
*addr
= p
;
2681 if (!is_valid_ether_addr(addr
->sa_data
))
2682 return -EADDRNOTAVAIL
;
2684 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2685 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2686 dev
->dev_addr
, ETH_ALEN
);
2687 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2688 dev
->dev_addr
, ETH_ALEN
);
2690 /* virtual address for data */
2691 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2693 /* physical address: used for pause frames */
2694 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2699 static void sky2_set_multicast(struct net_device
*dev
)
2701 struct sky2_port
*sky2
= netdev_priv(dev
);
2702 struct sky2_hw
*hw
= sky2
->hw
;
2703 unsigned port
= sky2
->port
;
2704 struct dev_mc_list
*list
= dev
->mc_list
;
2708 memset(filter
, 0, sizeof(filter
));
2710 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2711 reg
|= GM_RXCR_UCF_ENA
;
2713 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2714 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2715 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2716 memset(filter
, 0xff, sizeof(filter
));
2717 else if (dev
->mc_count
== 0) /* no multicast */
2718 reg
&= ~GM_RXCR_MCF_ENA
;
2721 reg
|= GM_RXCR_MCF_ENA
;
2723 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2724 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2725 filter
[bit
/ 8] |= 1 << (bit
% 8);
2729 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2730 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2731 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2732 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2733 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2734 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2735 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2736 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2738 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2741 /* Can have one global because blinking is controlled by
2742 * ethtool and that is always under RTNL mutex
2744 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2748 switch (hw
->chip_id
) {
2749 case CHIP_ID_YUKON_XL
:
2750 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2751 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2752 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2753 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2754 PHY_M_LEDC_INIT_CTRL(7) |
2755 PHY_M_LEDC_STA1_CTRL(7) |
2756 PHY_M_LEDC_STA0_CTRL(7))
2759 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2763 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2764 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2765 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2766 PHY_M_LED_MO_10(MO_LED_ON
) |
2767 PHY_M_LED_MO_100(MO_LED_ON
) |
2768 PHY_M_LED_MO_1000(MO_LED_ON
) |
2769 PHY_M_LED_MO_RX(MO_LED_ON
)
2770 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2771 PHY_M_LED_MO_10(MO_LED_OFF
) |
2772 PHY_M_LED_MO_100(MO_LED_OFF
) |
2773 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2774 PHY_M_LED_MO_RX(MO_LED_OFF
));
2779 /* blink LED's for finding board */
2780 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2782 struct sky2_port
*sky2
= netdev_priv(dev
);
2783 struct sky2_hw
*hw
= sky2
->hw
;
2784 unsigned port
= sky2
->port
;
2785 u16 ledctrl
, ledover
= 0;
2790 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2791 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2795 /* save initial values */
2796 spin_lock_bh(&sky2
->phy_lock
);
2797 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2798 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2799 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2800 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2801 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2803 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2804 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2808 while (!interrupted
&& ms
> 0) {
2809 sky2_led(hw
, port
, onoff
);
2812 spin_unlock_bh(&sky2
->phy_lock
);
2813 interrupted
= msleep_interruptible(250);
2814 spin_lock_bh(&sky2
->phy_lock
);
2819 /* resume regularly scheduled programming */
2820 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2821 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2822 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2823 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2824 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2826 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2827 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2829 spin_unlock_bh(&sky2
->phy_lock
);
2834 static void sky2_get_pauseparam(struct net_device
*dev
,
2835 struct ethtool_pauseparam
*ecmd
)
2837 struct sky2_port
*sky2
= netdev_priv(dev
);
2839 ecmd
->tx_pause
= sky2
->tx_pause
;
2840 ecmd
->rx_pause
= sky2
->rx_pause
;
2841 ecmd
->autoneg
= sky2
->autoneg
;
2844 static int sky2_set_pauseparam(struct net_device
*dev
,
2845 struct ethtool_pauseparam
*ecmd
)
2847 struct sky2_port
*sky2
= netdev_priv(dev
);
2850 sky2
->autoneg
= ecmd
->autoneg
;
2851 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2852 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2854 sky2_phy_reinit(sky2
);
2859 static int sky2_get_coalesce(struct net_device
*dev
,
2860 struct ethtool_coalesce
*ecmd
)
2862 struct sky2_port
*sky2
= netdev_priv(dev
);
2863 struct sky2_hw
*hw
= sky2
->hw
;
2865 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2866 ecmd
->tx_coalesce_usecs
= 0;
2868 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2869 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2871 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2873 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2874 ecmd
->rx_coalesce_usecs
= 0;
2876 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2877 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2879 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2881 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2882 ecmd
->rx_coalesce_usecs_irq
= 0;
2884 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2885 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2888 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2893 /* Note: this affect both ports */
2894 static int sky2_set_coalesce(struct net_device
*dev
,
2895 struct ethtool_coalesce
*ecmd
)
2897 struct sky2_port
*sky2
= netdev_priv(dev
);
2898 struct sky2_hw
*hw
= sky2
->hw
;
2899 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2901 if (ecmd
->tx_coalesce_usecs
> tmax
||
2902 ecmd
->rx_coalesce_usecs
> tmax
||
2903 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2906 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2908 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2910 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2913 if (ecmd
->tx_coalesce_usecs
== 0)
2914 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2916 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2917 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2918 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2920 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2922 if (ecmd
->rx_coalesce_usecs
== 0)
2923 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2925 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2926 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2927 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2929 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2931 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2932 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2934 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2935 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2936 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2938 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2942 static void sky2_get_ringparam(struct net_device
*dev
,
2943 struct ethtool_ringparam
*ering
)
2945 struct sky2_port
*sky2
= netdev_priv(dev
);
2947 ering
->rx_max_pending
= RX_MAX_PENDING
;
2948 ering
->rx_mini_max_pending
= 0;
2949 ering
->rx_jumbo_max_pending
= 0;
2950 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2952 ering
->rx_pending
= sky2
->rx_pending
;
2953 ering
->rx_mini_pending
= 0;
2954 ering
->rx_jumbo_pending
= 0;
2955 ering
->tx_pending
= sky2
->tx_pending
;
2958 static int sky2_set_ringparam(struct net_device
*dev
,
2959 struct ethtool_ringparam
*ering
)
2961 struct sky2_port
*sky2
= netdev_priv(dev
);
2964 if (ering
->rx_pending
> RX_MAX_PENDING
||
2965 ering
->rx_pending
< 8 ||
2966 ering
->tx_pending
< MAX_SKB_TX_LE
||
2967 ering
->tx_pending
> TX_RING_SIZE
- 1)
2970 if (netif_running(dev
))
2973 sky2
->rx_pending
= ering
->rx_pending
;
2974 sky2
->tx_pending
= ering
->tx_pending
;
2976 if (netif_running(dev
)) {
2981 sky2_set_multicast(dev
);
2987 static int sky2_get_regs_len(struct net_device
*dev
)
2993 * Returns copy of control register region
2994 * Note: access to the RAM address register set will cause timeouts.
2996 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2999 const struct sky2_port
*sky2
= netdev_priv(dev
);
3000 const void __iomem
*io
= sky2
->hw
->regs
;
3002 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3004 memset(p
, 0, regs
->len
);
3006 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3008 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3010 regs
->len
- B3_RI_WTO_R1
);
3013 static struct ethtool_ops sky2_ethtool_ops
= {
3014 .get_settings
= sky2_get_settings
,
3015 .set_settings
= sky2_set_settings
,
3016 .get_drvinfo
= sky2_get_drvinfo
,
3017 .get_msglevel
= sky2_get_msglevel
,
3018 .set_msglevel
= sky2_set_msglevel
,
3019 .nway_reset
= sky2_nway_reset
,
3020 .get_regs_len
= sky2_get_regs_len
,
3021 .get_regs
= sky2_get_regs
,
3022 .get_link
= ethtool_op_get_link
,
3023 .get_sg
= ethtool_op_get_sg
,
3024 .set_sg
= ethtool_op_set_sg
,
3025 .get_tx_csum
= ethtool_op_get_tx_csum
,
3026 .set_tx_csum
= ethtool_op_set_tx_csum
,
3027 .get_tso
= ethtool_op_get_tso
,
3028 .set_tso
= ethtool_op_set_tso
,
3029 .get_rx_csum
= sky2_get_rx_csum
,
3030 .set_rx_csum
= sky2_set_rx_csum
,
3031 .get_strings
= sky2_get_strings
,
3032 .get_coalesce
= sky2_get_coalesce
,
3033 .set_coalesce
= sky2_set_coalesce
,
3034 .get_ringparam
= sky2_get_ringparam
,
3035 .set_ringparam
= sky2_set_ringparam
,
3036 .get_pauseparam
= sky2_get_pauseparam
,
3037 .set_pauseparam
= sky2_set_pauseparam
,
3038 .phys_id
= sky2_phys_id
,
3039 .get_stats_count
= sky2_get_stats_count
,
3040 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3041 .get_perm_addr
= ethtool_op_get_perm_addr
,
3044 /* Initialize network device */
3045 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3046 unsigned port
, int highmem
)
3048 struct sky2_port
*sky2
;
3049 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3052 printk(KERN_ERR
"sky2 etherdev alloc failed");
3056 SET_MODULE_OWNER(dev
);
3057 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3058 dev
->irq
= hw
->pdev
->irq
;
3059 dev
->open
= sky2_up
;
3060 dev
->stop
= sky2_down
;
3061 dev
->do_ioctl
= sky2_ioctl
;
3062 dev
->hard_start_xmit
= sky2_xmit_frame
;
3063 dev
->get_stats
= sky2_get_stats
;
3064 dev
->set_multicast_list
= sky2_set_multicast
;
3065 dev
->set_mac_address
= sky2_set_mac_address
;
3066 dev
->change_mtu
= sky2_change_mtu
;
3067 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3068 dev
->tx_timeout
= sky2_tx_timeout
;
3069 dev
->watchdog_timeo
= TX_WATCHDOG
;
3071 dev
->poll
= sky2_poll
;
3072 dev
->weight
= NAPI_WEIGHT
;
3073 #ifdef CONFIG_NET_POLL_CONTROLLER
3074 dev
->poll_controller
= sky2_netpoll
;
3077 sky2
= netdev_priv(dev
);
3080 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3082 spin_lock_init(&sky2
->tx_lock
);
3083 /* Auto speed and flow control */
3084 sky2
->autoneg
= AUTONEG_ENABLE
;
3089 sky2
->advertising
= sky2_supported_modes(hw
);
3092 spin_lock_init(&sky2
->phy_lock
);
3093 sky2
->tx_pending
= TX_DEF_PENDING
;
3094 sky2
->rx_pending
= RX_DEF_PENDING
;
3095 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3097 hw
->dev
[port
] = dev
;
3101 dev
->features
|= NETIF_F_LLTX
;
3102 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3103 dev
->features
|= NETIF_F_TSO
;
3105 dev
->features
|= NETIF_F_HIGHDMA
;
3106 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3108 #ifdef SKY2_VLAN_TAG_USED
3109 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3110 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3111 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3114 /* read the mac address */
3115 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3116 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3118 /* device is off until link detection */
3119 netif_carrier_off(dev
);
3120 netif_stop_queue(dev
);
3125 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3127 const struct sky2_port
*sky2
= netdev_priv(dev
);
3129 if (netif_msg_probe(sky2
))
3130 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3132 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3133 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3136 /* Handle software interrupt used during MSI test */
3137 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3138 struct pt_regs
*regs
)
3140 struct sky2_hw
*hw
= dev_id
;
3141 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3146 if (status
& Y2_IS_IRQ_SW
) {
3147 hw
->msi_detected
= 1;
3148 wake_up(&hw
->msi_wait
);
3149 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3151 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3156 /* Test interrupt path by forcing a a software IRQ */
3157 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3159 struct pci_dev
*pdev
= hw
->pdev
;
3162 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3164 err
= request_irq(pdev
->irq
, sky2_test_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3166 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3167 pci_name(pdev
), pdev
->irq
);
3171 init_waitqueue_head (&hw
->msi_wait
);
3173 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3176 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3178 if (!hw
->msi_detected
) {
3179 /* MSI test failed, go back to INTx mode */
3180 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3181 "switching to INTx mode. Please report this failure to "
3182 "the PCI maintainer and include system chipset information.\n",
3186 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3189 sky2_write32(hw
, B0_IMSK
, 0);
3191 free_irq(pdev
->irq
, hw
);
3196 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3197 const struct pci_device_id
*ent
)
3199 struct net_device
*dev
, *dev1
= NULL
;
3201 int err
, pm_cap
, using_dac
= 0;
3203 err
= pci_enable_device(pdev
);
3205 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3210 err
= pci_request_regions(pdev
, DRV_NAME
);
3212 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3217 pci_set_master(pdev
);
3219 /* Find power-management capability. */
3220 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3222 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3225 goto err_out_free_regions
;
3228 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3229 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3231 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3233 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3234 "for consistent allocations\n", pci_name(pdev
));
3235 goto err_out_free_regions
;
3239 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3241 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3243 goto err_out_free_regions
;
3248 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3250 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3252 goto err_out_free_regions
;
3257 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3259 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3261 goto err_out_free_hw
;
3263 hw
->pm_cap
= pm_cap
;
3266 /* byte swap descriptors in hardware */
3270 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3271 reg
|= PCI_REV_DESC
;
3272 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3276 /* ring for status responses */
3277 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3280 goto err_out_iounmap
;
3282 err
= sky2_reset(hw
);
3284 goto err_out_iounmap
;
3286 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3287 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3288 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3289 hw
->chip_id
, hw
->chip_rev
);
3291 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3293 goto err_out_free_pci
;
3295 err
= register_netdev(dev
);
3297 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3299 goto err_out_free_netdev
;
3302 sky2_show_addr(dev
);
3304 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3305 if (register_netdev(dev1
) == 0)
3306 sky2_show_addr(dev1
);
3308 /* Failure to register second port need not be fatal */
3309 printk(KERN_WARNING PFX
3310 "register of second port failed\n");
3316 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3317 err
= sky2_test_msi(hw
);
3318 if (err
== -EOPNOTSUPP
)
3319 pci_disable_msi(pdev
);
3321 goto err_out_unregister
;
3324 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3326 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3327 pci_name(pdev
), pdev
->irq
);
3328 goto err_out_unregister
;
3331 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3333 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3334 if (idle_timeout
> 0)
3335 mod_timer(&hw
->idle_timer
,
3336 jiffies
+ msecs_to_jiffies(idle_timeout
));
3338 pci_set_drvdata(pdev
, hw
);
3343 pci_disable_msi(pdev
);
3345 unregister_netdev(dev1
);
3348 unregister_netdev(dev
);
3349 err_out_free_netdev
:
3352 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3353 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3358 err_out_free_regions
:
3359 pci_release_regions(pdev
);
3360 pci_disable_device(pdev
);
3365 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3367 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3368 struct net_device
*dev0
, *dev1
;
3373 del_timer_sync(&hw
->idle_timer
);
3375 sky2_write32(hw
, B0_IMSK
, 0);
3376 synchronize_irq(hw
->pdev
->irq
);
3381 unregister_netdev(dev1
);
3382 unregister_netdev(dev0
);
3384 sky2_set_power_state(hw
, PCI_D3hot
);
3385 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3386 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3387 sky2_read8(hw
, B0_CTST
);
3389 free_irq(pdev
->irq
, hw
);
3390 pci_disable_msi(pdev
);
3391 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3392 pci_release_regions(pdev
);
3393 pci_disable_device(pdev
);
3401 pci_set_drvdata(pdev
, NULL
);
3405 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3407 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3410 for (i
= 0; i
< 2; i
++) {
3411 struct net_device
*dev
= hw
->dev
[i
];
3414 if (!netif_running(dev
))
3418 netif_device_detach(dev
);
3422 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3425 static int sky2_resume(struct pci_dev
*pdev
)
3427 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3430 pci_restore_state(pdev
);
3431 pci_enable_wake(pdev
, PCI_D0
, 0);
3432 err
= sky2_set_power_state(hw
, PCI_D0
);
3436 err
= sky2_reset(hw
);
3440 for (i
= 0; i
< 2; i
++) {
3441 struct net_device
*dev
= hw
->dev
[i
];
3442 if (dev
&& netif_running(dev
)) {
3443 netif_device_attach(dev
);
3446 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3458 static struct pci_driver sky2_driver
= {
3460 .id_table
= sky2_id_table
,
3461 .probe
= sky2_probe
,
3462 .remove
= __devexit_p(sky2_remove
),
3464 .suspend
= sky2_suspend
,
3465 .resume
= sky2_resume
,
3469 static int __init
sky2_init_module(void)
3471 return pci_register_driver(&sky2_driver
);
3474 static void __exit
sky2_cleanup_module(void)
3476 pci_unregister_driver(&sky2_driver
);
3479 module_init(sky2_init_module
);
3480 module_exit(sky2_cleanup_module
);
3482 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3483 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3484 MODULE_LICENSE("GPL");
3485 MODULE_VERSION(DRV_VERSION
);