2 * linux/drivers/ide/arm/icside.c
4 * Copyright (c) 1996-2004 Russell King.
6 * Please note that this platform does not support 32-bit IDE IO.
9 #include <linux/string.h>
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/slab.h>
13 #include <linux/blkdev.h>
14 #include <linux/errno.h>
15 #include <linux/hdreg.h>
16 #include <linux/ide.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/scatterlist.h>
24 #include <asm/ecard.h>
26 #define ICS_IDENT_OFFSET 0x2280
28 #define ICS_ARCIN_V5_INTRSTAT 0x0000
29 #define ICS_ARCIN_V5_INTROFFSET 0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING 6
34 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING 6
45 unsigned int dataoffset
;
46 unsigned int ctrloffset
;
47 unsigned int stepping
;
50 static struct cardinfo icside_cardinfo_v5
= {
51 .dataoffset
= ICS_ARCIN_V5_IDEOFFSET
,
52 .ctrloffset
= ICS_ARCIN_V5_IDEALTOFFSET
,
53 .stepping
= ICS_ARCIN_V5_IDESTEPPING
,
56 static struct cardinfo icside_cardinfo_v6_1
= {
57 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_1
,
58 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_1
,
59 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
62 static struct cardinfo icside_cardinfo_v6_2
= {
63 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_2
,
64 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_2
,
65 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
71 void __iomem
*irq_port
;
72 void __iomem
*ioc_base
;
74 /* parent device... until the IDE core gets one of its own */
79 #define ICS_TYPE_A3IN 0
80 #define ICS_TYPE_A3USER 1
82 #define ICS_TYPE_V5 15
83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
85 /* ---------------- Version 5 PCB Support Functions --------------------- */
86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
87 * Purpose : enable interrupts from card
89 static void icside_irqenable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
91 struct icside_state
*state
= ec
->irq_data
;
93 writeb(0, state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
97 * Purpose : disable interrupts from card
99 static void icside_irqdisable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
101 struct icside_state
*state
= ec
->irq_data
;
103 readb(state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
106 static const expansioncard_ops_t icside_ops_arcin_v5
= {
107 .irqenable
= icside_irqenable_arcin_v5
,
108 .irqdisable
= icside_irqdisable_arcin_v5
,
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114 * Purpose : enable interrupts from card
116 static void icside_irqenable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
118 struct icside_state
*state
= ec
->irq_data
;
119 void __iomem
*base
= state
->irq_port
;
123 switch (state
->channel
) {
125 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_1
);
126 readb(base
+ ICS_ARCIN_V6_INTROFFSET_2
);
129 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_2
);
130 readb(base
+ ICS_ARCIN_V6_INTROFFSET_1
);
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136 * Purpose : disable interrupts from card
138 static void icside_irqdisable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
140 struct icside_state
*state
= ec
->irq_data
;
144 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
145 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149 * Purpose : detect an active interrupt from card
151 static int icside_irqpending_arcin_v6(struct expansion_card
*ec
)
153 struct icside_state
*state
= ec
->irq_data
;
155 return readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_1
) & 1 ||
156 readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_2
) & 1;
159 static const expansioncard_ops_t icside_ops_arcin_v6
= {
160 .irqenable
= icside_irqenable_arcin_v6
,
161 .irqdisable
= icside_irqdisable_arcin_v6
,
162 .irqpending
= icside_irqpending_arcin_v6
,
166 * Handle routing of interrupts. This is called before
167 * we write the command to the drive.
169 static void icside_maskproc(ide_drive_t
*drive
, int mask
)
171 ide_hwif_t
*hwif
= HWIF(drive
);
172 struct icside_state
*state
= hwif
->hwif_data
;
175 local_irq_save(flags
);
177 state
->channel
= hwif
->channel
;
179 if (state
->enabled
&& !mask
) {
180 switch (hwif
->channel
) {
182 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
183 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
186 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
187 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
191 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
192 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
195 local_irq_restore(flags
);
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
202 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
203 * There is only one DMA controller per card, which means that only
204 * one drive can be accessed at one time. NOTE! We do not enforce that
205 * here, but we rely on the main IDE driver spotting that both
206 * interfaces use the same IRQ, which should guarantee this.
209 static void icside_build_sglist(ide_drive_t
*drive
, struct request
*rq
)
211 ide_hwif_t
*hwif
= drive
->hwif
;
212 struct icside_state
*state
= hwif
->hwif_data
;
213 struct scatterlist
*sg
= hwif
->sg_table
;
215 ide_map_sg(drive
, rq
);
217 if (rq_data_dir(rq
) == READ
)
218 hwif
->sg_dma_direction
= DMA_FROM_DEVICE
;
220 hwif
->sg_dma_direction
= DMA_TO_DEVICE
;
222 hwif
->sg_nents
= dma_map_sg(state
->dev
, sg
, hwif
->sg_nents
,
223 hwif
->sg_dma_direction
);
227 * Configure the IOMD to give the appropriate timings for the transfer
228 * mode being requested. We take the advice of the ATA standards, and
229 * calculate the cycle time based on the transfer mode, and the EIDE
230 * MW DMA specs that the drive provides in the IDENTIFY command.
232 * We have the following IOMD DMA modes to choose from:
234 * Type Active Recovery Cycle
235 * A 250 (250) 312 (550) 562 (800)
237 * C 125 (125) 125 (375) 250 (500)
240 * (figures in brackets are actual measured timings)
242 * However, we also need to take care of the read/write active and
246 * Mode Active -- Recovery -- Cycle IOMD type
247 * MW0 215 50 215 480 A
251 static void icside_set_dma_mode(ide_drive_t
*drive
, const u8 xfer_mode
)
253 int cycle_time
, use_dma_info
= 0;
280 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
281 * take care to note the values in the ID...
283 if (use_dma_info
&& drive
->id
->eide_dma_time
> cycle_time
)
284 cycle_time
= drive
->id
->eide_dma_time
;
286 drive
->drive_data
= cycle_time
;
288 printk("%s: %s selected (peak %dMB/s)\n", drive
->name
,
289 ide_xfer_verbose(xfer_mode
), 2000 / drive
->drive_data
);
292 static void icside_dma_host_off(ide_drive_t
*drive
)
296 static void icside_dma_off_quietly(ide_drive_t
*drive
)
298 drive
->using_dma
= 0;
301 static void icside_dma_host_on(ide_drive_t
*drive
)
305 static int icside_dma_on(ide_drive_t
*drive
)
307 drive
->using_dma
= 1;
312 static int icside_dma_end(ide_drive_t
*drive
)
314 ide_hwif_t
*hwif
= HWIF(drive
);
315 struct icside_state
*state
= hwif
->hwif_data
;
317 drive
->waiting_for_dma
= 0;
319 disable_dma(state
->dev
->dma
);
321 /* Teardown mappings after DMA has completed. */
322 dma_unmap_sg(state
->dev
, hwif
->sg_table
, hwif
->sg_nents
,
323 hwif
->sg_dma_direction
);
325 return get_dma_residue(state
->dev
->dma
) != 0;
328 static void icside_dma_start(ide_drive_t
*drive
)
330 ide_hwif_t
*hwif
= HWIF(drive
);
331 struct icside_state
*state
= hwif
->hwif_data
;
333 /* We can not enable DMA on both channels simultaneously. */
334 BUG_ON(dma_channel_active(state
->dev
->dma
));
335 enable_dma(state
->dev
->dma
);
338 static int icside_dma_setup(ide_drive_t
*drive
)
340 ide_hwif_t
*hwif
= HWIF(drive
);
341 struct icside_state
*state
= hwif
->hwif_data
;
342 struct request
*rq
= hwif
->hwgroup
->rq
;
343 unsigned int dma_mode
;
346 dma_mode
= DMA_MODE_WRITE
;
348 dma_mode
= DMA_MODE_READ
;
351 * We can not enable DMA on both channels.
353 BUG_ON(dma_channel_active(state
->dev
->dma
));
355 icside_build_sglist(drive
, rq
);
358 * Ensure that we have the right interrupt routed.
360 icside_maskproc(drive
, 0);
363 * Route the DMA signals to the correct interface.
365 writeb(hwif
->select_data
, hwif
->config_data
);
368 * Select the correct timing for this drive.
370 set_dma_speed(state
->dev
->dma
, drive
->drive_data
);
373 * Tell the DMA engine about the SG table and
376 set_dma_sg(state
->dev
->dma
, hwif
->sg_table
, hwif
->sg_nents
);
377 set_dma_mode(state
->dev
->dma
, dma_mode
);
379 drive
->waiting_for_dma
= 1;
384 static void icside_dma_exec_cmd(ide_drive_t
*drive
, u8 cmd
)
386 /* issue cmd to drive */
387 ide_execute_command(drive
, cmd
, ide_dma_intr
, 2 * WAIT_CMD
, NULL
);
390 static int icside_dma_test_irq(ide_drive_t
*drive
)
392 ide_hwif_t
*hwif
= HWIF(drive
);
393 struct icside_state
*state
= hwif
->hwif_data
;
395 return readb(state
->irq_port
+
397 ICS_ARCIN_V6_INTRSTAT_2
:
398 ICS_ARCIN_V6_INTRSTAT_1
)) & 1;
401 static void icside_dma_timeout(ide_drive_t
*drive
)
403 printk(KERN_ERR
"%s: DMA timeout occurred: ", drive
->name
);
405 if (icside_dma_test_irq(drive
))
408 ide_dump_status(drive
, "DMA timeout", HWIF(drive
)->INB(IDE_STATUS_REG
));
410 icside_dma_end(drive
);
413 static void icside_dma_lost_irq(ide_drive_t
*drive
)
415 printk(KERN_ERR
"%s: IRQ lost\n", drive
->name
);
418 static void icside_dma_init(ide_hwif_t
*hwif
)
420 hwif
->mwdma_mask
= 7; /* MW0..2 */
421 hwif
->swdma_mask
= 7; /* SW0..2 */
423 hwif
->dmatable_cpu
= NULL
;
424 hwif
->dmatable_dma
= 0;
425 hwif
->set_dma_mode
= icside_set_dma_mode
;
427 hwif
->dma_host_off
= icside_dma_host_off
;
428 hwif
->dma_off_quietly
= icside_dma_off_quietly
;
429 hwif
->dma_host_on
= icside_dma_host_on
;
430 hwif
->ide_dma_on
= icside_dma_on
;
431 hwif
->dma_setup
= icside_dma_setup
;
432 hwif
->dma_exec_cmd
= icside_dma_exec_cmd
;
433 hwif
->dma_start
= icside_dma_start
;
434 hwif
->ide_dma_end
= icside_dma_end
;
435 hwif
->ide_dma_test_irq
= icside_dma_test_irq
;
436 hwif
->dma_timeout
= icside_dma_timeout
;
437 hwif
->dma_lost_irq
= icside_dma_lost_irq
;
440 #define icside_dma_init(hwif) (0)
444 icside_setup(void __iomem
*base
, struct cardinfo
*info
, struct expansion_card
*ec
)
446 unsigned long port
= (unsigned long)base
+ info
->dataoffset
;
449 hwif
= ide_find_port(port
);
453 memset(&hwif
->hw
, 0, sizeof(hw_regs_t
));
456 * Ensure we're using MMIO
458 default_hwif_mmiops(hwif
);
461 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; i
++) {
462 hwif
->hw
.io_ports
[i
] = port
;
463 hwif
->io_ports
[i
] = port
;
464 port
+= 1 << info
->stepping
;
466 hwif
->hw
.io_ports
[IDE_CONTROL_OFFSET
] = (unsigned long)base
+ info
->ctrloffset
;
467 hwif
->io_ports
[IDE_CONTROL_OFFSET
] = (unsigned long)base
+ info
->ctrloffset
;
468 hwif
->hw
.irq
= ec
->irq
;
471 hwif
->chipset
= ide_acorn
;
472 hwif
->gendev
.parent
= &ec
->dev
;
479 icside_register_v5(struct icside_state
*state
, struct expansion_card
*ec
)
483 u8 idx
[4] = { 0xff, 0xff, 0xff, 0xff };
485 base
= ecardm_iomap(ec
, ECARD_RES_MEMC
, 0, 0);
489 state
->irq_port
= base
;
491 ec
->irqaddr
= base
+ ICS_ARCIN_V5_INTRSTAT
;
494 ecard_setirq(ec
, &icside_ops_arcin_v5
, state
);
497 * Be on the safe side - disable interrupts
499 icside_irqdisable_arcin_v5(ec
, 0);
501 hwif
= icside_setup(base
, &icside_cardinfo_v5
, ec
);
505 state
->hwif
[0] = hwif
;
507 idx
[0] = hwif
->index
;
515 icside_register_v6(struct icside_state
*state
, struct expansion_card
*ec
)
517 ide_hwif_t
*hwif
, *mate
;
518 void __iomem
*ioc_base
, *easi_base
;
519 unsigned int sel
= 0;
521 u8 idx
[4] = { 0xff, 0xff, 0xff, 0xff };
523 ioc_base
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
529 easi_base
= ioc_base
;
531 if (ecard_resource_flags(ec
, ECARD_RES_EASI
)) {
532 easi_base
= ecardm_iomap(ec
, ECARD_RES_EASI
, 0, 0);
539 * Enable access to the EASI region.
544 writeb(sel
, ioc_base
);
546 ecard_setirq(ec
, &icside_ops_arcin_v6
, state
);
548 state
->irq_port
= easi_base
;
549 state
->ioc_base
= ioc_base
;
552 * Be on the safe side - disable interrupts
554 icside_irqdisable_arcin_v6(ec
, 0);
557 * Find and register the interfaces.
559 hwif
= icside_setup(easi_base
, &icside_cardinfo_v6_1
, ec
);
560 mate
= icside_setup(easi_base
, &icside_cardinfo_v6_2
, ec
);
562 if (!hwif
|| !mate
) {
567 state
->hwif
[0] = hwif
;
568 state
->hwif
[1] = mate
;
570 hwif
->maskproc
= icside_maskproc
;
572 hwif
->hwif_data
= state
;
574 hwif
->serialized
= 1;
575 hwif
->config_data
= (unsigned long)ioc_base
;
576 hwif
->select_data
= sel
;
578 mate
->maskproc
= icside_maskproc
;
580 mate
->hwif_data
= state
;
582 mate
->serialized
= 1;
583 mate
->config_data
= (unsigned long)ioc_base
;
584 mate
->select_data
= sel
| 1;
586 if (ec
->dma
!= NO_DMA
&& !request_dma(ec
->dma
, hwif
->name
)) {
587 icside_dma_init(hwif
);
588 icside_dma_init(mate
);
591 idx
[0] = hwif
->index
;
592 idx
[1] = mate
->index
;
603 icside_probe(struct expansion_card
*ec
, const struct ecard_id
*id
)
605 struct icside_state
*state
;
609 ret
= ecard_request_resources(ec
);
613 state
= kzalloc(sizeof(struct icside_state
), GFP_KERNEL
);
619 state
->type
= ICS_TYPE_NOTYPE
;
620 state
->dev
= &ec
->dev
;
622 idmem
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
626 type
= readb(idmem
+ ICS_IDENT_OFFSET
) & 1;
627 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 4) & 1) << 1;
628 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 8) & 1) << 2;
629 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 12) & 1) << 3;
630 ecardm_iounmap(ec
, idmem
);
635 switch (state
->type
) {
637 dev_warn(&ec
->dev
, "A3IN unsupported\n");
641 case ICS_TYPE_A3USER
:
642 dev_warn(&ec
->dev
, "A3USER unsupported\n");
647 ret
= icside_register_v5(state
, ec
);
651 ret
= icside_register_v6(state
, ec
);
655 dev_warn(&ec
->dev
, "unknown interface type\n");
661 ecard_set_drvdata(ec
, state
);
667 ecard_release_resources(ec
);
672 static void __devexit
icside_remove(struct expansion_card
*ec
)
674 struct icside_state
*state
= ecard_get_drvdata(ec
);
676 switch (state
->type
) {
678 /* FIXME: tell IDE to stop using the interface */
680 /* Disable interrupts */
681 icside_irqdisable_arcin_v5(ec
, 0);
685 /* FIXME: tell IDE to stop using the interface */
686 if (ec
->dma
!= NO_DMA
)
689 /* Disable interrupts */
690 icside_irqdisable_arcin_v6(ec
, 0);
692 /* Reset the ROM pointer/EASI selection */
693 writeb(0, state
->ioc_base
);
697 ecard_set_drvdata(ec
, NULL
);
700 ecard_release_resources(ec
);
703 static void icside_shutdown(struct expansion_card
*ec
)
705 struct icside_state
*state
= ecard_get_drvdata(ec
);
709 * Disable interrupts from this card. We need to do
710 * this before disabling EASI since we may be accessing
711 * this register via that region.
713 local_irq_save(flags
);
714 ec
->ops
->irqdisable(ec
, 0);
715 local_irq_restore(flags
);
718 * Reset the ROM pointer so that we can read the ROM
719 * after a soft reboot. This also disables access to
720 * the IDE taskfile via the EASI region.
723 writeb(0, state
->ioc_base
);
726 static const struct ecard_id icside_ids
[] = {
727 { MANU_ICS
, PROD_ICS_IDE
},
728 { MANU_ICS2
, PROD_ICS2_IDE
},
732 static struct ecard_driver icside_driver
= {
733 .probe
= icside_probe
,
734 .remove
= __devexit_p(icside_remove
),
735 .shutdown
= icside_shutdown
,
736 .id_table
= icside_ids
,
742 static int __init
icside_init(void)
744 return ecard_register_driver(&icside_driver
);
747 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
748 MODULE_LICENSE("GPL");
749 MODULE_DESCRIPTION("ICS IDE driver");
751 module_init(icside_init
);