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[PATCH] w1: Fix for kconfig entry typo
[linux-2.6/verdex.git] / drivers / net / r8169.c
blobf83b41d4cb0e64f8374b55b894bf916171b8a479
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30 VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37 VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45 VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
63 #include <linux/in.h>
64 #include <linux/ip.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
68
69 #include <asm/io.h>
70 #include <asm/irq.h>
71
72 #ifdef CONFIG_R8169_NAPI
73 #define NAPI_SUFFIX "-NAPI"
74 #else
75 #define NAPI_SUFFIX ""
76 #endif
77
78 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
79 #define MODULENAME "r8169"
80 #define PFX MODULENAME ": "
81
82 #ifdef RTL8169_DEBUG
83 #define assert(expr) \
84 if (!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89 #else
90 #define assert(expr) do {} while (0)
91 #define dprintk(fmt, args...) do {} while (0)
92 #endif /* RTL8169_DEBUG */
93
94 #define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
96
97 #define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100 #ifdef CONFIG_R8169_NAPI
101 #define rtl8169_rx_skb netif_receive_skb
102 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
103 #define rtl8169_rx_quota(count, quota) min(count, quota)
104 #else
105 #define rtl8169_rx_skb netif_rx
106 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
107 #define rtl8169_rx_quota(count, quota) count
108 #endif
109
110 /* media options */
111 #define MAX_UNITS 8
112 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113 static int num_media = 0;
114
115 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116 static const int max_interrupt_work = 20;
117
118 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120 static const int multicast_filter_limit = 32;
121
122 /* MAC address length */
123 #define MAC_ADDR_LEN 6
124
125 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133 #define R8169_REGS_SIZE 256
134 #define R8169_NAPI_WEIGHT 64
135 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
138 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141 #define RTL8169_TX_TIMEOUT (6*HZ)
142 #define RTL8169_PHY_TIMEOUT (10*HZ)
143
144 /* write/read MMIO register */
145 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148 #define RTL_R8(reg) readb (ioaddr + (reg))
149 #define RTL_R16(reg) readw (ioaddr + (reg))
150 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152 enum mac_version {
153 RTL_GIGA_MAC_VER_01 = 0x00,
154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_11 = 0x0b,
159 RTL_GIGA_MAC_VER_12 = 0x0c,
160 RTL_GIGA_MAC_VER_13 = 0x0d,
161 RTL_GIGA_MAC_VER_14 = 0x0e,
162 RTL_GIGA_MAC_VER_15 = 0x0f
163 };
164
165 enum phy_version {
166 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
167 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
168 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
170 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
171 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
172 };
173
174 #define _R(NAME,MAC,MASK) \
175 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
176
177 static const struct {
178 const char *name;
179 u8 mac_version;
180 u32 RxConfigMask; /* Clears the bits supported by this chip */
181 } rtl_chip_info[] = {
182 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
183 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
185 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
187 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
190 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
191 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
192 };
193 #undef _R
194
195 enum cfg_version {
196 RTL_CFG_0 = 0x00,
197 RTL_CFG_1,
198 RTL_CFG_2
199 };
200
201 static const struct {
202 unsigned int region;
203 unsigned int align;
204 } rtl_cfg_info[] = {
205 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
206 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
207 [RTL_CFG_2] = { 2, 8 }
208 };
209
210 static struct pci_device_id rtl8169_pci_tbl[] = {
211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
216 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
218 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
219 { PCI_VENDOR_ID_LINKSYS, 0x1032,
220 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
221 {0,},
222 };
223
224 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226 static int rx_copybreak = 200;
227 static int use_dac;
228 static int ignore_parity_err;
229 static struct {
230 u32 msg_enable;
231 } debug = { -1 };
232
233 enum RTL8169_registers {
234 MAC0 = 0, /* Ethernet hardware address. */
235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3C,
247 IntrStatus = 0x3E,
248 TxConfig = 0x40,
249 RxConfig = 0x44,
250 RxMissed = 0x4C,
251 Cfg9346 = 0x50,
252 Config0 = 0x51,
253 Config1 = 0x52,
254 Config2 = 0x53,
255 Config3 = 0x54,
256 Config4 = 0x55,
257 Config5 = 0x56,
258 MultiIntr = 0x5C,
259 PHYAR = 0x60,
260 TBICSR = 0x64,
261 TBI_ANAR = 0x68,
262 TBI_LPAR = 0x6A,
263 PHYstatus = 0x6C,
264 RxMaxSize = 0xDA,
265 CPlusCmd = 0xE0,
266 IntrMitigate = 0xE2,
267 RxDescAddrLow = 0xE4,
268 RxDescAddrHigh = 0xE8,
269 EarlyTxThres = 0xEC,
270 FuncEvent = 0xF0,
271 FuncEventMask = 0xF4,
272 FuncPresetState = 0xF8,
273 FuncForceEvent = 0xFC,
274 };
275
276 enum RTL8169_register_content {
277 /* InterruptStatusBits */
278 SYSErr = 0x8000,
279 PCSTimeout = 0x4000,
280 SWInt = 0x0100,
281 TxDescUnavail = 0x80,
282 RxFIFOOver = 0x40,
283 LinkChg = 0x20,
284 RxOverflow = 0x10,
285 TxErr = 0x08,
286 TxOK = 0x04,
287 RxErr = 0x02,
288 RxOK = 0x01,
289
290 /* RxStatusDesc */
291 RxFOVF = (1 << 23),
292 RxRWT = (1 << 22),
293 RxRES = (1 << 21),
294 RxRUNT = (1 << 20),
295 RxCRC = (1 << 19),
296
297 /* ChipCmdBits */
298 CmdReset = 0x10,
299 CmdRxEnb = 0x08,
300 CmdTxEnb = 0x04,
301 RxBufEmpty = 0x01,
302
303 /* Cfg9346Bits */
304 Cfg9346_Lock = 0x00,
305 Cfg9346_Unlock = 0xC0,
306
307 /* rx_mode_bits */
308 AcceptErr = 0x20,
309 AcceptRunt = 0x10,
310 AcceptBroadcast = 0x08,
311 AcceptMulticast = 0x04,
312 AcceptMyPhys = 0x02,
313 AcceptAllPhys = 0x01,
314
315 /* RxConfigBits */
316 RxCfgFIFOShift = 13,
317 RxCfgDMAShift = 8,
318
319 /* TxConfigBits */
320 TxInterFrameGapShift = 24,
321 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
322
323 /* Config1 register p.24 */
324 PMEnable = (1 << 0), /* Power Management Enable */
325
326 /* Config3 register p.25 */
327 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
328 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
329
330 /* Config5 register p.27 */
331 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
332 MWF = (1 << 5), /* Accept Multicast wakeup frame */
333 UWF = (1 << 4), /* Accept Unicast wakeup frame */
334 LanWake = (1 << 1), /* LanWake enable/disable */
335 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
336
337 /* TBICSR p.28 */
338 TBIReset = 0x80000000,
339 TBILoopback = 0x40000000,
340 TBINwEnable = 0x20000000,
341 TBINwRestart = 0x10000000,
342 TBILinkOk = 0x02000000,
343 TBINwComplete = 0x01000000,
344
345 /* CPlusCmd p.31 */
346 RxVlan = (1 << 6),
347 RxChkSum = (1 << 5),
348 PCIDAC = (1 << 4),
349 PCIMulRW = (1 << 3),
350
351 /* rtl8169_PHYstatus */
352 TBI_Enable = 0x80,
353 TxFlowCtrl = 0x40,
354 RxFlowCtrl = 0x20,
355 _1000bpsF = 0x10,
356 _100bps = 0x08,
357 _10bps = 0x04,
358 LinkStatus = 0x02,
359 FullDup = 0x01,
360
361 /* _MediaType */
362 _10_Half = 0x01,
363 _10_Full = 0x02,
364 _100_Half = 0x04,
365 _100_Full = 0x08,
366 _1000_Full = 0x10,
367
368 /* _TBICSRBit */
369 TBILinkOK = 0x02000000,
370
371 /* DumpCounterCommand */
372 CounterDump = 0x8,
373 };
374
375 enum _DescStatusBit {
376 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
377 RingEnd = (1 << 30), /* End of descriptor ring */
378 FirstFrag = (1 << 29), /* First segment of a packet */
379 LastFrag = (1 << 28), /* Final segment of a packet */
380
381 /* Tx private */
382 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
383 MSSShift = 16, /* MSS value position */
384 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
385 IPCS = (1 << 18), /* Calculate IP checksum */
386 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
387 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
388 TxVlanTag = (1 << 17), /* Add VLAN tag */
389
390 /* Rx private */
391 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
392 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
393
394 #define RxProtoUDP (PID1)
395 #define RxProtoTCP (PID0)
396 #define RxProtoIP (PID1 | PID0)
397 #define RxProtoMask RxProtoIP
398
399 IPFail = (1 << 16), /* IP checksum failed */
400 UDPFail = (1 << 15), /* UDP/IP checksum failed */
401 TCPFail = (1 << 14), /* TCP/IP checksum failed */
402 RxVlanTag = (1 << 16), /* VLAN tag available */
403 };
404
405 #define RsvdMask 0x3fffc000
406
407 struct TxDesc {
408 u32 opts1;
409 u32 opts2;
410 u64 addr;
411 };
412
413 struct RxDesc {
414 u32 opts1;
415 u32 opts2;
416 u64 addr;
417 };
418
419 struct ring_info {
420 struct sk_buff *skb;
421 u32 len;
422 u8 __pad[sizeof(void *) - sizeof(u32)];
423 };
424
425 struct rtl8169_private {
426 void __iomem *mmio_addr; /* memory map physical address */
427 struct pci_dev *pci_dev; /* Index of PCI device */
428 struct net_device *dev;
429 struct net_device_stats stats; /* statistics of net device */
430 spinlock_t lock; /* spin lock flag */
431 u32 msg_enable;
432 int chipset;
433 int mac_version;
434 int phy_version;
435 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
437 u32 dirty_rx;
438 u32 dirty_tx;
439 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
440 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr;
442 dma_addr_t RxPhyAddr;
443 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
445 unsigned align;
446 unsigned rx_buf_sz;
447 struct timer_list timer;
448 u16 cp_cmd;
449 u16 intr_mask;
450 int phy_auto_nego_reg;
451 int phy_1000_ctrl_reg;
452 #ifdef CONFIG_R8169_VLAN
453 struct vlan_group *vlgrp;
454 #endif
455 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
456 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
457 void (*phy_reset_enable)(void __iomem *);
458 unsigned int (*phy_reset_pending)(void __iomem *);
459 unsigned int (*link_ok)(void __iomem *);
460 struct delayed_work task;
461 unsigned wol_enabled : 1;
462 };
463
464 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
465 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
466 module_param_array(media, int, &num_media, 0);
467 MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
468 module_param(rx_copybreak, int, 0);
469 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
470 module_param(use_dac, int, 0);
471 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
472 module_param_named(debug, debug.msg_enable, int, 0);
473 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
474 module_param_named(ignore_parity_err, ignore_parity_err, bool, 0);
475 MODULE_PARM_DESC(ignore_parity_err, "Ignore PCI parity error as target. Default: false");
476 MODULE_LICENSE("GPL");
477 MODULE_VERSION(RTL8169_VERSION);
478
479 static int rtl8169_open(struct net_device *dev);
480 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
481 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
482 static int rtl8169_init_ring(struct net_device *dev);
483 static void rtl8169_hw_start(struct net_device *dev);
484 static int rtl8169_close(struct net_device *dev);
485 static void rtl8169_set_rx_mode(struct net_device *dev);
486 static void rtl8169_tx_timeout(struct net_device *dev);
487 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
488 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
489 void __iomem *);
490 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
491 static void rtl8169_down(struct net_device *dev);
492
493 #ifdef CONFIG_R8169_NAPI
494 static int rtl8169_poll(struct net_device *dev, int *budget);
495 #endif
496
497 static const u16 rtl8169_intr_mask =
498 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
499 static const u16 rtl8169_napi_event =
500 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
501 static const unsigned int rtl8169_rx_config =
502 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
503
504 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
505 {
506 int i;
507
508 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
509
510 for (i = 20; i > 0; i--) {
511 /* Check if the RTL8169 has completed writing to the specified MII register */
512 if (!(RTL_R32(PHYAR) & 0x80000000))
513 break;
514 udelay(25);
515 }
516 }
517
518 static int mdio_read(void __iomem *ioaddr, int RegAddr)
519 {
520 int i, value = -1;
521
522 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
523
524 for (i = 20; i > 0; i--) {
525 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
526 if (RTL_R32(PHYAR) & 0x80000000) {
527 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
528 break;
529 }
530 udelay(25);
531 }
532 return value;
533 }
534
535 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
536 {
537 RTL_W16(IntrMask, 0x0000);
538
539 RTL_W16(IntrStatus, 0xffff);
540 }
541
542 static void rtl8169_asic_down(void __iomem *ioaddr)
543 {
544 RTL_W8(ChipCmd, 0x00);
545 rtl8169_irq_mask_and_ack(ioaddr);
546 RTL_R16(CPlusCmd);
547 }
548
549 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
550 {
551 return RTL_R32(TBICSR) & TBIReset;
552 }
553
554 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
555 {
556 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
557 }
558
559 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
560 {
561 return RTL_R32(TBICSR) & TBILinkOk;
562 }
563
564 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
565 {
566 return RTL_R8(PHYstatus) & LinkStatus;
567 }
568
569 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
570 {
571 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
572 }
573
574 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
575 {
576 unsigned int val;
577
578 mdio_write(ioaddr, MII_BMCR, BMCR_RESET);
579 val = mdio_read(ioaddr, MII_BMCR);
580 }
581
582 static void rtl8169_check_link_status(struct net_device *dev,
583 struct rtl8169_private *tp, void __iomem *ioaddr)
584 {
585 unsigned long flags;
586
587 spin_lock_irqsave(&tp->lock, flags);
588 if (tp->link_ok(ioaddr)) {
589 netif_carrier_on(dev);
590 if (netif_msg_ifup(tp))
591 printk(KERN_INFO PFX "%s: link up\n", dev->name);
592 } else {
593 if (netif_msg_ifdown(tp))
594 printk(KERN_INFO PFX "%s: link down\n", dev->name);
595 netif_carrier_off(dev);
596 }
597 spin_unlock_irqrestore(&tp->lock, flags);
598 }
599
600 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
601 {
602 struct {
603 u16 speed;
604 u8 duplex;
605 u8 autoneg;
606 u8 media;
607 } link_settings[] = {
608 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
609 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
610 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
611 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
612 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
613 /* Make TBI happy */
614 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
615 }, *p;
616 unsigned char option;
617
618 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
619
620 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
621 printk(KERN_WARNING PFX "media option is deprecated.\n");
622
623 for (p = link_settings; p->media != 0xff; p++) {
624 if (p->media == option)
625 break;
626 }
627 *autoneg = p->autoneg;
628 *speed = p->speed;
629 *duplex = p->duplex;
630 }
631
632 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
633 {
634 struct rtl8169_private *tp = netdev_priv(dev);
635 void __iomem *ioaddr = tp->mmio_addr;
636 u8 options;
637
638 wol->wolopts = 0;
639
640 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
641 wol->supported = WAKE_ANY;
642
643 spin_lock_irq(&tp->lock);
644
645 options = RTL_R8(Config1);
646 if (!(options & PMEnable))
647 goto out_unlock;
648
649 options = RTL_R8(Config3);
650 if (options & LinkUp)
651 wol->wolopts |= WAKE_PHY;
652 if (options & MagicPacket)
653 wol->wolopts |= WAKE_MAGIC;
654
655 options = RTL_R8(Config5);
656 if (options & UWF)
657 wol->wolopts |= WAKE_UCAST;
658 if (options & BWF)
659 wol->wolopts |= WAKE_BCAST;
660 if (options & MWF)
661 wol->wolopts |= WAKE_MCAST;
662
663 out_unlock:
664 spin_unlock_irq(&tp->lock);
665 }
666
667 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
668 {
669 struct rtl8169_private *tp = netdev_priv(dev);
670 void __iomem *ioaddr = tp->mmio_addr;
671 int i;
672 static struct {
673 u32 opt;
674 u16 reg;
675 u8 mask;
676 } cfg[] = {
677 { WAKE_ANY, Config1, PMEnable },
678 { WAKE_PHY, Config3, LinkUp },
679 { WAKE_MAGIC, Config3, MagicPacket },
680 { WAKE_UCAST, Config5, UWF },
681 { WAKE_BCAST, Config5, BWF },
682 { WAKE_MCAST, Config5, MWF },
683 { WAKE_ANY, Config5, LanWake }
684 };
685
686 spin_lock_irq(&tp->lock);
687
688 RTL_W8(Cfg9346, Cfg9346_Unlock);
689
690 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
691 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
692 if (wol->wolopts & cfg[i].opt)
693 options |= cfg[i].mask;
694 RTL_W8(cfg[i].reg, options);
695 }
696
697 RTL_W8(Cfg9346, Cfg9346_Lock);
698
699 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
700
701 spin_unlock_irq(&tp->lock);
702
703 return 0;
704 }
705
706 static void rtl8169_get_drvinfo(struct net_device *dev,
707 struct ethtool_drvinfo *info)
708 {
709 struct rtl8169_private *tp = netdev_priv(dev);
710
711 strcpy(info->driver, MODULENAME);
712 strcpy(info->version, RTL8169_VERSION);
713 strcpy(info->bus_info, pci_name(tp->pci_dev));
714 }
715
716 static int rtl8169_get_regs_len(struct net_device *dev)
717 {
718 return R8169_REGS_SIZE;
719 }
720
721 static int rtl8169_set_speed_tbi(struct net_device *dev,
722 u8 autoneg, u16 speed, u8 duplex)
723 {
724 struct rtl8169_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
726 int ret = 0;
727 u32 reg;
728
729 reg = RTL_R32(TBICSR);
730 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
731 (duplex == DUPLEX_FULL)) {
732 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
733 } else if (autoneg == AUTONEG_ENABLE)
734 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
735 else {
736 if (netif_msg_link(tp)) {
737 printk(KERN_WARNING "%s: "
738 "incorrect speed setting refused in TBI mode\n",
739 dev->name);
740 }
741 ret = -EOPNOTSUPP;
742 }
743
744 return ret;
745 }
746
747 static int rtl8169_set_speed_xmii(struct net_device *dev,
748 u8 autoneg, u16 speed, u8 duplex)
749 {
750 struct rtl8169_private *tp = netdev_priv(dev);
751 void __iomem *ioaddr = tp->mmio_addr;
752 int auto_nego, giga_ctrl;
753
754 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
755 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
756 ADVERTISE_100HALF | ADVERTISE_100FULL);
757 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
758 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
759
760 if (autoneg == AUTONEG_ENABLE) {
761 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
762 ADVERTISE_100HALF | ADVERTISE_100FULL);
763 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
764 } else {
765 if (speed == SPEED_10)
766 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
767 else if (speed == SPEED_100)
768 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
769 else if (speed == SPEED_1000)
770 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
771
772 if (duplex == DUPLEX_HALF)
773 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
774
775 if (duplex == DUPLEX_FULL)
776 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
777
778 /* This tweak comes straight from Realtek's driver. */
779 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
780 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
781 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
782 }
783 }
784
785 /* The 8100e/8101e do Fast Ethernet only. */
786 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
787 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
788 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
789 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
790 netif_msg_link(tp)) {
791 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
792 dev->name);
793 }
794 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
795 }
796
797 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
798
799 tp->phy_auto_nego_reg = auto_nego;
800 tp->phy_1000_ctrl_reg = giga_ctrl;
801
802 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
803 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
804 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
805 return 0;
806 }
807
808 static int rtl8169_set_speed(struct net_device *dev,
809 u8 autoneg, u16 speed, u8 duplex)
810 {
811 struct rtl8169_private *tp = netdev_priv(dev);
812 int ret;
813
814 ret = tp->set_speed(dev, autoneg, speed, duplex);
815
816 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
817 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
818
819 return ret;
820 }
821
822 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
823 {
824 struct rtl8169_private *tp = netdev_priv(dev);
825 unsigned long flags;
826 int ret;
827
828 spin_lock_irqsave(&tp->lock, flags);
829 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
830 spin_unlock_irqrestore(&tp->lock, flags);
831
832 return ret;
833 }
834
835 static u32 rtl8169_get_rx_csum(struct net_device *dev)
836 {
837 struct rtl8169_private *tp = netdev_priv(dev);
838
839 return tp->cp_cmd & RxChkSum;
840 }
841
842 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
843 {
844 struct rtl8169_private *tp = netdev_priv(dev);
845 void __iomem *ioaddr = tp->mmio_addr;
846 unsigned long flags;
847
848 spin_lock_irqsave(&tp->lock, flags);
849
850 if (data)
851 tp->cp_cmd |= RxChkSum;
852 else
853 tp->cp_cmd &= ~RxChkSum;
854
855 RTL_W16(CPlusCmd, tp->cp_cmd);
856 RTL_R16(CPlusCmd);
857
858 spin_unlock_irqrestore(&tp->lock, flags);
859
860 return 0;
861 }
862
863 #ifdef CONFIG_R8169_VLAN
864
865 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
866 struct sk_buff *skb)
867 {
868 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
869 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
870 }
871
872 static void rtl8169_vlan_rx_register(struct net_device *dev,
873 struct vlan_group *grp)
874 {
875 struct rtl8169_private *tp = netdev_priv(dev);
876 void __iomem *ioaddr = tp->mmio_addr;
877 unsigned long flags;
878
879 spin_lock_irqsave(&tp->lock, flags);
880 tp->vlgrp = grp;
881 if (tp->vlgrp)
882 tp->cp_cmd |= RxVlan;
883 else
884 tp->cp_cmd &= ~RxVlan;
885 RTL_W16(CPlusCmd, tp->cp_cmd);
886 RTL_R16(CPlusCmd);
887 spin_unlock_irqrestore(&tp->lock, flags);
888 }
889
890 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
891 {
892 struct rtl8169_private *tp = netdev_priv(dev);
893 unsigned long flags;
894
895 spin_lock_irqsave(&tp->lock, flags);
896 if (tp->vlgrp)
897 tp->vlgrp->vlan_devices[vid] = NULL;
898 spin_unlock_irqrestore(&tp->lock, flags);
899 }
900
901 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
902 struct sk_buff *skb)
903 {
904 u32 opts2 = le32_to_cpu(desc->opts2);
905 int ret;
906
907 if (tp->vlgrp && (opts2 & RxVlanTag)) {
908 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
909 swab16(opts2 & 0xffff));
910 ret = 0;
911 } else
912 ret = -1;
913 desc->opts2 = 0;
914 return ret;
915 }
916
917 #else /* !CONFIG_R8169_VLAN */
918
919 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
920 struct sk_buff *skb)
921 {
922 return 0;
923 }
924
925 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
926 struct sk_buff *skb)
927 {
928 return -1;
929 }
930
931 #endif
932
933 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
934 {
935 struct rtl8169_private *tp = netdev_priv(dev);
936 void __iomem *ioaddr = tp->mmio_addr;
937 u32 status;
938
939 cmd->supported =
940 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
941 cmd->port = PORT_FIBRE;
942 cmd->transceiver = XCVR_INTERNAL;
943
944 status = RTL_R32(TBICSR);
945 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
946 cmd->autoneg = !!(status & TBINwEnable);
947
948 cmd->speed = SPEED_1000;
949 cmd->duplex = DUPLEX_FULL; /* Always set */
950 }
951
952 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
953 {
954 struct rtl8169_private *tp = netdev_priv(dev);
955 void __iomem *ioaddr = tp->mmio_addr;
956 u8 status;
957
958 cmd->supported = SUPPORTED_10baseT_Half |
959 SUPPORTED_10baseT_Full |
960 SUPPORTED_100baseT_Half |
961 SUPPORTED_100baseT_Full |
962 SUPPORTED_1000baseT_Full |
963 SUPPORTED_Autoneg |
964 SUPPORTED_TP;
965
966 cmd->autoneg = 1;
967 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
968
969 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
970 cmd->advertising |= ADVERTISED_10baseT_Half;
971 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
972 cmd->advertising |= ADVERTISED_10baseT_Full;
973 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
974 cmd->advertising |= ADVERTISED_100baseT_Half;
975 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
976 cmd->advertising |= ADVERTISED_100baseT_Full;
977 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
978 cmd->advertising |= ADVERTISED_1000baseT_Full;
979
980 status = RTL_R8(PHYstatus);
981
982 if (status & _1000bpsF)
983 cmd->speed = SPEED_1000;
984 else if (status & _100bps)
985 cmd->speed = SPEED_100;
986 else if (status & _10bps)
987 cmd->speed = SPEED_10;
988
989 if (status & TxFlowCtrl)
990 cmd->advertising |= ADVERTISED_Asym_Pause;
991 if (status & RxFlowCtrl)
992 cmd->advertising |= ADVERTISED_Pause;
993
994 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
995 DUPLEX_FULL : DUPLEX_HALF;
996 }
997
998 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
999 {
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&tp->lock, flags);
1004
1005 tp->get_settings(dev, cmd);
1006
1007 spin_unlock_irqrestore(&tp->lock, flags);
1008 return 0;
1009 }
1010
1011 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1012 void *p)
1013 {
1014 struct rtl8169_private *tp = netdev_priv(dev);
1015 unsigned long flags;
1016
1017 if (regs->len > R8169_REGS_SIZE)
1018 regs->len = R8169_REGS_SIZE;
1019
1020 spin_lock_irqsave(&tp->lock, flags);
1021 memcpy_fromio(p, tp->mmio_addr, regs->len);
1022 spin_unlock_irqrestore(&tp->lock, flags);
1023 }
1024
1025 static u32 rtl8169_get_msglevel(struct net_device *dev)
1026 {
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 return tp->msg_enable;
1030 }
1031
1032 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1033 {
1034 struct rtl8169_private *tp = netdev_priv(dev);
1035
1036 tp->msg_enable = value;
1037 }
1038
1039 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1040 "tx_packets",
1041 "rx_packets",
1042 "tx_errors",
1043 "rx_errors",
1044 "rx_missed",
1045 "align_errors",
1046 "tx_single_collisions",
1047 "tx_multi_collisions",
1048 "unicast",
1049 "broadcast",
1050 "multicast",
1051 "tx_aborted",
1052 "tx_underrun",
1053 };
1054
1055 struct rtl8169_counters {
1056 u64 tx_packets;
1057 u64 rx_packets;
1058 u64 tx_errors;
1059 u32 rx_errors;
1060 u16 rx_missed;
1061 u16 align_errors;
1062 u32 tx_one_collision;
1063 u32 tx_multi_collision;
1064 u64 rx_unicast;
1065 u64 rx_broadcast;
1066 u32 rx_multicast;
1067 u16 tx_aborted;
1068 u16 tx_underun;
1069 };
1070
1071 static int rtl8169_get_stats_count(struct net_device *dev)
1072 {
1073 return ARRAY_SIZE(rtl8169_gstrings);
1074 }
1075
1076 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1077 struct ethtool_stats *stats, u64 *data)
1078 {
1079 struct rtl8169_private *tp = netdev_priv(dev);
1080 void __iomem *ioaddr = tp->mmio_addr;
1081 struct rtl8169_counters *counters;
1082 dma_addr_t paddr;
1083 u32 cmd;
1084
1085 ASSERT_RTNL();
1086
1087 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1088 if (!counters)
1089 return;
1090
1091 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1092 cmd = (u64)paddr & DMA_32BIT_MASK;
1093 RTL_W32(CounterAddrLow, cmd);
1094 RTL_W32(CounterAddrLow, cmd | CounterDump);
1095
1096 while (RTL_R32(CounterAddrLow) & CounterDump) {
1097 if (msleep_interruptible(1))
1098 break;
1099 }
1100
1101 RTL_W32(CounterAddrLow, 0);
1102 RTL_W32(CounterAddrHigh, 0);
1103
1104 data[0] = le64_to_cpu(counters->tx_packets);
1105 data[1] = le64_to_cpu(counters->rx_packets);
1106 data[2] = le64_to_cpu(counters->tx_errors);
1107 data[3] = le32_to_cpu(counters->rx_errors);
1108 data[4] = le16_to_cpu(counters->rx_missed);
1109 data[5] = le16_to_cpu(counters->align_errors);
1110 data[6] = le32_to_cpu(counters->tx_one_collision);
1111 data[7] = le32_to_cpu(counters->tx_multi_collision);
1112 data[8] = le64_to_cpu(counters->rx_unicast);
1113 data[9] = le64_to_cpu(counters->rx_broadcast);
1114 data[10] = le32_to_cpu(counters->rx_multicast);
1115 data[11] = le16_to_cpu(counters->tx_aborted);
1116 data[12] = le16_to_cpu(counters->tx_underun);
1117
1118 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1119 }
1120
1121 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1122 {
1123 switch(stringset) {
1124 case ETH_SS_STATS:
1125 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1126 break;
1127 }
1128 }
1129
1130
1131 static const struct ethtool_ops rtl8169_ethtool_ops = {
1132 .get_drvinfo = rtl8169_get_drvinfo,
1133 .get_regs_len = rtl8169_get_regs_len,
1134 .get_link = ethtool_op_get_link,
1135 .get_settings = rtl8169_get_settings,
1136 .set_settings = rtl8169_set_settings,
1137 .get_msglevel = rtl8169_get_msglevel,
1138 .set_msglevel = rtl8169_set_msglevel,
1139 .get_rx_csum = rtl8169_get_rx_csum,
1140 .set_rx_csum = rtl8169_set_rx_csum,
1141 .get_tx_csum = ethtool_op_get_tx_csum,
1142 .set_tx_csum = ethtool_op_set_tx_csum,
1143 .get_sg = ethtool_op_get_sg,
1144 .set_sg = ethtool_op_set_sg,
1145 .get_tso = ethtool_op_get_tso,
1146 .set_tso = ethtool_op_set_tso,
1147 .get_regs = rtl8169_get_regs,
1148 .get_wol = rtl8169_get_wol,
1149 .set_wol = rtl8169_set_wol,
1150 .get_strings = rtl8169_get_strings,
1151 .get_stats_count = rtl8169_get_stats_count,
1152 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1153 .get_perm_addr = ethtool_op_get_perm_addr,
1154 };
1155
1156 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1157 int bitval)
1158 {
1159 int val;
1160
1161 val = mdio_read(ioaddr, reg);
1162 val = (bitval == 1) ?
1163 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1164 mdio_write(ioaddr, reg, val & 0xffff);
1165 }
1166
1167 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1168 {
1169 const struct {
1170 u32 mask;
1171 int mac_version;
1172 } mac_info[] = {
1173 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1174 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1175 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1176 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1177 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1178 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1179 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1180 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1181 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1182 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1183 }, *p = mac_info;
1184 u32 reg;
1185
1186 reg = RTL_R32(TxConfig) & 0x7c800000;
1187 while ((reg & p->mask) != p->mask)
1188 p++;
1189 tp->mac_version = p->mac_version;
1190 }
1191
1192 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1193 {
1194 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1195 }
1196
1197 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1198 {
1199 const struct {
1200 u16 mask;
1201 u16 set;
1202 int phy_version;
1203 } phy_info[] = {
1204 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1205 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1206 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1207 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1208 }, *p = phy_info;
1209 u16 reg;
1210
1211 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1212 while ((reg & p->mask) != p->set)
1213 p++;
1214 tp->phy_version = p->phy_version;
1215 }
1216
1217 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1218 {
1219 struct {
1220 int version;
1221 char *msg;
1222 u32 reg;
1223 } phy_print[] = {
1224 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1225 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1226 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1227 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1228 { 0, NULL, 0x0000 }
1229 }, *p;
1230
1231 for (p = phy_print; p->msg; p++) {
1232 if (tp->phy_version == p->version) {
1233 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1234 return;
1235 }
1236 }
1237 dprintk("phy_version == Unknown\n");
1238 }
1239
1240 static void rtl8169_hw_phy_config(struct net_device *dev)
1241 {
1242 struct rtl8169_private *tp = netdev_priv(dev);
1243 void __iomem *ioaddr = tp->mmio_addr;
1244 struct {
1245 u16 regs[5]; /* Beware of bit-sign propagation */
1246 } phy_magic[5] = { {
1247 { 0x0000, //w 4 15 12 0
1248 0x00a1, //w 3 15 0 00a1
1249 0x0008, //w 2 15 0 0008
1250 0x1020, //w 1 15 0 1020
1251 0x1000 } },{ //w 0 15 0 1000
1252 { 0x7000, //w 4 15 12 7
1253 0xff41, //w 3 15 0 ff41
1254 0xde60, //w 2 15 0 de60
1255 0x0140, //w 1 15 0 0140
1256 0x0077 } },{ //w 0 15 0 0077
1257 { 0xa000, //w 4 15 12 a
1258 0xdf01, //w 3 15 0 df01
1259 0xdf20, //w 2 15 0 df20
1260 0xff95, //w 1 15 0 ff95
1261 0xfa00 } },{ //w 0 15 0 fa00
1262 { 0xb000, //w 4 15 12 b
1263 0xff41, //w 3 15 0 ff41
1264 0xde20, //w 2 15 0 de20
1265 0x0140, //w 1 15 0 0140
1266 0x00bb } },{ //w 0 15 0 00bb
1267 { 0xf000, //w 4 15 12 f
1268 0xdf01, //w 3 15 0 df01
1269 0xdf20, //w 2 15 0 df20
1270 0xff95, //w 1 15 0 ff95
1271 0xbf00 } //w 0 15 0 bf00
1272 }
1273 }, *p = phy_magic;
1274 int i;
1275
1276 rtl8169_print_mac_version(tp);
1277 rtl8169_print_phy_version(tp);
1278
1279 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1280 return;
1281 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1282 return;
1283
1284 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1285 dprintk("Do final_reg2.cfg\n");
1286
1287 /* Shazam ! */
1288
1289 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1290 mdio_write(ioaddr, 31, 0x0002);
1291 mdio_write(ioaddr, 1, 0x90d0);
1292 mdio_write(ioaddr, 31, 0x0000);
1293 return;
1294 }
1295
1296 /* phy config for RTL8169s mac_version C chip */
1297 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1298 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1299 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1300 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1301
1302 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1303 int val, pos = 4;
1304
1305 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1306 mdio_write(ioaddr, pos, val);
1307 while (--pos >= 0)
1308 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1309 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1311 }
1312 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1313 }
1314
1315 static void rtl8169_phy_timer(unsigned long __opaque)
1316 {
1317 struct net_device *dev = (struct net_device *)__opaque;
1318 struct rtl8169_private *tp = netdev_priv(dev);
1319 struct timer_list *timer = &tp->timer;
1320 void __iomem *ioaddr = tp->mmio_addr;
1321 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1322
1323 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1324 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1325
1326 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1327 return;
1328
1329 spin_lock_irq(&tp->lock);
1330
1331 if (tp->phy_reset_pending(ioaddr)) {
1332 /*
1333 * A busy loop could burn quite a few cycles on nowadays CPU.
1334 * Let's delay the execution of the timer for a few ticks.
1335 */
1336 timeout = HZ/10;
1337 goto out_mod_timer;
1338 }
1339
1340 if (tp->link_ok(ioaddr))
1341 goto out_unlock;
1342
1343 if (netif_msg_link(tp))
1344 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1345
1346 tp->phy_reset_enable(ioaddr);
1347
1348 out_mod_timer:
1349 mod_timer(timer, jiffies + timeout);
1350 out_unlock:
1351 spin_unlock_irq(&tp->lock);
1352 }
1353
1354 static inline void rtl8169_delete_timer(struct net_device *dev)
1355 {
1356 struct rtl8169_private *tp = netdev_priv(dev);
1357 struct timer_list *timer = &tp->timer;
1358
1359 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1360 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1361 return;
1362
1363 del_timer_sync(timer);
1364 }
1365
1366 static inline void rtl8169_request_timer(struct net_device *dev)
1367 {
1368 struct rtl8169_private *tp = netdev_priv(dev);
1369 struct timer_list *timer = &tp->timer;
1370
1371 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1372 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1373 return;
1374
1375 init_timer(timer);
1376 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1377 timer->data = (unsigned long)(dev);
1378 timer->function = rtl8169_phy_timer;
1379 add_timer(timer);
1380 }
1381
1382 #ifdef CONFIG_NET_POLL_CONTROLLER
1383 /*
1384 * Polling 'interrupt' - used by things like netconsole to send skbs
1385 * without having to re-enable interrupts. It's not called while
1386 * the interrupt routine is executing.
1387 */
1388 static void rtl8169_netpoll(struct net_device *dev)
1389 {
1390 struct rtl8169_private *tp = netdev_priv(dev);
1391 struct pci_dev *pdev = tp->pci_dev;
1392
1393 disable_irq(pdev->irq);
1394 rtl8169_interrupt(pdev->irq, dev);
1395 enable_irq(pdev->irq);
1396 }
1397 #endif
1398
1399 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1400 void __iomem *ioaddr)
1401 {
1402 iounmap(ioaddr);
1403 pci_release_regions(pdev);
1404 pci_disable_device(pdev);
1405 free_netdev(dev);
1406 }
1407
1408 static void rtl8169_phy_reset(struct net_device *dev,
1409 struct rtl8169_private *tp)
1410 {
1411 void __iomem *ioaddr = tp->mmio_addr;
1412 int i;
1413
1414 tp->phy_reset_enable(ioaddr);
1415 for (i = 0; i < 100; i++) {
1416 if (!tp->phy_reset_pending(ioaddr))
1417 return;
1418 msleep(1);
1419 }
1420 if (netif_msg_link(tp))
1421 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1422 }
1423
1424 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1425 {
1426 void __iomem *ioaddr = tp->mmio_addr;
1427 static int board_idx = -1;
1428 u8 autoneg, duplex;
1429 u16 speed;
1430
1431 board_idx++;
1432
1433 rtl8169_hw_phy_config(dev);
1434
1435 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1436 RTL_W8(0x82, 0x01);
1437
1438 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
1439 dprintk("Set PCI Latency=0x40\n");
1440 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1441 }
1442
1443 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1444 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1445 RTL_W8(0x82, 0x01);
1446 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1447 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1448 }
1449
1450 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1451
1452 rtl8169_phy_reset(dev, tp);
1453
1454 rtl8169_set_speed(dev, autoneg, speed, duplex);
1455
1456 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1457 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1458 }
1459
1460 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1461 {
1462 struct rtl8169_private *tp = netdev_priv(dev);
1463 struct mii_ioctl_data *data = if_mii(ifr);
1464
1465 if (!netif_running(dev))
1466 return -ENODEV;
1467
1468 switch (cmd) {
1469 case SIOCGMIIPHY:
1470 data->phy_id = 32; /* Internal PHY */
1471 return 0;
1472
1473 case SIOCGMIIREG:
1474 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1475 return 0;
1476
1477 case SIOCSMIIREG:
1478 if (!capable(CAP_NET_ADMIN))
1479 return -EPERM;
1480 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1481 return 0;
1482 }
1483 return -EOPNOTSUPP;
1484 }
1485
1486 static int __devinit
1487 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1488 {
1489 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1490 struct rtl8169_private *tp;
1491 struct net_device *dev;
1492 void __iomem *ioaddr;
1493 unsigned int pm_cap;
1494 int i, rc;
1495
1496 if (netif_msg_drv(&debug)) {
1497 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1498 MODULENAME, RTL8169_VERSION);
1499 }
1500
1501 dev = alloc_etherdev(sizeof (*tp));
1502 if (!dev) {
1503 if (netif_msg_drv(&debug))
1504 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1505 rc = -ENOMEM;
1506 goto out;
1507 }
1508
1509 SET_MODULE_OWNER(dev);
1510 SET_NETDEV_DEV(dev, &pdev->dev);
1511 tp = netdev_priv(dev);
1512 tp->dev = dev;
1513 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1514
1515 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1516 rc = pci_enable_device(pdev);
1517 if (rc < 0) {
1518 if (netif_msg_probe(tp))
1519 dev_err(&pdev->dev, "enable failure\n");
1520 goto err_out_free_dev_1;
1521 }
1522
1523 rc = pci_set_mwi(pdev);
1524 if (rc < 0)
1525 goto err_out_disable_2;
1526
1527 /* save power state before pci_enable_device overwrites it */
1528 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1529 if (pm_cap) {
1530 u16 pwr_command, acpi_idle_state;
1531
1532 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1533 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1534 } else {
1535 if (netif_msg_probe(tp)) {
1536 dev_err(&pdev->dev,
1537 "PowerManagement capability not found.\n");
1538 }
1539 }
1540
1541 /* make sure PCI base addr 1 is MMIO */
1542 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1543 if (netif_msg_probe(tp)) {
1544 dev_err(&pdev->dev,
1545 "region #%d not an MMIO resource, aborting\n",
1546 region);
1547 }
1548 rc = -ENODEV;
1549 goto err_out_mwi_3;
1550 }
1551
1552 /* check for weird/broken PCI region reporting */
1553 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1554 if (netif_msg_probe(tp)) {
1555 dev_err(&pdev->dev,
1556 "Invalid PCI region size(s), aborting\n");
1557 }
1558 rc = -ENODEV;
1559 goto err_out_mwi_3;
1560 }
1561
1562 rc = pci_request_regions(pdev, MODULENAME);
1563 if (rc < 0) {
1564 if (netif_msg_probe(tp))
1565 dev_err(&pdev->dev, "could not request regions.\n");
1566 goto err_out_mwi_3;
1567 }
1568
1569 tp->cp_cmd = PCIMulRW | RxChkSum;
1570
1571 if ((sizeof(dma_addr_t) > 4) &&
1572 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1573 tp->cp_cmd |= PCIDAC;
1574 dev->features |= NETIF_F_HIGHDMA;
1575 } else {
1576 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1577 if (rc < 0) {
1578 if (netif_msg_probe(tp)) {
1579 dev_err(&pdev->dev,
1580 "DMA configuration failed.\n");
1581 }
1582 goto err_out_free_res_4;
1583 }
1584 }
1585
1586 pci_set_master(pdev);
1587
1588 /* ioremap MMIO region */
1589 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1590 if (!ioaddr) {
1591 if (netif_msg_probe(tp))
1592 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1593 rc = -EIO;
1594 goto err_out_free_res_4;
1595 }
1596
1597 /* Unneeded ? Don't mess with Mrs. Murphy. */
1598 rtl8169_irq_mask_and_ack(ioaddr);
1599
1600 /* Soft reset the chip. */
1601 RTL_W8(ChipCmd, CmdReset);
1602
1603 /* Check that the chip has finished the reset. */
1604 for (i = 100; i > 0; i--) {
1605 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1606 break;
1607 msleep_interruptible(1);
1608 }
1609
1610 /* Identify chip attached to board */
1611 rtl8169_get_mac_version(tp, ioaddr);
1612 rtl8169_get_phy_version(tp, ioaddr);
1613
1614 rtl8169_print_mac_version(tp);
1615 rtl8169_print_phy_version(tp);
1616
1617 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1618 if (tp->mac_version == rtl_chip_info[i].mac_version)
1619 break;
1620 }
1621 if (i < 0) {
1622 /* Unknown chip: assume array element #0, original RTL-8169 */
1623 if (netif_msg_probe(tp)) {
1624 dev_printk(KERN_DEBUG, &pdev->dev,
1625 "unknown chip version, assuming %s\n",
1626 rtl_chip_info[0].name);
1627 }
1628 i++;
1629 }
1630 tp->chipset = i;
1631
1632 RTL_W8(Cfg9346, Cfg9346_Unlock);
1633 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1634 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1635 RTL_W8(Cfg9346, Cfg9346_Lock);
1636
1637 if (RTL_R8(PHYstatus) & TBI_Enable) {
1638 tp->set_speed = rtl8169_set_speed_tbi;
1639 tp->get_settings = rtl8169_gset_tbi;
1640 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1641 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1642 tp->link_ok = rtl8169_tbi_link_ok;
1643
1644 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1645 } else {
1646 tp->set_speed = rtl8169_set_speed_xmii;
1647 tp->get_settings = rtl8169_gset_xmii;
1648 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1649 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1650 tp->link_ok = rtl8169_xmii_link_ok;
1651
1652 dev->do_ioctl = rtl8169_ioctl;
1653 }
1654
1655 /* Get MAC address. FIXME: read EEPROM */
1656 for (i = 0; i < MAC_ADDR_LEN; i++)
1657 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1658 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1659
1660 dev->open = rtl8169_open;
1661 dev->hard_start_xmit = rtl8169_start_xmit;
1662 dev->get_stats = rtl8169_get_stats;
1663 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1664 dev->stop = rtl8169_close;
1665 dev->tx_timeout = rtl8169_tx_timeout;
1666 dev->set_multicast_list = rtl8169_set_rx_mode;
1667 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1668 dev->irq = pdev->irq;
1669 dev->base_addr = (unsigned long) ioaddr;
1670 dev->change_mtu = rtl8169_change_mtu;
1671
1672 #ifdef CONFIG_R8169_NAPI
1673 dev->poll = rtl8169_poll;
1674 dev->weight = R8169_NAPI_WEIGHT;
1675 #endif
1676
1677 #ifdef CONFIG_R8169_VLAN
1678 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1679 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1680 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1681 #endif
1682
1683 #ifdef CONFIG_NET_POLL_CONTROLLER
1684 dev->poll_controller = rtl8169_netpoll;
1685 #endif
1686
1687 tp->intr_mask = 0xffff;
1688 tp->pci_dev = pdev;
1689 tp->mmio_addr = ioaddr;
1690 tp->align = rtl_cfg_info[ent->driver_data].align;
1691
1692 spin_lock_init(&tp->lock);
1693
1694 rc = register_netdev(dev);
1695 if (rc < 0)
1696 goto err_out_unmap_5;
1697
1698 pci_set_drvdata(pdev, dev);
1699
1700 if (netif_msg_probe(tp)) {
1701 printk(KERN_INFO "%s: %s at 0x%lx, "
1702 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1703 "IRQ %d\n",
1704 dev->name,
1705 rtl_chip_info[tp->chipset].name,
1706 dev->base_addr,
1707 dev->dev_addr[0], dev->dev_addr[1],
1708 dev->dev_addr[2], dev->dev_addr[3],
1709 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1710 }
1711
1712 rtl8169_init_phy(dev, tp);
1713
1714 out:
1715 return rc;
1716
1717 err_out_unmap_5:
1718 iounmap(ioaddr);
1719 err_out_free_res_4:
1720 pci_release_regions(pdev);
1721 err_out_mwi_3:
1722 pci_clear_mwi(pdev);
1723 err_out_disable_2:
1724 pci_disable_device(pdev);
1725 err_out_free_dev_1:
1726 free_netdev(dev);
1727 goto out;
1728 }
1729
1730 static void __devexit
1731 rtl8169_remove_one(struct pci_dev *pdev)
1732 {
1733 struct net_device *dev = pci_get_drvdata(pdev);
1734 struct rtl8169_private *tp = netdev_priv(dev);
1735
1736 assert(dev != NULL);
1737 assert(tp != NULL);
1738
1739 unregister_netdev(dev);
1740 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1741 pci_set_drvdata(pdev, NULL);
1742 }
1743
1744 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1745 struct net_device *dev)
1746 {
1747 unsigned int mtu = dev->mtu;
1748
1749 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1750 }
1751
1752 static int rtl8169_open(struct net_device *dev)
1753 {
1754 struct rtl8169_private *tp = netdev_priv(dev);
1755 struct pci_dev *pdev = tp->pci_dev;
1756 int retval;
1757
1758 rtl8169_set_rxbufsize(tp, dev);
1759
1760 retval =
1761 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1762 if (retval < 0)
1763 goto out;
1764
1765 retval = -ENOMEM;
1766
1767 /*
1768 * Rx and Tx desscriptors needs 256 bytes alignment.
1769 * pci_alloc_consistent provides more.
1770 */
1771 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1772 &tp->TxPhyAddr);
1773 if (!tp->TxDescArray)
1774 goto err_free_irq;
1775
1776 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1777 &tp->RxPhyAddr);
1778 if (!tp->RxDescArray)
1779 goto err_free_tx;
1780
1781 retval = rtl8169_init_ring(dev);
1782 if (retval < 0)
1783 goto err_free_rx;
1784
1785 INIT_DELAYED_WORK(&tp->task, NULL);
1786
1787 rtl8169_hw_start(dev);
1788
1789 rtl8169_request_timer(dev);
1790
1791 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1792 out:
1793 return retval;
1794
1795 err_free_rx:
1796 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1797 tp->RxPhyAddr);
1798 err_free_tx:
1799 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1800 tp->TxPhyAddr);
1801 err_free_irq:
1802 free_irq(dev->irq, dev);
1803 goto out;
1804 }
1805
1806 static void rtl8169_hw_reset(void __iomem *ioaddr)
1807 {
1808 /* Disable interrupts */
1809 rtl8169_irq_mask_and_ack(ioaddr);
1810
1811 /* Reset the chipset */
1812 RTL_W8(ChipCmd, CmdReset);
1813
1814 /* PCI commit */
1815 RTL_R8(ChipCmd);
1816 }
1817
1818 static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
1819 {
1820 void __iomem *ioaddr = tp->mmio_addr;
1821 u32 cfg = rtl8169_rx_config;
1822
1823 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1824 RTL_W32(RxConfig, cfg);
1825
1826 /* Set DMA burst size and Interframe Gap Time */
1827 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1828 (InterFrameGap << TxInterFrameGapShift));
1829 }
1830
1831 static void rtl8169_hw_start(struct net_device *dev)
1832 {
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 void __iomem *ioaddr = tp->mmio_addr;
1835 struct pci_dev *pdev = tp->pci_dev;
1836 u16 cmd;
1837 u32 i;
1838
1839 /* Soft reset the chip. */
1840 RTL_W8(ChipCmd, CmdReset);
1841
1842 /* Check that the chip has finished the reset. */
1843 for (i = 100; i > 0; i--) {
1844 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1845 break;
1846 msleep_interruptible(1);
1847 }
1848
1849 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1850 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1851 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1852 }
1853
1854 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1855 pci_write_config_word(pdev, 0x68, 0x00);
1856 pci_write_config_word(pdev, 0x69, 0x08);
1857 }
1858
1859 /* Undocumented stuff. */
1860 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1861 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1862 if ((RTL_R8(Config2) & 0x07) & 0x01)
1863 RTL_W32(0x7c, 0x0007ffff);
1864
1865 RTL_W32(0x7c, 0x0007ff00);
1866
1867 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1868 cmd = cmd & 0xef;
1869 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1870 }
1871
1872 RTL_W8(Cfg9346, Cfg9346_Unlock);
1873 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1874 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1876 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1877 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1878
1879 RTL_W8(EarlyTxThres, EarlyTxThld);
1880
1881 /* Low hurts. Let's disable the filtering. */
1882 RTL_W16(RxMaxSize, 16383);
1883
1884 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1885 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1886 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1887 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1888 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1889 rtl8169_set_rx_tx_config_registers(tp);
1890
1891 cmd = RTL_R16(CPlusCmd);
1892 RTL_W16(CPlusCmd, cmd);
1893
1894 tp->cp_cmd |= cmd | PCIMulRW;
1895
1896 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1897 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1898 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1899 "Bit-3 and bit-14 MUST be 1\n");
1900 tp->cp_cmd |= (1 << 14);
1901 }
1902
1903 RTL_W16(CPlusCmd, tp->cp_cmd);
1904
1905 /*
1906 * Undocumented corner. Supposedly:
1907 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1908 */
1909 RTL_W16(IntrMitigate, 0x0000);
1910
1911 /*
1912 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1913 * register to be written before TxDescAddrLow to work.
1914 * Switching from MMIO to I/O access fixes the issue as well.
1915 */
1916 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1917 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1918 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1919 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1920
1921 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1922 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1923 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1924 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1925 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1926 rtl8169_set_rx_tx_config_registers(tp);
1927 }
1928
1929 RTL_W8(Cfg9346, Cfg9346_Lock);
1930
1931 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1932 RTL_R8(IntrMask);
1933
1934 RTL_W32(RxMissed, 0);
1935
1936 rtl8169_set_rx_mode(dev);
1937
1938 /* no early-rx interrupts */
1939 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1940
1941 /* Enable all known interrupts by setting the interrupt mask. */
1942 RTL_W16(IntrMask, rtl8169_intr_mask);
1943
1944 netif_start_queue(dev);
1945 }
1946
1947 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1948 {
1949 struct rtl8169_private *tp = netdev_priv(dev);
1950 int ret = 0;
1951
1952 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1953 return -EINVAL;
1954
1955 dev->mtu = new_mtu;
1956
1957 if (!netif_running(dev))
1958 goto out;
1959
1960 rtl8169_down(dev);
1961
1962 rtl8169_set_rxbufsize(tp, dev);
1963
1964 ret = rtl8169_init_ring(dev);
1965 if (ret < 0)
1966 goto out;
1967
1968 netif_poll_enable(dev);
1969
1970 rtl8169_hw_start(dev);
1971
1972 rtl8169_request_timer(dev);
1973
1974 out:
1975 return ret;
1976 }
1977
1978 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1979 {
1980 desc->addr = 0x0badbadbadbadbadull;
1981 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1982 }
1983
1984 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1985 struct sk_buff **sk_buff, struct RxDesc *desc)
1986 {
1987 struct pci_dev *pdev = tp->pci_dev;
1988
1989 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1990 PCI_DMA_FROMDEVICE);
1991 dev_kfree_skb(*sk_buff);
1992 *sk_buff = NULL;
1993 rtl8169_make_unusable_by_asic(desc);
1994 }
1995
1996 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1997 {
1998 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1999
2000 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2001 }
2002
2003 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2004 u32 rx_buf_sz)
2005 {
2006 desc->addr = cpu_to_le64(mapping);
2007 wmb();
2008 rtl8169_mark_to_asic(desc, rx_buf_sz);
2009 }
2010
2011 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
2012 struct RxDesc *desc, int rx_buf_sz,
2013 unsigned int align)
2014 {
2015 struct sk_buff *skb;
2016 dma_addr_t mapping;
2017 int ret = 0;
2018
2019 skb = dev_alloc_skb(rx_buf_sz + align);
2020 if (!skb)
2021 goto err_out;
2022
2023 skb_reserve(skb, (align - 1) & (u32)skb->data);
2024 *sk_buff = skb;
2025
2026 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2027 PCI_DMA_FROMDEVICE);
2028
2029 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2030
2031 out:
2032 return ret;
2033
2034 err_out:
2035 ret = -ENOMEM;
2036 rtl8169_make_unusable_by_asic(desc);
2037 goto out;
2038 }
2039
2040 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2041 {
2042 int i;
2043
2044 for (i = 0; i < NUM_RX_DESC; i++) {
2045 if (tp->Rx_skbuff[i]) {
2046 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2047 tp->RxDescArray + i);
2048 }
2049 }
2050 }
2051
2052 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2053 u32 start, u32 end)
2054 {
2055 u32 cur;
2056
2057 for (cur = start; end - cur > 0; cur++) {
2058 int ret, i = cur % NUM_RX_DESC;
2059
2060 if (tp->Rx_skbuff[i])
2061 continue;
2062
2063 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
2064 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
2065 if (ret < 0)
2066 break;
2067 }
2068 return cur - start;
2069 }
2070
2071 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2072 {
2073 desc->opts1 |= cpu_to_le32(RingEnd);
2074 }
2075
2076 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2077 {
2078 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2079 }
2080
2081 static int rtl8169_init_ring(struct net_device *dev)
2082 {
2083 struct rtl8169_private *tp = netdev_priv(dev);
2084
2085 rtl8169_init_ring_indexes(tp);
2086
2087 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2088 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2089
2090 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2091 goto err_out;
2092
2093 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2094
2095 return 0;
2096
2097 err_out:
2098 rtl8169_rx_clear(tp);
2099 return -ENOMEM;
2100 }
2101
2102 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2103 struct TxDesc *desc)
2104 {
2105 unsigned int len = tx_skb->len;
2106
2107 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2108 desc->opts1 = 0x00;
2109 desc->opts2 = 0x00;
2110 desc->addr = 0x00;
2111 tx_skb->len = 0;
2112 }
2113
2114 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2115 {
2116 unsigned int i;
2117
2118 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2119 unsigned int entry = i % NUM_TX_DESC;
2120 struct ring_info *tx_skb = tp->tx_skb + entry;
2121 unsigned int len = tx_skb->len;
2122
2123 if (len) {
2124 struct sk_buff *skb = tx_skb->skb;
2125
2126 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2127 tp->TxDescArray + entry);
2128 if (skb) {
2129 dev_kfree_skb(skb);
2130 tx_skb->skb = NULL;
2131 }
2132 tp->stats.tx_dropped++;
2133 }
2134 }
2135 tp->cur_tx = tp->dirty_tx = 0;
2136 }
2137
2138 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2139 {
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141
2142 PREPARE_DELAYED_WORK(&tp->task, task);
2143 schedule_delayed_work(&tp->task, 4);
2144 }
2145
2146 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2147 {
2148 struct rtl8169_private *tp = netdev_priv(dev);
2149 void __iomem *ioaddr = tp->mmio_addr;
2150
2151 synchronize_irq(dev->irq);
2152
2153 /* Wait for any pending NAPI task to complete */
2154 netif_poll_disable(dev);
2155
2156 rtl8169_irq_mask_and_ack(ioaddr);
2157
2158 netif_poll_enable(dev);
2159 }
2160
2161 static void rtl8169_reinit_task(struct work_struct *work)
2162 {
2163 struct rtl8169_private *tp =
2164 container_of(work, struct rtl8169_private, task.work);
2165 struct net_device *dev = tp->dev;
2166 int ret;
2167
2168 if (netif_running(dev)) {
2169 rtl8169_wait_for_quiescence(dev);
2170 rtl8169_close(dev);
2171 }
2172
2173 ret = rtl8169_open(dev);
2174 if (unlikely(ret < 0)) {
2175 if (net_ratelimit()) {
2176 struct rtl8169_private *tp = netdev_priv(dev);
2177
2178 if (netif_msg_drv(tp)) {
2179 printk(PFX KERN_ERR
2180 "%s: reinit failure (status = %d)."
2181 " Rescheduling.\n", dev->name, ret);
2182 }
2183 }
2184 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2185 }
2186 }
2187
2188 static void rtl8169_reset_task(struct work_struct *work)
2189 {
2190 struct rtl8169_private *tp =
2191 container_of(work, struct rtl8169_private, task.work);
2192 struct net_device *dev = tp->dev;
2193
2194 if (!netif_running(dev))
2195 return;
2196
2197 rtl8169_wait_for_quiescence(dev);
2198
2199 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2200 rtl8169_tx_clear(tp);
2201
2202 if (tp->dirty_rx == tp->cur_rx) {
2203 rtl8169_init_ring_indexes(tp);
2204 rtl8169_hw_start(dev);
2205 netif_wake_queue(dev);
2206 } else {
2207 if (net_ratelimit()) {
2208 struct rtl8169_private *tp = netdev_priv(dev);
2209
2210 if (netif_msg_intr(tp)) {
2211 printk(PFX KERN_EMERG
2212 "%s: Rx buffers shortage\n", dev->name);
2213 }
2214 }
2215 rtl8169_schedule_work(dev, rtl8169_reset_task);
2216 }
2217 }
2218
2219 static void rtl8169_tx_timeout(struct net_device *dev)
2220 {
2221 struct rtl8169_private *tp = netdev_priv(dev);
2222
2223 rtl8169_hw_reset(tp->mmio_addr);
2224
2225 /* Let's wait a bit while any (async) irq lands on */
2226 rtl8169_schedule_work(dev, rtl8169_reset_task);
2227 }
2228
2229 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2230 u32 opts1)
2231 {
2232 struct skb_shared_info *info = skb_shinfo(skb);
2233 unsigned int cur_frag, entry;
2234 struct TxDesc *txd;
2235
2236 entry = tp->cur_tx;
2237 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2238 skb_frag_t *frag = info->frags + cur_frag;
2239 dma_addr_t mapping;
2240 u32 status, len;
2241 void *addr;
2242
2243 entry = (entry + 1) % NUM_TX_DESC;
2244
2245 txd = tp->TxDescArray + entry;
2246 len = frag->size;
2247 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2248 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2249
2250 /* anti gcc 2.95.3 bugware (sic) */
2251 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2252
2253 txd->opts1 = cpu_to_le32(status);
2254 txd->addr = cpu_to_le64(mapping);
2255
2256 tp->tx_skb[entry].len = len;
2257 }
2258
2259 if (cur_frag) {
2260 tp->tx_skb[entry].skb = skb;
2261 txd->opts1 |= cpu_to_le32(LastFrag);
2262 }
2263
2264 return cur_frag;
2265 }
2266
2267 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2268 {
2269 if (dev->features & NETIF_F_TSO) {
2270 u32 mss = skb_shinfo(skb)->gso_size;
2271
2272 if (mss)
2273 return LargeSend | ((mss & MSSMask) << MSSShift);
2274 }
2275 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2276 const struct iphdr *ip = skb->nh.iph;
2277
2278 if (ip->protocol == IPPROTO_TCP)
2279 return IPCS | TCPCS;
2280 else if (ip->protocol == IPPROTO_UDP)
2281 return IPCS | UDPCS;
2282 WARN_ON(1); /* we need a WARN() */
2283 }
2284 return 0;
2285 }
2286
2287 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2288 {
2289 struct rtl8169_private *tp = netdev_priv(dev);
2290 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2291 struct TxDesc *txd = tp->TxDescArray + entry;
2292 void __iomem *ioaddr = tp->mmio_addr;
2293 dma_addr_t mapping;
2294 u32 status, len;
2295 u32 opts1;
2296 int ret = NETDEV_TX_OK;
2297
2298 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2299 if (netif_msg_drv(tp)) {
2300 printk(KERN_ERR
2301 "%s: BUG! Tx Ring full when queue awake!\n",
2302 dev->name);
2303 }
2304 goto err_stop;
2305 }
2306
2307 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2308 goto err_stop;
2309
2310 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2311
2312 frags = rtl8169_xmit_frags(tp, skb, opts1);
2313 if (frags) {
2314 len = skb_headlen(skb);
2315 opts1 |= FirstFrag;
2316 } else {
2317 len = skb->len;
2318
2319 if (unlikely(len < ETH_ZLEN)) {
2320 if (skb_padto(skb, ETH_ZLEN))
2321 goto err_update_stats;
2322 len = ETH_ZLEN;
2323 }
2324
2325 opts1 |= FirstFrag | LastFrag;
2326 tp->tx_skb[entry].skb = skb;
2327 }
2328
2329 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2330
2331 tp->tx_skb[entry].len = len;
2332 txd->addr = cpu_to_le64(mapping);
2333 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2334
2335 wmb();
2336
2337 /* anti gcc 2.95.3 bugware (sic) */
2338 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2339 txd->opts1 = cpu_to_le32(status);
2340
2341 dev->trans_start = jiffies;
2342
2343 tp->cur_tx += frags + 1;
2344
2345 smp_wmb();
2346
2347 RTL_W8(TxPoll, 0x40); /* set polling bit */
2348
2349 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2350 netif_stop_queue(dev);
2351 smp_rmb();
2352 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2353 netif_wake_queue(dev);
2354 }
2355
2356 out:
2357 return ret;
2358
2359 err_stop:
2360 netif_stop_queue(dev);
2361 ret = NETDEV_TX_BUSY;
2362 err_update_stats:
2363 tp->stats.tx_dropped++;
2364 goto out;
2365 }
2366
2367 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2368 {
2369 struct rtl8169_private *tp = netdev_priv(dev);
2370 struct pci_dev *pdev = tp->pci_dev;
2371 void __iomem *ioaddr = tp->mmio_addr;
2372 u16 pci_status, pci_cmd;
2373
2374 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2375 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2376
2377 if (netif_msg_intr(tp)) {
2378 printk(KERN_ERR
2379 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2380 dev->name, pci_cmd, pci_status);
2381 }
2382
2383 /*
2384 * The recovery sequence below admits a very elaborated explanation:
2385 * - it seems to work;
2386 * - I did not see what else could be done;
2387 * - it makes iop3xx happy.
2388 *
2389 * Feel free to adjust to your needs.
2390 */
2391 if (ignore_parity_err)
2392 pci_cmd &= ~PCI_COMMAND_PARITY;
2393 else
2394 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2395
2396 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2397
2398 pci_write_config_word(pdev, PCI_STATUS,
2399 pci_status & (PCI_STATUS_DETECTED_PARITY |
2400 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2401 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2402
2403 /* The infamous DAC f*ckup only happens at boot time */
2404 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2405 if (netif_msg_intr(tp))
2406 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2407 tp->cp_cmd &= ~PCIDAC;
2408 RTL_W16(CPlusCmd, tp->cp_cmd);
2409 dev->features &= ~NETIF_F_HIGHDMA;
2410 }
2411
2412 rtl8169_hw_reset(ioaddr);
2413
2414 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2415 }
2416
2417 static void
2418 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2419 void __iomem *ioaddr)
2420 {
2421 unsigned int dirty_tx, tx_left;
2422
2423 assert(dev != NULL);
2424 assert(tp != NULL);
2425 assert(ioaddr != NULL);
2426
2427 dirty_tx = tp->dirty_tx;
2428 smp_rmb();
2429 tx_left = tp->cur_tx - dirty_tx;
2430
2431 while (tx_left > 0) {
2432 unsigned int entry = dirty_tx % NUM_TX_DESC;
2433 struct ring_info *tx_skb = tp->tx_skb + entry;
2434 u32 len = tx_skb->len;
2435 u32 status;
2436
2437 rmb();
2438 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2439 if (status & DescOwn)
2440 break;
2441
2442 tp->stats.tx_bytes += len;
2443 tp->stats.tx_packets++;
2444
2445 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2446
2447 if (status & LastFrag) {
2448 dev_kfree_skb_irq(tx_skb->skb);
2449 tx_skb->skb = NULL;
2450 }
2451 dirty_tx++;
2452 tx_left--;
2453 }
2454
2455 if (tp->dirty_tx != dirty_tx) {
2456 tp->dirty_tx = dirty_tx;
2457 smp_wmb();
2458 if (netif_queue_stopped(dev) &&
2459 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2460 netif_wake_queue(dev);
2461 }
2462 }
2463 }
2464
2465 static inline int rtl8169_fragmented_frame(u32 status)
2466 {
2467 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2468 }
2469
2470 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2471 {
2472 u32 opts1 = le32_to_cpu(desc->opts1);
2473 u32 status = opts1 & RxProtoMask;
2474
2475 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2476 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2477 ((status == RxProtoIP) && !(opts1 & IPFail)))
2478 skb->ip_summed = CHECKSUM_UNNECESSARY;
2479 else
2480 skb->ip_summed = CHECKSUM_NONE;
2481 }
2482
2483 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2484 struct RxDesc *desc, int rx_buf_sz,
2485 unsigned int align)
2486 {
2487 int ret = -1;
2488
2489 if (pkt_size < rx_copybreak) {
2490 struct sk_buff *skb;
2491
2492 skb = dev_alloc_skb(pkt_size + align);
2493 if (skb) {
2494 skb_reserve(skb, (align - 1) & (u32)skb->data);
2495 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
2496 *sk_buff = skb;
2497 rtl8169_mark_to_asic(desc, rx_buf_sz);
2498 ret = 0;
2499 }
2500 }
2501 return ret;
2502 }
2503
2504 static int
2505 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2506 void __iomem *ioaddr)
2507 {
2508 unsigned int cur_rx, rx_left;
2509 unsigned int delta, count;
2510
2511 assert(dev != NULL);
2512 assert(tp != NULL);
2513 assert(ioaddr != NULL);
2514
2515 cur_rx = tp->cur_rx;
2516 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2517 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2518
2519 for (; rx_left > 0; rx_left--, cur_rx++) {
2520 unsigned int entry = cur_rx % NUM_RX_DESC;
2521 struct RxDesc *desc = tp->RxDescArray + entry;
2522 u32 status;
2523
2524 rmb();
2525 status = le32_to_cpu(desc->opts1);
2526
2527 if (status & DescOwn)
2528 break;
2529 if (unlikely(status & RxRES)) {
2530 if (netif_msg_rx_err(tp)) {
2531 printk(KERN_INFO
2532 "%s: Rx ERROR. status = %08x\n",
2533 dev->name, status);
2534 }
2535 tp->stats.rx_errors++;
2536 if (status & (RxRWT | RxRUNT))
2537 tp->stats.rx_length_errors++;
2538 if (status & RxCRC)
2539 tp->stats.rx_crc_errors++;
2540 if (status & RxFOVF) {
2541 rtl8169_schedule_work(dev, rtl8169_reset_task);
2542 tp->stats.rx_fifo_errors++;
2543 }
2544 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2545 } else {
2546 struct sk_buff *skb = tp->Rx_skbuff[entry];
2547 int pkt_size = (status & 0x00001FFF) - 4;
2548 void (*pci_action)(struct pci_dev *, dma_addr_t,
2549 size_t, int) = pci_dma_sync_single_for_device;
2550
2551 /*
2552 * The driver does not support incoming fragmented
2553 * frames. They are seen as a symptom of over-mtu
2554 * sized frames.
2555 */
2556 if (unlikely(rtl8169_fragmented_frame(status))) {
2557 tp->stats.rx_dropped++;
2558 tp->stats.rx_length_errors++;
2559 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2560 continue;
2561 }
2562
2563 rtl8169_rx_csum(skb, desc);
2564
2565 pci_dma_sync_single_for_cpu(tp->pci_dev,
2566 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2567 PCI_DMA_FROMDEVICE);
2568
2569 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2570 tp->rx_buf_sz, tp->align)) {
2571 pci_action = pci_unmap_single;
2572 tp->Rx_skbuff[entry] = NULL;
2573 }
2574
2575 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2576 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2577
2578 skb->dev = dev;
2579 skb_put(skb, pkt_size);
2580 skb->protocol = eth_type_trans(skb, dev);
2581
2582 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2583 rtl8169_rx_skb(skb);
2584
2585 dev->last_rx = jiffies;
2586 tp->stats.rx_bytes += pkt_size;
2587 tp->stats.rx_packets++;
2588 }
2589 }
2590
2591 count = cur_rx - tp->cur_rx;
2592 tp->cur_rx = cur_rx;
2593
2594 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2595 if (!delta && count && netif_msg_intr(tp))
2596 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2597 tp->dirty_rx += delta;
2598
2599 /*
2600 * FIXME: until there is periodic timer to try and refill the ring,
2601 * a temporary shortage may definitely kill the Rx process.
2602 * - disable the asic to try and avoid an overflow and kick it again
2603 * after refill ?
2604 * - how do others driver handle this condition (Uh oh...).
2605 */
2606 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2607 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2608
2609 return count;
2610 }
2611
2612 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2613 static irqreturn_t
2614 rtl8169_interrupt(int irq, void *dev_instance)
2615 {
2616 struct net_device *dev = (struct net_device *) dev_instance;
2617 struct rtl8169_private *tp = netdev_priv(dev);
2618 int boguscnt = max_interrupt_work;
2619 void __iomem *ioaddr = tp->mmio_addr;
2620 int status;
2621 int handled = 0;
2622
2623 do {
2624 status = RTL_R16(IntrStatus);
2625
2626 /* hotplug/major error/no more work/shared irq */
2627 if ((status == 0xFFFF) || !status)
2628 break;
2629
2630 handled = 1;
2631
2632 if (unlikely(!netif_running(dev))) {
2633 rtl8169_asic_down(ioaddr);
2634 goto out;
2635 }
2636
2637 status &= tp->intr_mask;
2638 RTL_W16(IntrStatus,
2639 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2640
2641 if (!(status & rtl8169_intr_mask))
2642 break;
2643
2644 if (unlikely(status & SYSErr)) {
2645 rtl8169_pcierr_interrupt(dev);
2646 break;
2647 }
2648
2649 if (status & LinkChg)
2650 rtl8169_check_link_status(dev, tp, ioaddr);
2651
2652 #ifdef CONFIG_R8169_NAPI
2653 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2654 tp->intr_mask = ~rtl8169_napi_event;
2655
2656 if (likely(netif_rx_schedule_prep(dev)))
2657 __netif_rx_schedule(dev);
2658 else if (netif_msg_intr(tp)) {
2659 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2660 dev->name, status);
2661 }
2662 break;
2663 #else
2664 /* Rx interrupt */
2665 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2666 rtl8169_rx_interrupt(dev, tp, ioaddr);
2667 }
2668 /* Tx interrupt */
2669 if (status & (TxOK | TxErr))
2670 rtl8169_tx_interrupt(dev, tp, ioaddr);
2671 #endif
2672
2673 boguscnt--;
2674 } while (boguscnt > 0);
2675
2676 if (boguscnt <= 0) {
2677 if (netif_msg_intr(tp) && net_ratelimit() ) {
2678 printk(KERN_WARNING
2679 "%s: Too much work at interrupt!\n", dev->name);
2680 }
2681 /* Clear all interrupt sources. */
2682 RTL_W16(IntrStatus, 0xffff);
2683 }
2684 out:
2685 return IRQ_RETVAL(handled);
2686 }
2687
2688 #ifdef CONFIG_R8169_NAPI
2689 static int rtl8169_poll(struct net_device *dev, int *budget)
2690 {
2691 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2692 struct rtl8169_private *tp = netdev_priv(dev);
2693 void __iomem *ioaddr = tp->mmio_addr;
2694
2695 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2696 rtl8169_tx_interrupt(dev, tp, ioaddr);
2697
2698 *budget -= work_done;
2699 dev->quota -= work_done;
2700
2701 if (work_done < work_to_do) {
2702 netif_rx_complete(dev);
2703 tp->intr_mask = 0xffff;
2704 /*
2705 * 20040426: the barrier is not strictly required but the
2706 * behavior of the irq handler could be less predictable
2707 * without it. Btw, the lack of flush for the posted pci
2708 * write is safe - FR
2709 */
2710 smp_wmb();
2711 RTL_W16(IntrMask, rtl8169_intr_mask);
2712 }
2713
2714 return (work_done >= work_to_do);
2715 }
2716 #endif
2717
2718 static void rtl8169_down(struct net_device *dev)
2719 {
2720 struct rtl8169_private *tp = netdev_priv(dev);
2721 void __iomem *ioaddr = tp->mmio_addr;
2722 unsigned int poll_locked = 0;
2723 unsigned int intrmask;
2724
2725 rtl8169_delete_timer(dev);
2726
2727 netif_stop_queue(dev);
2728
2729 flush_scheduled_work();
2730
2731 core_down:
2732 spin_lock_irq(&tp->lock);
2733
2734 rtl8169_asic_down(ioaddr);
2735
2736 /* Update the error counts. */
2737 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2738 RTL_W32(RxMissed, 0);
2739
2740 spin_unlock_irq(&tp->lock);
2741
2742 synchronize_irq(dev->irq);
2743
2744 if (!poll_locked) {
2745 netif_poll_disable(dev);
2746 poll_locked++;
2747 }
2748
2749 /* Give a racing hard_start_xmit a few cycles to complete. */
2750 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2751
2752 /*
2753 * And now for the 50k$ question: are IRQ disabled or not ?
2754 *
2755 * Two paths lead here:
2756 * 1) dev->close
2757 * -> netif_running() is available to sync the current code and the
2758 * IRQ handler. See rtl8169_interrupt for details.
2759 * 2) dev->change_mtu
2760 * -> rtl8169_poll can not be issued again and re-enable the
2761 * interruptions. Let's simply issue the IRQ down sequence again.
2762 *
2763 * No loop if hotpluged or major error (0xffff).
2764 */
2765 intrmask = RTL_R16(IntrMask);
2766 if (intrmask && (intrmask != 0xffff))
2767 goto core_down;
2768
2769 rtl8169_tx_clear(tp);
2770
2771 rtl8169_rx_clear(tp);
2772 }
2773
2774 static int rtl8169_close(struct net_device *dev)
2775 {
2776 struct rtl8169_private *tp = netdev_priv(dev);
2777 struct pci_dev *pdev = tp->pci_dev;
2778
2779 rtl8169_down(dev);
2780
2781 free_irq(dev->irq, dev);
2782
2783 netif_poll_enable(dev);
2784
2785 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2786 tp->RxPhyAddr);
2787 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2788 tp->TxPhyAddr);
2789 tp->TxDescArray = NULL;
2790 tp->RxDescArray = NULL;
2791
2792 return 0;
2793 }
2794
2795 static void
2796 rtl8169_set_rx_mode(struct net_device *dev)
2797 {
2798 struct rtl8169_private *tp = netdev_priv(dev);
2799 void __iomem *ioaddr = tp->mmio_addr;
2800 unsigned long flags;
2801 u32 mc_filter[2]; /* Multicast hash filter */
2802 int i, rx_mode;
2803 u32 tmp = 0;
2804
2805 if (dev->flags & IFF_PROMISC) {
2806 /* Unconditionally log net taps. */
2807 if (netif_msg_link(tp)) {
2808 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2809 dev->name);
2810 }
2811 rx_mode =
2812 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2813 AcceptAllPhys;
2814 mc_filter[1] = mc_filter[0] = 0xffffffff;
2815 } else if ((dev->mc_count > multicast_filter_limit)
2816 || (dev->flags & IFF_ALLMULTI)) {
2817 /* Too many to filter perfectly -- accept all multicasts. */
2818 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2819 mc_filter[1] = mc_filter[0] = 0xffffffff;
2820 } else {
2821 struct dev_mc_list *mclist;
2822 rx_mode = AcceptBroadcast | AcceptMyPhys;
2823 mc_filter[1] = mc_filter[0] = 0;
2824 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2825 i++, mclist = mclist->next) {
2826 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2827 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2828 rx_mode |= AcceptMulticast;
2829 }
2830 }
2831
2832 spin_lock_irqsave(&tp->lock, flags);
2833
2834 tmp = rtl8169_rx_config | rx_mode |
2835 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2836
2837 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2838 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2839 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2840 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2841 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2842 mc_filter[0] = 0xffffffff;
2843 mc_filter[1] = 0xffffffff;
2844 }
2845
2846 RTL_W32(RxConfig, tmp);
2847 RTL_W32(MAR0 + 0, mc_filter[0]);
2848 RTL_W32(MAR0 + 4, mc_filter[1]);
2849
2850 spin_unlock_irqrestore(&tp->lock, flags);
2851 }
2852
2853 /**
2854 * rtl8169_get_stats - Get rtl8169 read/write statistics
2855 * @dev: The Ethernet Device to get statistics for
2856 *
2857 * Get TX/RX statistics for rtl8169
2858 */
2859 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2860 {
2861 struct rtl8169_private *tp = netdev_priv(dev);
2862 void __iomem *ioaddr = tp->mmio_addr;
2863 unsigned long flags;
2864
2865 if (netif_running(dev)) {
2866 spin_lock_irqsave(&tp->lock, flags);
2867 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2868 RTL_W32(RxMissed, 0);
2869 spin_unlock_irqrestore(&tp->lock, flags);
2870 }
2871
2872 return &tp->stats;
2873 }
2874
2875 #ifdef CONFIG_PM
2876
2877 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2878 {
2879 struct net_device *dev = pci_get_drvdata(pdev);
2880 struct rtl8169_private *tp = netdev_priv(dev);
2881 void __iomem *ioaddr = tp->mmio_addr;
2882
2883 if (!netif_running(dev))
2884 goto out;
2885
2886 netif_device_detach(dev);
2887 netif_stop_queue(dev);
2888
2889 spin_lock_irq(&tp->lock);
2890
2891 rtl8169_asic_down(ioaddr);
2892
2893 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2894 RTL_W32(RxMissed, 0);
2895
2896 spin_unlock_irq(&tp->lock);
2897
2898 pci_save_state(pdev);
2899 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2900 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2901 out:
2902 return 0;
2903 }
2904
2905 static int rtl8169_resume(struct pci_dev *pdev)
2906 {
2907 struct net_device *dev = pci_get_drvdata(pdev);
2908
2909 if (!netif_running(dev))
2910 goto out;
2911
2912 netif_device_attach(dev);
2913
2914 pci_set_power_state(pdev, PCI_D0);
2915 pci_restore_state(pdev);
2916 pci_enable_wake(pdev, PCI_D0, 0);
2917
2918 rtl8169_schedule_work(dev, rtl8169_reset_task);
2919 out:
2920 return 0;
2921 }
2922
2923 #endif /* CONFIG_PM */
2924
2925 static struct pci_driver rtl8169_pci_driver = {
2926 .name = MODULENAME,
2927 .id_table = rtl8169_pci_tbl,
2928 .probe = rtl8169_init_one,
2929 .remove = __devexit_p(rtl8169_remove_one),
2930 #ifdef CONFIG_PM
2931 .suspend = rtl8169_suspend,
2932 .resume = rtl8169_resume,
2933 #endif
2934 };
2935
2936 static int __init
2937 rtl8169_init_module(void)
2938 {
2939 return pci_register_driver(&rtl8169_pci_driver);
2940 }
2941
2942 static void __exit
2943 rtl8169_cleanup_module(void)
2944 {
2945 pci_unregister_driver(&rtl8169_pci_driver);
2946 }
2947
2948 module_init(rtl8169_init_module);
2949 module_exit(rtl8169_cleanup_module);
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